The Behavior Analysis of Flash Memory Storage

Systems

The Behavior Analysis of Flash Memory Storage

Systems

Po-Chun Huang, Yuan-Hao Chang, Tei-Wei Kuo, Jen-Wei Hsieh

Dept. of Comp. Sci. & Info. Engr.National Taiwan University, Taiwan

Agenda

Introduction

Flash-Memory Characteristics

Behavior Analysis

Conclusion

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Introduction – Why Flash Memory

Diversified Application Domains

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Mobile Media Players

Mobile Media Players

Solid-State Disks (SSD)

Solid-State Disks (SSD)

Thumb Disks

Thumb Disks

Multimedia Memory Cards

Multimedia Memory Cards

Embedded Systems

Embedded Systems

Introduction – NAND-Type Flash Makers

http://hugoleijtens.spaces.live.com/blog/cns!4B94B7453D4BFD9E!988.entry

Source: iSuppli Corp (Unit: Million Dollars)

[EE Times,11/30/2007] NAND flash prices have dropped by an average of more than 40 % per year.

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Flash Memory Characteristics – A Typical Architecture

……

Block 0

Block 1

Block 2

Block 3

Erase one blockErase one block

1 Page = 2KB1 Block = 64 pages(128KB)

……

Write one pageWrite one page

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Flash Memory Characteristics –Access ConstraintsWrite-Once

– No writing on the same page unless its residing block is erased!

– Pages are classified into valid, invalid, and free pages.

Bulk-Erasing – Pages are erased in a block unit to recycle used but

invalid pages.

Wear-Leveling– Each block has a limited lifetime in erasing counts.

Flash Memory Characteristics – NOR-type & NAND-type

NOR-type NAND-type

Access Unit Byte (Random Read, Sequential Write)

Page (Serial Access)

Cost Higher Lower

XIP Support Yes No

Write 8MB/s 20MB/s

PurposeXIP media (such as EPROM, EEPROM, EAROM, and DRAM)

Nonvolatile secondary storage media (such as Hard disk)

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Flash Memory Characteristics – Small and Large Block Flash MemoryFlash memory page and block sizes are growing

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Small Block Large Block

Page Size 512+16 Bytes 2K~8K Bytes

Block Size 16K Bytes 128K~256K Bytes

Used for... <1G Bytes >1G Bytes

Throughput Low High

Small Block Now Switches to Large Block

Introduction (cont’d)Single-Level-Cell and Multi-Level Cell Flash Memory

MLC has gained its momentum in cost and capacity!

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SLC Flash MLC Flash

Cell Level 1 2 or 4

Cost 17.2 USD / 16G Bytes 5.25 USD / 16G Bytes

Chip Density Lower Higher

Access Speed Higher Lower

Average Cell Endurance 104~105 W-E cycles* 103~104 W-E cycles

Partial Programming Yes (4 times) No (1 time)

Sequential Utilization Constraint of Pages in a Block No Yes

*Write-Erase Cycles

Flash-Memory Characteristics – Hard Disks versus Flash Memory

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Hard Disk (NAND-type) Flash Memory

Access Granularity Page-based Access Page-based Access

Write-once No Yes

Erasure No Need to Erase Bulk Erasure

Medium Lifetime Very Long Median

Cost Lower Higher

Other Properties and Constraints

•Long seek time and rotational latency•Power-hunger•Spin-up latency

•Shock resistance•High density

Flash-Memory Characteristics – System ArchitectureIn order to address the special properties and constraints of flash

memory, a good management scheme is required

Typical forms of management schemes are implemented as the Flash Translation Layer (FTL), the driver, or the Flash File System (FFS), each with different design considerations

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Flash-Memory Characteristics – System ArchitectureA Typical Flash Memory Management Scheme

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Perform Address Translation from LBA to PBA

Perform Address Translation from LBA to PBA

Determine the Physical Position of Written Data

Determine the Physical Position of Written Data

Because of the Write-Once Property, We Must Perform Garbage Collection Task to Released the Space Occupied by Invalidated Data

Because of the Write-Once Property, We Must Perform Garbage Collection Task to Released the Space Occupied by Invalidated Data

Garbage Collector Requires This Facility

Garbage Collector Requires This Facility

Even the Times of Utilization of Each Block to Avoid Fast Corruption

Even the Times of Utilization of Each Block to Avoid Fast Corruption

Behavior Analysis – Motivation

Physical properties of flash memory are very different from those of hard drives.

The management schemes give flash-memory storage systems special behaviors, compared to in-place update policies of many other storage systems.

There are few benchmarking tools with the considerations of the physical properties and the management schemes of flash memory.

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Behavior Analysis – MotivationViews of a Flash Memory Storage System

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User-PerspectiveUser-Perspective

Architecture-Perspective

Architecture-Perspective

Hardware-Perspective

Hardware-Perspective

Operation response time or throughput, product functional life span, file system operation latencies, prices, and compatibility

Operation response time or throughput, product functional life span, file system operation latencies, prices, and compatibility

Maintenance resources, assembly costs, architecture, and mediation between user expectation, hardware functions, and the flash management scheme

Maintenance resources, assembly costs, architecture, and mediation between user expectation, hardware functions, and the flash management scheme

production costs, materials, technology, cell reliability, etc.

production costs, materials, technology, cell reliability, etc.

Behavior Analysis – MotivationRevisiting of Existing I/O benchmarks

– IOZone: a file system benchmark considering no flash properties (http://www.iozone.org/)

– IOMeter: synthetic benchmark that users can control the degree of random-sequential access mixture. Does not consider flash properties (http://www.iometer.org)

– The effective I/O bandwidth benchmark: examine the I/O bandwidth achievable of an I/O device (http://www.hlrs.de/organization/par/services/models/mpi/b_eff_io/index_v1.2.html)

– IOBench: An operating system and processor independent synthetic input/output (IO) benchmark designed to put a configurable IO and processor (CP) load on the system under test (http://portal.acm.org/citation.cfm?id=71302.71309)

– Bonnie++: a benchmark suite that is aimed at performing a number of simple tests of hard drive and file system performance (http://www.coker.com.au/bonnie++/)

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Behavior Analysis – Motivation

Unfortunately,–Physical properties of flash memory are different

from hard drives

–There are few benchmarking tools including the consideration of the management schemes of flash memory storage systems

–All previous works are based on user-perspective and consider no flash-specific properties and management overheads

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Behavior Analysis

We need an evaluation strategy considering both the user and system architecture’s perspectives, so that–Users can fairly evaluate the cost-effectiveness

of various flash products

–System architects can have a fair method to evaluate their designs on architectures or the flash management schemes

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The Behavior AnalysisOur Approach

–Micro-benchmark: evaluate specific metrics (instead of the overall status) of the system

- Best-case throughput

- Worst-case response time

–Macro-benchmark: probe the actual macroscopic behaviors of the systems- Read disturbance effects

- Write disturbance effects

- Simulation of actual traces

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The Behavior AnalysisBest-Case Throughput Test: It is to examine the maximum possible performance of the device– Large, sequential accesses yield the best performance on

many FTLs

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ith access

LBA Largest request packet length (1024 sectors on Windows; 128 sectors on USB interface)

The Behavior AnalysisWorst-Case Response Time Test: It is to examine the real-time access capability of a device– Small, random accesses yield the worst performance on

many FTLs

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LBALBA

iithth access access

The Behavior AnalysisRead-Disturb Effect Test: It is to test the management

overheads about the read-disturb effect– Repetitively read a small range of data to examine the write

disturbance overhead– The first phase is only used to write the data that will be read later

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LBA

ith access

Phase-1(Preparation)

Phase-2(Actual Test)

Hot area(test area)

Write the data for Future Read

Write the data for Future Read

Monitor the Performance Drop Continuously

Monitor the Performance Drop Continuously

Fill the Cache with Irrelevant Data to Avoid the Caching Effects

Fill the Cache with Irrelevant Data to Avoid the Caching Effects

The Behavior AnalysisWrite-Disturb Effect Test: It is to test the management

overheads about the write-disturb effect– Repetitively write to a small range of data to examine the write-disturb

overhead

– Accesses to other addresses are used to eliminate the caching effect

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LBA

ith access

Hot area(test area)

Hot area(test area)

The Behavior AnalysisMultimedia environment: multimedia cards, thumb disks,

and SSDs are often used to keep multimedia contents– The contents of audio or video files are generally sequentially

accessed, while their metadata are randomly accessed

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ith access

LBA

Metadata Area(Randomly Accessed)

Data Area(Sequentially Accessed)

Similar to the Behaviors of FAT

Similar to the Behaviors of FAT

The Behavior AnalysisMultiplexed environment: A large number of different

applications mixed together in multi-purpose systems – The behaviors are affected by a large number of factors, forming a

pattern following normal distribution

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LBA

ith access

Random Starting Address

Random Starting Address

Random Access Length

Random Access Length

About the Timing of Request IssuingThe time intervals between consecutive requests matters– Foreground management

- Handle the requests on-demand

- Introduce user-sensible delays

– Background management- Handle some management tasks on system idle time

- Is not always applicable; for example, read requests must be served on-demand

If the interval between requests is large, background management will yield better performance, while foreground won’t

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Conclusion and Future Work

Conclusion– In this paper, we provide a fair evaluation strategy for

flash memory storage systems so that- Users can evaluate the cost-effectiveness of various flash

products- Designers can evaluate the pros and cons of their designs and

improve them

Future Work– Investigate the relationship among different access

patterns, system architectures, and flash memory management schemes

– Analysis the access patterns of various applications of flash memory in the next generation

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Contact Information

Po-Chun Huang, Ph.D. Student – Advisor: Prof. Tei-Wei Kuo

– Mail & MSN: b91048@csie.ntu.edu.tw

– Flash Research Group: http://newslab.csie.ntu.edu.tw/~flash/

– Office: +886-2-33664888#438

– Fax: +886-2-23628167

– Address: Dept. of Computer Science & Information Engr.National Taiwan University, Taipei, Taiwan 106

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Q & A

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