Slide Set 4 Layout and Design Rulescourses.ece.ubc.ca/elec402/handouts/s4_1up.pdfSlide Set 4, Page 2...
Transcript of Slide Set 4 Layout and Design Rulescourses.ece.ubc.ca/elec402/handouts/s4_1up.pdfSlide Set 4, Page 2...
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Slide Set 4, Page 1
Slide Set 4
Layout and Design Rules
Steve WiltonDept. of ECE
University of British [email protected]
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Overview
• Reading– Wolf 2.5, 2.6
• IntroductionThe fabrication discussion from last lecture motivates the design rules that need to be followed for layout. In this lecture, we describe a simple layout editor called Magic. This tool is relatively easy to learn and use, and serves as a good tool for layout courses such as EECE479. The different layers and contacts for CMOS designs are described and this leads to a discussion of the design rules needed when laying out integrated circuits. Finally, some methods of estimating the sizes of stick diagrams are presented as the rule of 8λ.
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Specifying What to Build
• Now that we know what fabrication is trying to do, how do we tell them precisely what to build? We create a layout (GDS II data)
• We don’t care about the real details of the fab, but we have to define the patterning of the layers (that meet the design rules) to specify our design.
• Sometimes knowing more about the fab details is useful when you need to debug a part.
Designer FoundryLayout
(Mask Set)
Design RulesProcess Parameters
“tapeout”
Step 1
Step 2
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MAGIC Layout Editor
The different layers that a designer uses is generally set by theCAD tool.
Our layout editor is ‘Magic’– Magic is quick to learn and commonly available.– Primarily Paint (Color)-based, not object-based.– Highlighting of Electrically connected paint.– Interactive DRC checking.
We will use the SCMOS design technology with Magic
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Laying out an NMOS
polysiliconndiffusion
polysilicon
ndiffusion
metal1
ndcontact
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Laying out a PMOS
polysilicon
pdiffusion
metal1
pdcontact
nwell
polysilicon
pdiffusion
nwell
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Connections and Vias
polysilicon
polycontact metal1
metal1
m2contact metal2
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P-substrate contacts
Need to connect substrate to ground fairly often (at least once percell). Do this with a psubstratepcontact
metal-1 (connected toground)
psubstratepcontact
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P-substrate Contacts
Sometimes, people combine their substrate contacts andNMOS transistors (likely, the source of many NMOS transistors areconnected to ground).
Remember you only need to do this once per cell.
metal1 (connected toground)
psubstratepcontact
ndcontact
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N-Well Contacts
Must also tie each Nwell to Vdd (about once per cell):
metal1 (connected to Vdd)
nsubstratencontact
nwell
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N-Well Contacts
Can also combine N-Well contacts with a PMOS transistor:
nsubstratencontact
pdcontact
metal1 (connected to Vdd)
nwell
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The best way to understand layout is to look at someexisting layouts. In Assignment 2, you are given a cellcalled mystery.mag. Look at it very closely to understandhow things are drawn and connected.
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Pentium: First Poly Layer
Source: M.W. Davidson, FSU © 1995-2001
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Pentium: Second Poly Layer
Source: M.W. Davidson, FSU © 1995-2001
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Pentium: Metal Layer
Source: M.W. Davidson, FSU © 1995-2001
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Pentium: Contact Layer
Source: M.W. Davidson, FSU © 1995-2001
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Fabrication Constraints on Layout
Fabrication places many constraints on the layout • In EECE479 we will worry about the two main types of
constraints:– Resolution constraints (within one layer)
– What is the smallest width feature than can be printed– What is the smallest spacing that will guarantee no shorts
• Depends on lithography and processing steps that follow• Resolution often depends on the smoothness of the surface
– Most modern processes are planarized, to keep surface flat– Alignment/overlap constraints (between two layers)
• Like printing a color picture, need to align layers to each other• Mostly for contacts and poly overhang into diffusion
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Design Rules
• Most processes have design rules that are expressed in absolute physical units– poly width 0.3µm– poly spacing 0.3µm– metal width 0.5µm– metal spacing 0.5µm
• Typically not multiples of one another
• Using process-specific design rules gives the densest layout but is difficult to master
• We will express our design rules in lambda (λ) units– λ is half the drawn gate
length (poly width)– All other design rules are
expressed in whole multiples of λ
• poly width 2 λ, space 3 λ• metal width, space 3 λ
– usually requires rounding up– rules are scaled to generate
masks for a variety of processes
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SCMOS Lambda (λ) Design Rules
We will be using the SCMOS design rules– They are a simplified set of rules– Allow you to send your designs to a number of fab lines– Rules are based on λ, a type of scaling constant– λ was initially 1.5 µ, and now it is 0.030 µ in advanced fab lines
Ignores some of the ways to save area (so extra conservative)– Use only Manhattan Layouts– Use only 90o angles
Companies regularly do design scaling, even if they don’t use the symbol λ
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Geometric Design Rules
• Resolution– width and spacing of lines
on one layer• Alignment
– to make sure interacting layers overlap (or don’t)
• Examples– poly overlap of diff – contact surround– well surround of diff– contact spacing to unrelated
geometry
3λ3λ3λ3λ3λ
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SCMOS Design Rule Highlights
Resolution rules:
LAYER WIDTH SPACE
poly 2 3
diff 3 3
metal1 3 3
metal2 3 4
nwell 10 9
cut 2 2
via 2 3
Alignment rules:
cut/via surround 1
poly overlap diff 2
poly space to diff 1
Notes:
contact cut plus surround is 4λ
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Using the Design Rules
While the Magic SCMOS design rules are simplified, there are still a number of rules to remember. A good way to start is to begin with a stick diagram of the cell you want to layout. Then you can use a subset of the rules to estimate what the layout will look like, and if it meets your standards you can begin the actual layout. While Magic makes layout easier, it always a good idea to have a plan on where things go before you start.
Warning:While layout is often (sometimes) fun to do, it easily can be become an infinite time sink – one can always find a way to shrink the cell a few more microns. You should really have a plan BEFORE you start layout, and have a set constraints you are trying to achieve so you know when you are done.
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Layout Guidelines
In CMOS there are two types of diffusion• ndiff (green)
– Poly crossing ndiff makes nMOS transistors• pdiff (yellow / brown)
– Poly crossing pdiff makes pMOS transistorsBe careful, ndiff and pdiff are different• You can’t directly connect ndiff to pdiff
– Must connect ndiff to metal and then metal to pdiff• Can’t get ndiff too close to pdiff because of wells
– Large spacing rule between ndiff and pdiff– Means you need to group nMOS devices together and
pMOS devices together• Can’t connect poly directly to M2 -- must use M1 to reach M2
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Basic Layout Planning
Here are a few more simple guidelines to CMOS layouts:
• You need to route power and ground (using metal)– often power and ground is run horizontally
• Try to keep nMOS devices near nMOS devices and pMOSdevices near pMOS devices.– So nMOS usually are placed near Gnd, and pMOS near Vdd
• Run poly vertically and diffusion horizontally, with metal1 horizontal (or the reverse, just keep them orthogonal)
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Basic Layout Planning
Here are a few more simple guidelines to CMOS layouts:
• Keep diffusion wires as short as possible (just connect to transistor)
• All long wires (wire that go outside a cell, for example) should be in either m1 or m2.
• Try to design/layout as little stuff as possible (use repetition/tools)
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Typical Cell Layout Plan
A A_b
Vdd
Gnd
CMOS Inverter (this is actually two in series)
Even
Odd
A A_b
Even Out
Odd Out
Parity Circuit (from earlier).
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What I will show you next are some rules of thumb for estimating the size of a layout from a sticks diagram
You might want to do this if you are “floorplanning” your project (deciding how big each block will be and how they will fit together) before assigning each block to a group member
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Definition: Pitch
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Definition: Pitch
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Definition: Pitch
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Definition: Pitch
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Definition: Pitch
In this case, the “pitch” is equal to 6λ
If we have n metal lines, their height is approximately (n*pitch)
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Minor Complication
We rarely can put metal lines so close together.The reason is: we often need to connect the metal linesto something (eg. poly) at some point.
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Minor Complication (continued…)
But, from our design rules, “contact cut plus surround” = 4 λ
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Minor Complication (continued…)
Worst case pitch is now 7 λ
This is called “fully contacted”pitch
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Minor Complication (continued…)
Worst case pitch is now 6.5 λ
(can you see why this is?)
This is called “semi-contacted”pitch
Of course, a smart engineer (e.g. you) might choose to “stagger”the connections to compact things a bit more
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Summary of metal pitch:
Metal-1
No contacts: 6λ
Fully Contacted Pitch: 7λ
Semi-Contacted Pitch: 6.5λ
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Summary of metal pitch:
Metal-1 Metal-2
No contacts: 6λ 7λ
Fully Contacted Pitch: 7λ 8λ
Semi-Contacted Pitch: 6.5λ 7.5λ
When we are estimating the size of a cell, let’s use 8λ as a quick estimate of pitch
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Example: if we have a cell that has 64 wires in parallel, the height of this cell would be approximately 8 λ * 64 = 512 λ
Approximately 512 λ
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What about Transistors?
These also approximately fit on this 8 λ grid:
Approximately 8λ
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The “Rule of 8’s”: When estimating size, everything is 8 λ
This obviously is not exactly correct, but it will give you a rough idea how big your cell is very quickly.
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Example of Size Estimation: Parity Circuit
8 * (3 tall +1 for space to next cell) = 32λ tall
8 * (3 wide +1 for space to next cell) = 32λ wide
8
8
8
88888
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One more wrinkle…
This approximation assumes that all wires and transistors are of the minimum size.
For wires, this is usually the case (except for power/ground lines…but we’ll talk about that later)
As we will see, however, transistors are often considerably wider than their minimum…. (example on next slide)
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Example of Size Estimation: Parity Circuit
If we know the transistors are wider, we can add a little bit to the height of the cell. How much do we add?
-> Add x, where x is the difference between the actual width and minimum width
![Page 45: Slide Set 4 Layout and Design Rulescourses.ece.ubc.ca/elec402/handouts/s4_1up.pdfSlide Set 4, Page 2 Overview • Reading – Wolf 2.5, 2.6 • Introduction The fabrication discussion](https://reader033.fdocuments.us/reader033/viewer/2022050311/5f72d668b1754d1f51198cac/html5/thumbnails/45.jpg)
Slide Set 4, Page 45
Size Estimation Summary
Don’t get too stressed out about getting your size estimations correct.
This is just a tool that might help youwhen are doing your initial layout planning.
As you get more experience, you willbe able to come up with more accurate estimates faster. It just takes practice.