Sketched oxide single-electron transistor

5
Sketched oxide single-electron transistor Guanglei Cheng 1 , Pablo F. Siles 2,3 , Feng Bi 1 , Cheng Cen 1 , Daniela F. Bogorin 1 , Chung Wung Bark 4 , Chad M. Folkman 4 , Jae-Wan Park 4 , Chang-Beom Eom 4 , Gilberto Medeiros-Ribeiro 5 and Jeremy Levy 1 * Devices that confine and process single electrons represent an important scaling limit of electronics 1,2 . Such devices have been realized in a variety of materials and exhibit remarkable elec- tronic, optical and spintronic properties 3–5 . Here, we use an atomic force microscope tip to reversibly ‘sketch’ single-elec- tron transistors by controlling a metal–insulator transition at the interface of two oxides 6–8 . In these devices, single electrons tunnel resonantly between source and drain electrodes through a conducting oxide island with a diameter of 1.5 nm. We demonstrate control over the number of electrons on the island using bottom- and side-gate electrodes, and observe hysteresis in electron occupation that is attributed to ferroelec- tricity within the oxide heterostructure. These single-electron devices may find use as ultradense non-volatile memories, nanoscale hybrid piezoelectric and charge sensors, as well as building blocks in quantum information processing and simulation platforms. The discovery of a high-mobility quasi-two-dimensional electron gas (q-2DEG) at the interface of two insulating oxides, TiO 2 -termi- nated SrTiO 3 and LaAlO 3 (ref. 6), has stimulated interest in the development of oxide-based electronics. The transition between insulating and conducting states in this system is an atomically sharp function of the number of LaAlO 3 unit cells 7 . At or below a thickness of three unit cells of LaAlO 3 , the interface is insulating, but for four or more unit cells the interface is conducting. The con- ductance of films grown at a critical thickness (three-unit-cell LaAlO 3 /SrTiO 3 ) can be locally and reversibly controlled using a conductive atomic force microscope (c-AFM) probe technique 8 . Positive voltages applied to the c-AFM tip locally switch the three-unit-cell LaAlO 3 /SrTiO 3 interface to a conducting state, and negative voltages locally restore the insulating state. The writing mechanism is believed to be governed by a ‘water cycle’ 9 in which the top LaAlO 3 surface is locally charged through hydrogen pas- sivation, resulting in high-resolution modulation doping of the LaAlO 3 /SrTiO 3 interface. Using this technique, it is possible to create nanowires as small as 2 nm wide (ref. 10), islands as small as 1 nm in diameter (ref. 10), tunnel barriers 10 , rectifying junctions 11 , ‘SketchFET’ transistors 10 and photoconductive switches 12 with com- parably small dimensions. Cryogenic operation of these devices 13 raises the possibility that single-electron devices may also be created. Here, we report the creation and electronic characterization of a ferroelectric sketch-based single-electron transistor (SketchSET) at the three-unit-cell LaAlO 3 /SrTiO 3 interface. These devices were created using the same c-AFM lithography technique presented in ref. 8. SketchSET devices can be created in a variety of ways, one of which is illustrated in Fig. 1a,b. Two crossed nanowires are written at the LaAlO 3 /SrTiO 3 interface to a conducting state. The c-AFM tip is then positioned at the intersection, and an erase pulse is applied (duration, t b ; tip voltage, V tip ¼ V erase , 0), followed by a brief positive pulse (duration, t d ; V tip ¼ V write . 0). This pro- cedure creates an ultrasmall island that behaves as a quantum dot at the intersection. The quantum dot is surrounded by an insulating barrier and is separated from the four nanowires by a narrow tunnel barrier. The centre island, produced by a 10 ms write pulse, is esti- mated to have a diameter d of 1.5 nm, based on a calibration of the writing process performed on the same sample (see Supplementary Information). One can roughly estimate the number N of electrons able to reside within the quantum dot, based on typical two-dimen- sional carrier densities for nanoscale writing (n 5 × 10 13 cm 22 ) at the LaAlO 3 /SrTiO 3 interface: N ¼ pd 2 n/4 1 electron. This esti- mate agrees well with the observed behaviour, described in detail below. Electrical transport experiments were performed on six different devices, including one control structure on which no island was written. Here, we describe the results obtained for three devices (A, B and C), which were created using the parameters described in Supplementary Table S1 and Fig. S2. The experiments focus on the effect of the side gates (V g1 and V g2 ) and back gate (V gb ) on the source–drain differential conductance (G sd ) and capacitance (C sd ). Figure 1c shows the differential conductance curve for device A immediately after cooldown, with the side gates and V gb all grounded, and the drain V d (where current is measured) held at virtual ground. For sufficiently small source– drain voltage (V sd ), the differential conductance is strongly suppressed, and increases rapidly above a well-defined threshold. Although the structure is nominally symmetric, the threshold for positive and negative V sd is generally different owing to hard- to-control variations at the scale of 1 nm. Figure 1c shows two clearly resolved Coulomb peaks for V sd , 0, and another three for V sd . 0 before being obscured by the large conducting background. Subsequent voltage cycles resulted in fewer peaks (Fig. 2a). Structures that do not have islands at the intersec- tion (such as SketchFET devices 13 ) do not exhibit any Coulomb peaks. Here, we focus on transport for SketchSET devices in the low- conductance regime. Figure 2a,b shows the differential conductance G sd and capacitance C sd of device A as a function of temperature (16–40 K) and source–drain voltage V sd (–0.3 V to 0.3 V), with all three side gates and the back gate grounded. The conductance exhi- bits distinct Coulomb peaks, which are associated with resonant tunnelling into the quantum dot (Supplementary Fig. S3). Coinciding with these conductance peaks are abrupt changes in capacitance. Generally, increases in quantum dot occupancy DN ¼ 1 are associated with roughly constant capacitance jumps DC (see also Fig. 4). In the blue shadowed regime in Fig. 2b, the con- ductance is negligible and the capacitance, C sd , DC, is insensitive to V sd . For these reasons, we infer that N ¼ 0 electrons are contained in the quantum dot in this regime. 1 Department of Physics and Astronomy, University of Pittsburgh, Pittsburgh, Pennsylvania 15260, USA, 2 Laborato ´rio Nacional de Luz Sı ´ncrotron, Caixa Postal 6192, 13083-970 Campinas SP, Brazil, 3 Instituto de Fı ´sica ‘Gleb Wataghin’, Universidade Estadual de Campinas-UNICAMP, Campinas SP, Brazil, 4 Department of Materials Science and Engineering, University of Wisconsin-Madison, Madison, Wisconsin 53706, USA, 5 Hewlett Packard Laboratories, 1501 Page Mill Road, Palo Alto, California 94304, USA. *e-mail: [email protected] LETTERS PUBLISHED ONLINE: 17 APRIL 2011 | DOI: 10.1038/NNANO.2011.56 NATURE NANOTECHNOLOGY | ADVANCE ONLINE PUBLICATION | www.nature.com/naturenanotechnology 1 © 2011 Macmillan Publishers Limited. All rights reserved.

Transcript of Sketched oxide single-electron transistor

Page 1: Sketched oxide single-electron transistor

Sketched oxide single-electron transistorGuanglei Cheng1, Pablo F. Siles2,3, Feng Bi1, Cheng Cen1, Daniela F. Bogorin1, Chung Wung Bark4,

Chad M. Folkman4, Jae-Wan Park4, Chang-Beom Eom4, Gilberto Medeiros-Ribeiro5 and Jeremy Levy1*

Devices that confine and process single electrons represent animportant scaling limit of electronics1,2. Such devices have beenrealized in a variety of materials and exhibit remarkable elec-tronic, optical and spintronic properties3–5. Here, we use anatomic force microscope tip to reversibly ‘sketch’ single-elec-tron transistors by controlling a metal–insulator transition atthe interface of two oxides6–8. In these devices, single electronstunnel resonantly between source and drain electrodes througha conducting oxide island with a diameter of ∼1.5 nm. Wedemonstrate control over the number of electrons on theisland using bottom- and side-gate electrodes, and observehysteresis in electron occupation that is attributed to ferroelec-tricity within the oxide heterostructure. These single-electrondevices may find use as ultradense non-volatile memories,nanoscale hybrid piezoelectric and charge sensors, as well asbuilding blocks in quantum information processing andsimulation platforms.

The discovery of a high-mobility quasi-two-dimensional electrongas (q-2DEG) at the interface of two insulating oxides, TiO2-termi-nated SrTiO3 and LaAlO3 (ref. 6), has stimulated interest in thedevelopment of oxide-based electronics. The transition betweeninsulating and conducting states in this system is an atomicallysharp function of the number of LaAlO3 unit cells7. At or below athickness of three unit cells of LaAlO3, the interface is insulating,but for four or more unit cells the interface is conducting. The con-ductance of films grown at a critical thickness (three-unit-cellLaAlO3/SrTiO3) can be locally and reversibly controlled using aconductive atomic force microscope (c-AFM) probe technique8.Positive voltages applied to the c-AFM tip locally switch thethree-unit-cell LaAlO3/SrTiO3 interface to a conducting state, andnegative voltages locally restore the insulating state. The writingmechanism is believed to be governed by a ‘water cycle’9 in whichthe top LaAlO3 surface is locally charged through hydrogen pas-sivation, resulting in high-resolution modulation doping of theLaAlO3/SrTiO3 interface. Using this technique, it is possible tocreate nanowires as small as 2 nm wide (ref. 10), islands as small as1 nm in diameter (ref. 10), tunnel barriers10, rectifying junctions11,‘SketchFET’ transistors10 and photoconductive switches12 with com-parably small dimensions. Cryogenic operation of these devices13

raises the possibility that single-electron devices may also be created.Here, we report the creation and electronic characterization of a

ferroelectric sketch-based single-electron transistor (SketchSET) atthe three-unit-cell LaAlO3/SrTiO3 interface. These devices werecreated using the same c-AFM lithography technique presented inref. 8. SketchSET devices can be created in a variety of ways, oneof which is illustrated in Fig. 1a,b. Two crossed nanowires arewritten at the LaAlO3/SrTiO3 interface to a conducting state. Thec-AFM tip is then positioned at the intersection, and an erasepulse is applied (duration, tb; tip voltage, Vtip¼ Verase , 0), followed

by a brief positive pulse (duration, td; Vtip¼ Vwrite . 0). This pro-cedure creates an ultrasmall island that behaves as a quantum dotat the intersection. The quantum dot is surrounded by an insulatingbarrier and is separated from the four nanowires by a narrow tunnelbarrier. The centre island, produced by a 10 ms write pulse, is esti-mated to have a diameter d of �1.5 nm, based on a calibration of thewriting process performed on the same sample (see SupplementaryInformation). One can roughly estimate the number N of electronsable to reside within the quantum dot, based on typical two-dimen-sional carrier densities for nanoscale writing (n ≈ 5 × 1013 cm22) atthe LaAlO3/SrTiO3 interface: N¼ pd2n/4 ≈ 1 electron. This esti-mate agrees well with the observed behaviour, described indetail below.

Electrical transport experiments were performed on six differentdevices, including one control structure on which no island waswritten. Here, we describe the results obtained for three devices(A, B and C), which were created using the parametersdescribed in Supplementary Table S1 and Fig. S2. The experimentsfocus on the effect of the side gates (Vg1 and Vg2) and back gate(Vgb) on the source–drain differential conductance (Gsd) andcapacitance (Csd). Figure 1c shows the differential conductancecurve for device A immediately after cooldown, with the sidegates and Vgb all grounded, and the drain Vd (where current ismeasured) held at virtual ground. For sufficiently small source–drain voltage (Vsd), the differential conductance is stronglysuppressed, and increases rapidly above a well-defined threshold.Although the structure is nominally symmetric, the thresholdfor positive and negative Vsd is generally different owing to hard-to-control variations at the scale of �1 nm. Figure 1c shows twoclearly resolved Coulomb peaks for Vsd , 0, and another threefor Vsd . 0 before being obscured by the large conductingbackground. Subsequent voltage cycles resulted in fewerpeaks (Fig. 2a). Structures that do not have islands at the intersec-tion (such as SketchFET devices13) do not exhibit anyCoulomb peaks.

Here, we focus on transport for SketchSET devices in the low-conductance regime. Figure 2a,b shows the differential conductanceGsd and capacitance Csd of device A as a function of temperature(16–40 K) and source–drain voltage Vsd (–0.3 V to 0.3 V), with allthree side gates and the back gate grounded. The conductance exhi-bits distinct Coulomb peaks, which are associated with resonanttunnelling into the quantum dot (Supplementary Fig. S3).Coinciding with these conductance peaks are abrupt changesin capacitance. Generally, increases in quantum dot occupancyDN¼ 1 are associated with roughly constant capacitance jumpsDC (see also Fig. 4). In the blue shadowed regime in Fig. 2b, the con-ductance is negligible and the capacitance, Csd , DC, is insensitiveto Vsd. For these reasons, we infer that N¼ 0 electrons are containedin the quantum dot in this regime.

1Department of Physics and Astronomy, University of Pittsburgh, Pittsburgh, Pennsylvania 15260, USA, 2Laboratorio Nacional de Luz Sıncrotron, CaixaPostal 6192, 13083-970 Campinas SP, Brazil, 3Instituto de Fısica ‘Gleb Wataghin’, Universidade Estadual de Campinas-UNICAMP, Campinas SP, Brazil,4Department of Materials Science and Engineering, University of Wisconsin-Madison, Madison, Wisconsin 53706, USA, 5Hewlett Packard Laboratories,1501 Page Mill Road, Palo Alto, California 94304, USA. *e-mail: [email protected]

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The Coulomb peaks and associated capacitance jump locationsexhibit hysteresis with respect to the source–drain voltage sweepdirection. The conductance peak position, peak width and hysteresismagnitude vary significantly with temperature (SupplementaryFig. S3). With increasing temperature, the peak position firstshifts to more negative Vsd, then at TC1¼ 25 K it begins to increasewith temperature. The width of the peak increases approximatelylinearly with temperature; above T¼ TC1, the slope increases by afactor of five (Fig. 2d).

The observed hysteresis in the Coulomb peak position is attrib-uted to ferroelectric switching in the SrTiO3 barrier. The lattice con-stants of LaAlO3 and SrTiO3 are 3.789 Å and 3.905 Å respectively(3% mismatch), and the three-unit-cell LaAlO3 is coherentlystrained biaxially to match the SrTiO3 lattice constant. The pro-found effect of strain on thin SrTiO3 layers is well known14–17.Field-emission experiments on LaAlO3/SrTiO3-based SketchFETdevices13 show evidence of a diverging dielectric permittivity

associated with structural phase transitions in the near-interfaceSrTiO3 region at TC1¼ 25 K and TC2¼ 65 K. The hysteretic behav-iour observed as a function of local in-plane applied electric fields ishighly non-monotonic with respect to temperature, and exhibitsanomalies at a known structural transition TC1. This hysteresis isqualitatively distinct from the hysteretic changes in polarizationthat have been reported for vertically gated LaAlO3/SrTiO3 hetero-structures18. Hysteresis in both conduction and capacitance as afunction of the back-gate bias is observed for device A(Supplementary Fig. S8); however, as noted in ref. 18, it is difficultto distinguish ferroelectric hysteresis from trap charging or otherpolarization effects in this geometry.

Ferroelectric polarization has a profound influence on the res-onant tunnelling characteristics of the SketchSET, and is capableof switching the conductance of the source–drain channelbetween ‘on’ and ‘off’ states (Fig. 2c). At T¼ 30 K, when Vsd isswept in the forward direction, resonant tunnelling is observed at

LaAlO 3

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Figure 1 | SketchSET schematic and transport characteristics. a, c-AFM sketching of a single-electron transistor device. b, Energy illustration of the

SketchSET device. The vertical scale has arbitrary units, but reflects the relative electron energy barrier height. Quantum-dot tunnel barriers are created by

applying a negative voltage pulse of duration tb. The quantum dot is formed by applying a positive voltage pulse of duration td. c, Differential conductance

Gsd from source to drain at T¼ 16 K. Conductance is suppressed at low biases and increases rapidly above a threshold voltage of �0.2 V. The red curve is

an exponential fit to the data. The peaks in the inset are Coulomb peaks after subtracting an exponential background. Numbers with arrows indicate

electron occupation.

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Figure 2 | Temperature-dependent differential conductance and capacitance of device A. a, Differential conductance Gsd measured at temperatures ranging

from 16 K (bottom black curve) to 40 K (top pink curve) in 1 K steps. Curves are shifted by 0.6 nS for clarity. b, Source–drain capacitance Csd measured over

the range in a. Curves are shifted by 1.6 pF for clarity. A sharp change in Csd corresponds to a single electron tunnelling event. The shadowed blue, red and

yellow regions indicate electron occupations of 0, 1 and 2, respectively. Green regions indicate hysteretic regions where electron occupation in the quantum

dot changes by DN¼+1. c, Gsd measured at T¼ 30 K for forward (red) and reverse (blue) source–drain bias sweep directions. The Coulomb peaks are

shifted by ferroelectric polarization in the SrTiO3. d, Coulomb peak width versus temperature. A kink is observed at TC1¼ 25 K, coincident with a ferroelectric

phase transition in the SrTiO3. e, Schematic band diagram showing resonant tunnelling at Vsd¼0 V in the forward sweep direction. The red arrow indicates

the direction of ferroelectric polarization P. f, For the reverse sweep, the polarization is reversed (2P) and the electrochemical potential of the dot is lowered

by Df so that the system is in the Coulomb blockade regime.

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Vsd¼ 0, with Gsd¼ 0.3 nS. After sweeping Vsd to 0.3 V and return-ing to Vsd¼ 0, the conductance has vanished.

The effect of ferroelectric polarization on the SketchSET charac-teristics can be understood qualitatively by expanding the constant-interaction (CI) picture2, in which there are well-defined energylevels in the quantum dot, to include the effect of ferroelectric polar-ization. Single-electron tunnelling occurs when an allowed energystate within the quantum dot becomes resonant with the electroche-mical potential of either the source lead (ms) or drain lead (md).Such a resonant condition is indicated in Fig. 2e. Ferroelectrictunnel barriers can shift the chemical potential within thequantum dot (by an amount Df) so that resonance only occurs

for one polarization direction (Fig. 2f ). The SketchSET can beregarded as a local sensitive detector of polarization in the SrTiO3;however, it is only sensitive when the SketchSET undergoesresonant tunnelling.

Within the CI framework, the Coulomb peak spacing DVsd canbe used to estimate the addition energy Ea by DVsd¼ Ea/ea,where the lever arm a¼ Cs/CQD is the ratio between the source-to-quantum dot capacitance Cs and total quantum dot capacitanceCQD. The width of the Coulomb peak is expected to broaden linearlywith temperature19: dVsd/dT¼ 3.5kB/ea, where kB is the Boltzmannconstant. From Fig. 2d, we can estimate a≈ 0.15 for T , TC1and a≈ 0.03 for T . TC1, respectively. The addition energy below

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Figure 4 | Differential conductance and capacitance dependence on back-gate voltage at T 5 16 K, device C. a, Differential conductance (Gsd) curves at

back-gate voltages Vbg from 20.4 V to 0 V in 0.02 V steps. Curves are offset by 0.2 nS for clarity. The second electron emerges at Vbg¼20.1 V. b, Intensity

plot of Gsd. c, Capacitance curves at the same gating conditions as in a. Curves are offset by 0.3 pF for clarity. The discrete jumps coincide with changes in

electron occupancy in the quantum dot. d, Intensity plot of Csd. Numbers in red in c and d indicate electron occupation N in the quantum dot.

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Figure 3 | Device B side gating at T 5 25 K. a, Differential conductance Gsd for various side-gate voltages Vg1¼22.5 V, 21.0 V, 0 V, 1.0 V and 2.5 V. The

other side gate is grounded: Vg2¼0 V. b, Two-dimensional plot of Gsd versus Vg1 and Vsd. A single Coulomb oscillation is observed only when Vg1 and Vsd

have opposite signs. The red arrows in a and b mark resonant tunnelling.

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25 K cannot be estimated, because N¼ 2 states are not observed. Asthe Coulomb peak shifts to positive values of Vsd, a second electronstate emerges at T . 31 K with spacing DVsd ≈ 0.3 V (Fig. 2b),which allows for an addition energy to be estimated as Ea¼9 meV and thus CQD ≥ 18 aF. An upper limit of CQD ≤ 40 aFcan be inferred from the thermal broadening effect, whichoccurs at T ≈ 45 K. The energy shift caused by the ferroelectricremnant polarization can be estimated in a similar manner:DEFE ≈ 2–6 meV.

There are two principal mechanisms by which the ferroelectricpolarization can produce an energy shift (Supplementary Fig. S7).If the polarization is spatially uniform, then it can only couple tothe dipole moment of the quantum dot. If the polarization isspatially non-uniform, then it can couple directly to the charge.The first scenario is outlined in Fig. 2e,f, but broken symmetriescould lead to a situation in which the polarization breaks intonon-symmetric domains. Such a case would also produce a directferroelectric coupling to the charge in the quantum dot.

Resonant tunnelling through the quantum dot can be modifiedthrough the application of either side gates or a back gate. Thestrength of the side-gate coupling can be adjusted by varying thebarrier width (controlled by the duration of the erase pulse tb) orby writing side gates a fixed distance from the quantum dot. Twoexamples are shown for side gates created close to the island(device B) and separated by a 50 nm gap (device A). For device A(Supplementary Fig. S4), a clearly defined resonance is shifted byDVsd¼ 40 mV as the side gate Vg is changed from 20.2 V toþ0.2 V, with no evidence of gate leakage. The low coupling factor,DVs/DVg¼ 0.1 in this case, reflects the geometric separation ofthe side gate. For device B, the gates are separated by approximatelythe same distance as the source and drain leads; hence, significantgate leakage is observed. Sharp resonances are only observedwhen Vg1 and Vsd have opposite signs (Fig. 3). This ‘differentialmode’ is more effective in aligning the lowest quantum dot chemicalpotential level than the ‘common mode’ configurations(Supplementary Fig. S5).

SketchSET structures respond to modest (|Vbg| , 1 V) voltagesapplied to the bottom of the SrTiO3 substrate. The sensitivity ofthe SketchSET to back gating, as measured by changes in the effec-tive carrier density within the quantum dot, is more than two ordersof magnitude larger than what has been reported for back-gatecontrol of the metal–insulator at room temperature7 and supercon-ductivity at low temperature20. The principal reason for the relativelyhigh sensitivity is that the high curvature of the metallic nanostruc-tures focuses the electric flux lines, thereby greatly increasing theelectric field effect at the device.

Figure 4 shows the differential conductance and capacitance as afunction of back-gate bias Vbg and source–drain bias Vsd for deviceC. For the lowest value Vbg¼20.4 V, a single resonant peak isobserved as Vsd is swept from 0 V in either the positive or negativedirections. The resonant peaks mark a transition from N¼ 0 elec-trons in the quantum dot to N¼ 1 electrons. The increase in N isassociated with a discrete jump in the measured capacitance(Fig. 4c,d), increasing from C0 ≈ 2.5 pF for Vsd¼ 0 by an amountDC2¼ 3.5 pF (DCþ¼ 2.5 pF) for scans with increasing |Vsd|.Although the structure is nominally symmetric with respect tosource and drain, there are clear asymmetries, which result in differ-ent thresholds for positive and negative Vsd. As Vbg is increased, theresonances shift towards Vsd¼ 0 V (Fig. 4d), and a second resonantpeak is observed on the Vsd , 0 side. The higher stability of theN ¼ 2 state, as measured by the strong suppression of the conduc-tance near Vsd¼20.18 V, and the greater width of the N¼ 2plateau in the capacitance, is believed to be a manifestation of thewell-known ‘shell filling effect’ that has been observed in two-dimensional quantum-dot systems21,22 and III–V self-assembledquantum dots23. Higher N values are not observed because the

structure becomes highly conducting outside the range shown, buta similar non-uniform spacing is apparent in Fig. 4c.

A remarkable feature of the SketchSET is the high sensitivity ofthe capacitance to changes in electron occupation in the quantumdot. The change in capacitance (�pF) observed during a single-elec-tron charging event at the quantum dot is approximately threeorders of magnitude too large to be accounted for solely by electro-static effects. It is well known that SrTiO3 is a high-permittivityincipient ferroelectric with a dielectric constant that can exceed1≈ 1 × 104 at low temperatures, which is easily perturbed by struc-tural deformation, strain and electric fields24. The presence of asingle bound electron at the LaAlO3/SrTiO3 interface is predictedto produce a large distortion of the SrTiO3 octahedra that extendsfar beyond the location of the charge8. This structural distortionincreases the polarizability of the nearby SrTiO3, thus increasingthe parasitic capacitance Cp between source and drain(Supplementary Fig. S6). The inferred CQD is roughly four ordersof magnitude smaller than the measured capacitance Cp.

The unique properties of this ferroelectric SketchSET providenew opportunities for combining the ultrahigh electrostatic sensi-tivity of SET devices with ferroelectric-derived sensitivity at thenanoscale. Because all ferroelectric materials are also piezoelectric,a natural coupling between charge and nanomechanical motion isexpected for the SketchSET. Furthermore, a variety of phenomenaassociated with the spin degree of freedom for single-electrondevices25,26 is expected to hold for these devices. By integratingoxide heterostructures with silicon27, it may be possible to integrateferroelectric SketchSET scanning probes that are capable of measur-ing charge and displacement simultaneously at the nanoscale28. Theexistence of a ferroelectrically programmable SET constitutes a newtype of nanoscale memory architecture that could be useful for low-power, ultrahigh-density storage, if the charging energy and ferro-electric polarization could be made to persist to room tempera-ture14,15,27. The method for creating a single SketchSET is readilyreplicated as one- or two-dimensional arrays, which may find usein quantum dot-based quantum computation29 or as a versatilesolid-state ‘Hubbard toolbox’30 capable of exploring new artificialquantum states of matter.

MethodsThe three-unit-cell LaAlO3/SrTiO3 samples for devices A, B and C were grown at780 8C with an oxygen background pressure of 7.5 × 1025 mbar using pulsed laserdeposition. The samples were then patterned with six gold electrodes contacting theinterface by ion milling 25 nm and backfilling with 2 nm titanium and 23 nm gold.AFM lithography was carried out using a commercial atomic force microscope(Asylum Research MFP-3D) under conditions of controlled relative humidity (40%).The tip position was controlled by a custom-made Labview program that convertsgraphic information to voltage commands, which are sent to the AFM scanner.Before writing the SketchSET device, the sample surface was cleaned by slowlyscanning the AFM tip with an applied voltage of 210 V to remove residue charges atthe interface. During writing, conductance between the electrodes of interests wasmonitored simultaneously. Transport measurements were performed using a dual-phase lock-in amplifier at 25.5 Hz. The lock-in phase was adjusted so that the xchannel reflected the conductance and the y channel reflected the capacitance.

Received 9 February 2011; accepted 16 March 2011;published online 17 April 2011

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AcknowledgementsThis work was supported by US National Science Foundation (DMR-0704022 andDMR-0906443), US Defense Advanced Research Projects Agency (W911NF-09-10258),US Army Research Office (W911NF-08-1-0317), The Fine Foundation, US Air Force Officeof Scientific Research (FA9550-10-1-0524), a David and Lucile Packard Fellowshipand the Fundacao de Amparo a Pesquisa do Estado de Sao Paulo – FAPESP (contactproject 05/04643-7).

Author contributionsG.C. carried out the major experiments. P.F.S. and C.C. carried out preliminaryexperiments. F.B., G.C. and D.F.B. contributed to device fabrication. C.W.B., C.M.F., J.W.P.and C.B.E. contributed to sample growth. J.L., G.C., C.C. and G.M.R. discussed andanalysed the results. All authors contributed to writing of the manuscript.

Additional informationThe authors declare no competing financial interests. Supplementary informationaccompanies this paper at www.nature.com/naturenanotechnology. Reprints andpermission information is available online at http://www.nature.com/reprints/.Correspondence and requests for materials should be addressed to J.L.

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