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May 18, 2004 MS Defense: Uppalapati 1

ASIC DESIGN FOR LOW

POWER APPLICATIONS

Represented by

B.Nethra

11k1a!"#

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May 18, 2004 MS Defense: Uppalapati 2

Ta$k O%t$&ne

Motivation

Background

rior !ork

roposed Design "lo#

$esults

%onclusion and "uture !ork

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May 18, 2004 MS Defense: Uppalapati &

'(t&)at&(n

'ncreasing gate count( increasing clockfre)uency *increasing +!$

orta-le e)uip.entruns on -attery

o#er consu.ptiondue to glitc/es can -e&0 0

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May 18, 2004 MS Defense: Uppalapati 4

'(t&)at&(n* Ch&p P(+er

Dens&ty

4004

8008

8080

8085

8086

286386

486Pentium

P6

1

10

100

1000

10000

1970 1980 1990 2000 2010

Year

PowerDensity(W

/cm2

!ot P"ate

#uc"ear$eactor

$oc%et

#o&&"e

'un(s

'ur)ace

'ource* +nte"

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May 18, 2004 MS Defense: Uppalapati 3

'(t&)at&(n ,"(nt-d/

resent dayApplication Specific

Integrated Circuit5S'%6 c/ips e.ploy

standard cell -ased design style75 )uick #ay to design circuits #it/ .illions of

gates

isting glitc/ reduction tec/ni)uesde.and gate re9design: not suita-le for a

cell-based design

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May 18, 2004 MS Defense: Uppalapati

Pr(b$e0 State0ent

;o devise a glitc/

suppressing

.et/odology after t/etec/nology .apping

p/ase

7 !it/out re)uiring cell re9

design7 !it/out violating circuit

delay constraints

Desi,n -ntry

.ec/no"o,y

ain,

ayout

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May 18, 2004 MS Defense: Uppalapati

Ta$k Pr(ress

Motivation

Background

rior !ork

roposed Design "lo#

$esults

%onclusion and "uture !ork

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May 18, 2004 MS Defense: Uppalapati 8

Pr&(r W(rk

isting glitc/ reduction tec/ni)ues

7 5gra#al, VLSIDesign ?@A

7 $educed constraint set linear progra. >$aa et alC,VLSI Design 0&A7 %M+S circuit design for .ini.u. dyna.ic po#er and

/ig/est speed >$aa etC alC, VLSI Design?04A

+pti.i=ation of cell -ased design7 %ell li-rary opti.i=ation >Masgonty et alC, PATMOS ?01A7 %ell selection >/ang et alC, DAC ?016A

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May 18, 2004 MS Defense: Uppalapati @

Pr&(r W(rk* 2a3ard F&$ter&n

Elitc/ is suppressed #/en t/e inertial delay

of gate eceeds t/e differential input delaysC

$e9design all gates in t/e circuit forinertial delay differential delay

3

2

Filtering Effect of a gate

$eference: FC DC 5gra#al, G

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May 18, 2004 MS Defense: Uppalapati 10

Pr&(r W(rk* Ce$$ L&brary

Opt&0&3at&(n

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May 18, 2004 MS Defense: Uppalapati 11

Pr&(r W(rk* Ce$$ Se$e"t&(n

Mi!ed Integer Linear Progra"M'

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May 18, 2004 MS Defense: Uppalapati 12

Ta$k Pr(ress

Motivation

Background

rior !ork

roposed Design "lo#

$esults

%onclusion and "uture !ork

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May 18, 2004 MS Defense: Uppalapati 1&

Ne+ G$&t"h Re0()&n S($%t&(n

Balanced t/e differential delays at cell

inputs:

7 Using delay ele.ents called #esisti$e%eedt&roug& cells5uto.ated t/e delay ele.ent

7Eeneration

7 'nsertion into t/e circuit

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May 18, 2004 MS Defense: Uppalapati 14

Pr(p(sed Des&n F$(+

Modified linear progra. $esistive feed t/oug/ cell

generation:7 "ully auto.ated7 Scala-le to large '%s

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May 18, 2004 MS Defense: Uppalapati 13

F&rst Atte0pt 4 D&d n(t +(rk*

'(d&5&ed L&near Pr(ra0

%/anges fro. $aa?slinear progra.:

7 Eate delays constants

7!ire delays onlyvaria-les

%onstrained solutionspace

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May 18, 2004 MS Defense: Uppalapati 1

RC De$ay '(de$

Used to find t/eresistance value for agiven delay

Delay depends on loadcapacitance

7 Ku.-er of fan9outs S%;$ si.ulations

done for varying $ and%

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May 18, 2004 MS Defense: Uppalapati 1

RC De$ay '(de$ ,"(nt-d/

%

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May 18, 2004 MS Defense: Uppalapati 18

Deta&$ed Des&n F$(+

Desi,n -ntry

.ec/ain,

ayout

$emoe

"itc/es

"ind delays fro.

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May 18, 2004 MS Defense: Uppalapati 1@

E6per&0enta$ Pr("ed%re

tract cell delays fro. initial layout

7 SP'CT#' si.ulation

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May 18, 2004 MS Defense: Uppalapati 20

P(+er Est&0at&(n

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May 18, 2004 MS Defense: Uppalapati 21

;H5KR +U