Single & Multichip Integration TWG

Workhorse of Electronics Packaging Industry

Presenter: Kyu-oh Lee is Sr. Engineering Manager at Intel Corporation

Chair: William (Bill) Chen is Past President of IEEE EPS. He is ASE Fellow & Senior Technical Advisor

Co-Chair: Annette Teng Past Chair of IEEE EPS Santa Clara Valley Chapter. She is CTO at Promex.

Lead Contributors

Lei Shan (IBM) Benson Chan (Binghamton U) Annette Teng (Promex) Ivy Qin (K&S) Mark Gerber (ASE)Kyu-oh Lee (Intel)

Jim Wilcox (UIC)Kris Erickson (HP) Paul Ho (U Texas)Abhjit Dasgupta (U Maryland)Baghat Sammakia (Binghamton U)William Chen (HIR & ASE)

A Quote from Gordon MooreIt may prove to be more economical to build large systems out of smaller functions, which are separately packaged and interconnected. The availability of large functions, combined with functional design and construction, should allow the manufacturer of large systems to design and construct a considerable variety of equipment both rapidly and economically. • Reprinted from Gordon E. Moore, “Cramming More Components onto Integrated Circuits,” Electronics, pp. 114–117, April 19, 1965.

It may prove to be more economical to build large systems out of smaller functions through Heterogeneous Integration into SiPs , which are separately packaged and interconnected. The availability of large functions, combined with functional design and construction, should allow the manufacturer of large systems to design and construct a considerable variety of equipment both rapidly and economically.

Single & Multichip Integration ChapterTable of Content

1. Executive Summary & Scope2. Electrical Requirements3. Thermal Management4. Mechanical Requirements5. Wafer Singulation & Thinning6. Wirebond7. Flip Chip

8. Substrate9. Board Assembly10. Additive Manufacturing11. Electromigration12. Reliability13. Executive Summary &

Challenges14. Acknowledgement

The Definition of Heterogeneous IntegrationSlide 5

Heterogeneous by material, component type, circuit type, node and bonding/interconnect method

Warpage Engineering, CPIWarpage Engineering• Assembly stress due to warpage is the largest contributor to failures in

packaging. Some of the variables leading to the warpage include substrate materials, copper distribution (wiring density), number of layers, underfill material, die thickness, processing temperatures, humidity…

• Reducing warpage and stress will contribute to higher yields and better reliability

• As interconnect pitches go down, the warpage window for packages will be reduced

Step1: Silicon attach to substrate at Solder Reflow Temperature ~230℃

Step2: Cool down to room temperature

Step3: Heat back to underfill temperature (150 ~ 200℃)

Step4: Cool down again

Wire Bonding Market and Technology Trends

• Majority of the interconnects are still made with wire bonders today. • The major growth in wire bonding is from SiP packages. From 2018 to 2023,

wire bonded SiP will grow from 25 to 38 billion units, while wire bonded single chip will only grow from 176.0 to 181.8 billion as shown above.

Semiconductor package unit growth by interconnect type. IC Package Shipment excluding Discreet, LED and Opto. Source Prismark May 2019.

Increased Interconnect Density• The finest inline pitch of wire bonding has remained around 35um.

However, wire bonding interconnect density continuously increases through higher level of system integration such as SiP, stack die and Multi-tier packages.

Stacked Memory DeviceHigh Density Multi-tier PackageSiP with Die to Die Wire Bond Interconnect

HI Interconnect RequirementIn

terc

onne

ct P

itch

(Die

to S

ubst

rate

/RDL

to S

ubst

rate

)

135um

Large Die >13mm

Large Die (>15mm)

120um

45um 30um

Small Die <13mm

Small Die (<15mm)

- Industry Trend is Reduction in Pitch By 5um Per 2 Yr – Material Dependent (Substrate/UF/Encap/Solder)- Die to Die Pitch Faster Due to Like CTE Properties-Low Stress

Time

Large Die Micro Bump/DIE/DIE

75um

20um

Direct Cu/Cu (Nanopaste)Embedded Technologies-CuCu)

180um

90um

3um

Enhanced By CorelessHetero Intg. W/Smaller Pitch

Enhanced by Adaptive Alignment

Substrate Roadmap Drivers

• High bandwidth• High TDP• Heterogeneous integration

(i.e. HBM, FPGA, Graphic)

High Performance Computing

• Low profile• High I/O density • Heterogeneous integration

(i.e. POP memory)• Cost

Mobile

• Low profile• Low latency• High bandwidth• Heterogeneous integration

(Antenna, RF, baseband)• Cost

5G/mmWave

• High Reliability• High bandwidth• Low latency

Automotive

High Density Wire Roadmap & Solution

• High resolution litho and laser process development for fine L/S (<3/3um) and uVia(<10um) w/ minimal overlay (< 6um)

• Low roughness (<200nm) and low CTE (<20ppm) build up materials development.

• Photoimagible dielectric materials development with lower CTE (<30ppm)

• Thin eless Cu (<0.1um) seed and high selective flash etching chemistry development.

• Dry seed and etching process and tool development in panel level.

• Fine pitch bumping technology development (single & mixed bump pitch)

High Speed Signal Transfer Roadmap & Solution

• Low roughness (<100nm) and low dielectric loss (<0.002) and dielectric constant (<2.5) BU development

• Pure chemical assisted adhesion promoter development (Rq<100nm)

• Cost effective panel level dry process development (desmear / seeding process)

Diel

ectr

ic lo

ss

Board Level AssemblyThe total diversity (heterogeneity) of packaging technologies

comprising any product culminates at the final board assembly.Packages are assembled onto PCBs of varying complexity.

HighLow PCB complexity~50 µm thick

single layer filmflexible substrate

temperature limits

≳5 mm thick several tens of layersextensive microviaslarge thermal mass

increasing thickness, rigidity

cloud serverswearablesmobile

automotiveaerospace

Package complexity and heterogeneity tends to scale with board complexity

Additive Assembly … Leaving the Plane• Existing board assembly infrastructure evolved for planar packages

• all components placed on horizontal surfaces• gravity retention through the joining process

• Additive manufacture of electronics anticipates component assembly in arbitrary orientations

• Ultimate additive assembly incorporates placement & joining operations within the 3D deposition process

Difficult Challenge

additive manufacturing

Focus for 2020 Edition

An Emerging Trend“Silicon Bridge”“Multi-Die SOC”

“Chiplets”…………

Enabling Multi-Die Integration

Two Generations of the AMD EPYC Server Processor

• Left is large die split into 4 “chiplets” tightly coupled on an organic substrate (14nm)

Slide 16

• Right are 4 groups of 2 “chiplets” (7nm) on each side of larger I/O die (14nm) tightly coupled on an organic substrate

Intel’s Embedded Multi-die Interconnect Bridge

EMIB is high bandwidth link between multiple die of different nodes and circuit types on organic substrate

Slide 17

EMIB example: Intel Kaby Lake G card with Intel CPU, AMD GPU and 4GB HBM2.

Challenges & OpportunitiesMarket Challenges• Design for Diverse Markets• Novel Devices & Sensors Integration – 2D+3D• Miniaturization & More Integration• Orthogonal multi-stacking Assembly• High Volume – Custom Design & Manufacturing on

Demand• Thermal Management• Security• Performance, Performance, & Performance• Cost, Cost & Cost

Opportunities & SolutionsAI & Knowledge Infrastructure• Big Data from Billions of sensors in electronic

products, in electronics manufacturing equipment, & in environments

• Data Analytics, Clouds & Edge CloudsAI & Physical Infrastructure• Robotics • Additive Manufacturing • Emerging Materials & Emerging Device Research & Development in anticipation of the needs

18

Thank you