Simulation Verification of Different Constraints in System Level Design in SystemC
description
Transcript of Simulation Verification of Different Constraints in System Level Design in SystemC
![Page 1: Simulation Verification of Different Constraints in System Level Design in SystemC](https://reader036.fdocuments.us/reader036/viewer/2022081520/568153a2550346895dc1a689/html5/thumbnails/1.jpg)
Simulation Verification of Different Constraints in System Level Design in SystemC
Piyush Ranjan Satapathy
CS220 Class Project Presentation
![Page 2: Simulation Verification of Different Constraints in System Level Design in SystemC](https://reader036.fdocuments.us/reader036/viewer/2022081520/568153a2550346895dc1a689/html5/thumbnails/2.jpg)
The Problem Statement
• How can we detect deadlock in the system level design in systemC ?
• What are the other possibilities of design constraints in systemC ? (E.g. Live lock, Starvation)
• We know that system level designs are highly complex, heterogeneous and concurrent. so how can we detect the above constraints in the complex model of designing ?
![Page 3: Simulation Verification of Different Constraints in System Level Design in SystemC](https://reader036.fdocuments.us/reader036/viewer/2022081520/568153a2550346895dc1a689/html5/thumbnails/3.jpg)
What is the solution ?
• Analyse the synchronization dependencies of the systems designed in systemC
• Capture the run time dependencies of various blocks in the system and maintain a data structure named Dynamic Synchronization Dependency Graph
• Use a loop detection algorithm to detect the deadlocks.
• Similar to Metropolis Approach but varies with the Environment and synchronization lists.
![Page 4: Simulation Verification of Different Constraints in System Level Design in SystemC](https://reader036.fdocuments.us/reader036/viewer/2022081520/568153a2550346895dc1a689/html5/thumbnails/4.jpg)
Motivation
• A System level designer deals with
Function Vs Architecture
Computation Vs Communication
Data Path Vs Control
• Possible to introduce unintended and undesirable behaviors into function specifications, high level architectural models or functional mappings.
• Deadlock, Livelock and Starvation are such undesired behaviors which designer may face at the runtime.
• So detecting such a scenario by simulation helps us knowing the design faults and also helps to figure out the exact portion of the design/code to change.
![Page 5: Simulation Verification of Different Constraints in System Level Design in SystemC](https://reader036.fdocuments.us/reader036/viewer/2022081520/568153a2550346895dc1a689/html5/thumbnails/5.jpg)
Road Map
• Some back Grounds in SystemC
• Synchronizations and Dependencies in SystemC
• Constraints scenario in systemC
• Deadlock Detection Data Structure
• Loop Detection Algorithm
• Algorithm in Action in 1 systemC Model
• A Comparison with Related Work (MMM Environment)
• Conclusion
• Future Work
![Page 6: Simulation Verification of Different Constraints in System Level Design in SystemC](https://reader036.fdocuments.us/reader036/viewer/2022081520/568153a2550346895dc1a689/html5/thumbnails/6.jpg)
Some back Grounds in SystemC
Slide From http://www-cad.eecs.berkeley.edu/~polis/class/ee249/lectures/l10-systemC.pdf
![Page 7: Simulation Verification of Different Constraints in System Level Design in SystemC](https://reader036.fdocuments.us/reader036/viewer/2022081520/568153a2550346895dc1a689/html5/thumbnails/7.jpg)
Slide From http://www-cad.eecs.berkeley.edu/~polis/class/ee249/lectures/l10-systemC.pdf
![Page 8: Simulation Verification of Different Constraints in System Level Design in SystemC](https://reader036.fdocuments.us/reader036/viewer/2022081520/568153a2550346895dc1a689/html5/thumbnails/8.jpg)
Slide From http://www-cad.eecs.berkeley.edu/~polis/class/ee249/lectures/l10-SystemC.pdf
![Page 9: Simulation Verification of Different Constraints in System Level Design in SystemC](https://reader036.fdocuments.us/reader036/viewer/2022081520/568153a2550346895dc1a689/html5/thumbnails/9.jpg)
Slide From http://www-cad.eecs.berkeley.edu/~polis/class/ee249/lectures/l10-SystemC.pdf
![Page 10: Simulation Verification of Different Constraints in System Level Design in SystemC](https://reader036.fdocuments.us/reader036/viewer/2022081520/568153a2550346895dc1a689/html5/thumbnails/10.jpg)
SystemC Highlights
1. It supports Hardware-Software Co-Design. All Constructs are in a C++ Environment. It introduces
• 3 kinds of processes such as Method, Thread, and Cthread
• Ports and Modules
2. It introduces
• Events (Flexible and Low Level synchronization Primitive)
• Channels (A Container class for communication and Synchronization)
• Interfaces (Specify a set of access methods to channel)
3. It supports• Clocks (time Keeper of Simulation)
• Event Driven Simulation by Dynamic sensitivity of Events
E.g. (Wait(), next_trigger(),wait_until)
![Page 11: Simulation Verification of Different Constraints in System Level Design in SystemC](https://reader036.fdocuments.us/reader036/viewer/2022081520/568153a2550346895dc1a689/html5/thumbnails/11.jpg)
Slide From http://www-cad.eecs.berkeley.edu/~polis/class/ee249/lectures/l10-SystemC.pdf
![Page 12: Simulation Verification of Different Constraints in System Level Design in SystemC](https://reader036.fdocuments.us/reader036/viewer/2022081520/568153a2550346895dc1a689/html5/thumbnails/12.jpg)
Synchronizations and Dependencies in SystemC
Transferring Control of Execution From One process to Another Process
1. For Thread Process:• Wait()• Wait(e1)• Wait(e1 | e2 | e3)• Wait(e1 & e2 & e3)
2. For Method Process:• Next_trigger() : Returns immediately so no constraints here.
3. For Clocked Thread Process:• Wait_until()• Watching()
4. Access to shared data using Mutex through proper synchronization
![Page 13: Simulation Verification of Different Constraints in System Level Design in SystemC](https://reader036.fdocuments.us/reader036/viewer/2022081520/568153a2550346895dc1a689/html5/thumbnails/13.jpg)
Synchronizations and Dependencies in SystemC
Resuming the Execution of the Dependent Process
1. For Thread Process:• Notify() //Notify Immediately
• Notify(SC_ZERO_TIME) //Notify Next Delta Cycle
• Notify(t) //Notify at time t
• Cancel() //Cancels a delayed notification
2. For Method Process:• Next_trigger method() returns immediately without passing the
control to another Process
3. For Clocked Thread Process:• Boolean true value to wait_until() or watching() methods.
![Page 14: Simulation Verification of Different Constraints in System Level Design in SystemC](https://reader036.fdocuments.us/reader036/viewer/2022081520/568153a2550346895dc1a689/html5/thumbnails/14.jpg)
SystemC Event SchedulerINIT
Evaluate
Update
Immediate Notification ?
Delta Event Notification ?
Next Simulation Time
Pending Events ?YES
DONE
YES
YES
![Page 15: Simulation Verification of Different Constraints in System Level Design in SystemC](https://reader036.fdocuments.us/reader036/viewer/2022081520/568153a2550346895dc1a689/html5/thumbnails/15.jpg)
P0
P1
P2
p4P3
||
e
e
e
e
![Page 16: Simulation Verification of Different Constraints in System Level Design in SystemC](https://reader036.fdocuments.us/reader036/viewer/2022081520/568153a2550346895dc1a689/html5/thumbnails/16.jpg)
P0
P1
P2
P3
&&
e
e
e
![Page 17: Simulation Verification of Different Constraints in System Level Design in SystemC](https://reader036.fdocuments.us/reader036/viewer/2022081520/568153a2550346895dc1a689/html5/thumbnails/17.jpg)
Live Lock in SystemC
Live lock is defined as a situation where the system falls into dead loop and responds to no further interrupts. Its defined as infinite cyclic executions of any events.
Case1:
Waiting events of the same process.. (But I have not tried)
Case2:
Data Watch in Cthread Process..What if Wait_until() and watching not get satisfied…It will loop infinitely. Because that is the property of the clocked thread process.
![Page 18: Simulation Verification of Different Constraints in System Level Design in SystemC](https://reader036.fdocuments.us/reader036/viewer/2022081520/568153a2550346895dc1a689/html5/thumbnails/18.jpg)
Starvation in SystemC
Starvation is defined as a situation where a process will be blocked infinitely. Live lock of some processes may cause starvation for the dependent processes.
Case1:
Notify() at a circular basis at immediate stage or at Next Delta cycle stage
Case2:
Data path blocking due to watch() or wait_until() or due to mutex sharing.
![Page 19: Simulation Verification of Different Constraints in System Level Design in SystemC](https://reader036.fdocuments.us/reader036/viewer/2022081520/568153a2550346895dc1a689/html5/thumbnails/19.jpg)
System level Design
Compilation
Simulation Model
Simulationvectors Simulation Deadlock Analysis
Simulationtrace
SimulationDependencies
Analysis Report
DSDG
Deadlock Detection Deadlock ?
Deadlock Warnings?
Update DSDG
YES
Output Dependencies
Dead Lock
Analysis
Revise the design and/or simulation vectors
![Page 20: Simulation Verification of Different Constraints in System Level Design in SystemC](https://reader036.fdocuments.us/reader036/viewer/2022081520/568153a2550346895dc1a689/html5/thumbnails/20.jpg)
Data Structure (Dynamic Synchronization Dependency Graph)
• Let’s represent the synchronization dependency as a directed graph S=(V,E) where V is a set of 4 categories of vertices representing processes in the system, one dependency, set of and dependency, set of or dependency. E is a set of directed edges between vertices indicating dynamic synchronization dependencies.
P
&&
||
e
Process vertex
And vertex
Or vertex
Single Dependency vertex
![Page 21: Simulation Verification of Different Constraints in System Level Design in SystemC](https://reader036.fdocuments.us/reader036/viewer/2022081520/568153a2550346895dc1a689/html5/thumbnails/21.jpg)
DSDG Examples
![Page 22: Simulation Verification of Different Constraints in System Level Design in SystemC](https://reader036.fdocuments.us/reader036/viewer/2022081520/568153a2550346895dc1a689/html5/thumbnails/22.jpg)
Updating DSDG Dynamically
Algorithm(1):
Checking When to update and what to update
For each process Pi in the system
If Pi is in Evaluation Phase
if Pi is unblocked by one or more synch constraints then
Remove all the dependency vertices and edges from Pi
end if
if Pi is blocked by one or more synch constraints then
UPDATE_PROCESS(Pi)
end if
end If
End For
![Page 23: Simulation Verification of Different Constraints in System Level Design in SystemC](https://reader036.fdocuments.us/reader036/viewer/2022081520/568153a2550346895dc1a689/html5/thumbnails/23.jpg)
Updating DSDG Dynamically
Algorithm(2):How to update
UPDATE_PROCESS(Pi)
For each synch construct that blocks Pi do
if Pi is blocked by any one of P1, P2,…Pn then
add an OR dependency vertex Oi
CONNECT(Pi, Oi, pj:j Є [1,n])
else if Pi is blocked by any all of P1, P2,…Pn then
add an AND dependency vertex ai
CONNECT(Pi, ai, pj:j Є [1,n])
else if Pi is blocked by one process PJ then
add an single dependency vertes si
CONNECT(Pi, si, pJ) end ifEnd for End procedure
![Page 24: Simulation Verification of Different Constraints in System Level Design in SystemC](https://reader036.fdocuments.us/reader036/viewer/2022081520/568153a2550346895dc1a689/html5/thumbnails/24.jpg)
Updating DSDG Dynamically
Algorithm(3):
Connecting…CONNECT (source,Mid, Desti: i Є [1,n])
add an edge from source to Mid
if (i = = 1) then
add an edge from Mid to Dest1
end if
for i := 1 to n do
add an edge from Mid to Desti
end for
![Page 25: Simulation Verification of Different Constraints in System Level Design in SystemC](https://reader036.fdocuments.us/reader036/viewer/2022081520/568153a2550346895dc1a689/html5/thumbnails/25.jpg)
Loop Detection Algorithm1 DEADLOCK_DETECTION(S,P)2 Search for simple cycles in S starting from process P3 Let L = {Vi, Si} be the set of all these cycles4 If L = Ф then5 Return “No Deadlock” 6 End if7 For each Li in L do8 if the cycle is marked then9 continue;10 end if11 Mark the cycle Li12 if each vertex in the cycle Li are either process or and dependency or single vertex dependency then the process in Li are deadlocked, return;13 else 14 D:= OR dependency vertices that have two or more outgoing edges 15 L’ = {Li}16 repeat17 Find unmarked cycles in L that contains vertices in Di18 mark all these cycles 19 L’ = L’ U {these cycles} 20 until L’ becomes stable21 If vertex in D that has an outgoing edge not belongs to L’ then 22 continue23 Endif 24 The process in L’ are deadlocked , return25 Endif26 End for27 Return No_Deadlock;28 End procedure
![Page 26: Simulation Verification of Different Constraints in System Level Design in SystemC](https://reader036.fdocuments.us/reader036/viewer/2022081520/568153a2550346895dc1a689/html5/thumbnails/26.jpg)
Algorithm in Action
Example: Dining philosopher problem
P0P1
P2
P3
P4
e0
e1
e2e3
e4
P0 e4 P4 e3 e1e2
e0
P3 P2 P1
Got e0 Got e4 Got e3 Got e2 Got e1
One Instance of Simulation:
Satisfied by Line 12 of algorithm..so deadlock….
![Page 27: Simulation Verification of Different Constraints in System Level Design in SystemC](https://reader036.fdocuments.us/reader036/viewer/2022081520/568153a2550346895dc1a689/html5/thumbnails/27.jpg)
Comparison With MMM
• Wait(), notify(), wait_until(), watching()
• Based on systemC kernel scheduler
• Based on the top of the C++. So systemC is more approachable for system level design
• More or less C++ Library
• Loop Detection algorithm much easier compared to MMM
• Await(), synch, eval
• Based on metro Quantity manager
• Based on the Java Platform
• New keywords and syntaxes
![Page 28: Simulation Verification of Different Constraints in System Level Design in SystemC](https://reader036.fdocuments.us/reader036/viewer/2022081520/568153a2550346895dc1a689/html5/thumbnails/28.jpg)
Conclusion
• Detecting deadlock at early time of the design saves both in time and money.
• In this project, I have studied the deadlock and other constraints in system level design in systemC
• Implemented a prototype of deadlock and verified the modified algorithms
![Page 29: Simulation Verification of Different Constraints in System Level Design in SystemC](https://reader036.fdocuments.us/reader036/viewer/2022081520/568153a2550346895dc1a689/html5/thumbnails/29.jpg)
Future work
• More research on Live lock and Starvation
• How to resolve the deadlock dynamically
• Possible modify the simulator of systemC-2.0.1 to hold this deadlock detection feautre
![Page 30: Simulation Verification of Different Constraints in System Level Design in SystemC](https://reader036.fdocuments.us/reader036/viewer/2022081520/568153a2550346895dc1a689/html5/thumbnails/30.jpg)
Acknowledgement
• “Simulation Based Deadlock Analysis for system Level Designs” by Xi Chen, et al. DAC’0
• http://www-cad.eecs.berkeley.edu/~polis/class/ee249/lectures/l10-systemC.pdf
• SystemC Func Guide and users guide (SystemC-2.0.1)
![Page 31: Simulation Verification of Different Constraints in System Level Design in SystemC](https://reader036.fdocuments.us/reader036/viewer/2022081520/568153a2550346895dc1a689/html5/thumbnails/31.jpg)
Thank You !!
![Page 32: Simulation Verification of Different Constraints in System Level Design in SystemC](https://reader036.fdocuments.us/reader036/viewer/2022081520/568153a2550346895dc1a689/html5/thumbnails/32.jpg)
P
&&
||
e
Process vertex
And vertex
Or vertex
Single dependency vertex
BA