Simulation InterfaceSimulation InterfaceFinal PresentationFinal Presentation

Guy Zur

Eithan Nadir

Instructor : Igal Kogan

Project Goal:

• Design and implementation of a Design and implementation of a generic signal generator for test generic signal generator for test procedures of DUT (Device Under procedures of DUT (Device Under Test) by using SoPC platform.Test) by using SoPC platform.

Quick Overview:

RequirementsRequirements

• Receive global parameters from a PC.Receive global parameters from a PC.

• Processing of the parameters using Processing of the parameters using Embedded 32bit RISC Processor.Embedded 32bit RISC Processor.

• Design of the unique signal generator Design of the unique signal generator controllers.controllers.

• Design a feedback module with digital Design a feedback module with digital signal processing capabilities.signal processing capabilities.

Virtex II Pro

PowerPC405

Core

Logic Cells

RAMs

Project resourcesProject resources

• Evaluation Platform Evaluation Platform – XUPV2PXUPV2P

• FPGA : FPGA :

Virtex II Pro platform architecture Virtex II Pro platform architecture

• Processor :Processor :PowerPC 405PowerPC 405

Working PhasesWorking Phases1.1.General Tester – CoreGen General Tester – CoreGen ControllerController

PPC

ethernet Web server

MemoryDouble Buffer

Control unit

DUT

DSP

Xsgacntrlr

Working PhasesWorking Phases1.1.General Tester General Tester

• Transmit time slot data through the Transmit time slot data through the Ethernet.Ethernet.

• Store it in the ddr, using PPC. Store it in the ddr, using PPC. • Extract the data from the ddr DIMM by Extract the data from the ddr DIMM by

control_unit ip and deliver it to the DUT.control_unit ip and deliver it to the DUT.• A special arbiter decides who has A special arbiter decides who has

access to the memory.access to the memory.• Memory controller is based on xilinx’s Memory controller is based on xilinx’s

MIG. MIG.

Working PhasesWorking Phases1.1.General Tester – control unitGeneral Tester – control unit

Data Control unit

Memory Interface

Connecting to the memory using arbiter interface

Data

16

Cntrl

8

Over plb

interface

Pixels’ valid

8

64

Working PhasesWorking Phases1.1.General Tester – control unit - General Tester – control unit - internalinternal

Data

PLBmodule

Frame Start

64

User input addr[22:0]

User bank addr[1:0]

User config reg[9:0]

User dm[7:0]

User input data[127:0]

User cmd ack

User data valid

User output data[127:0]

Auro ref req

Rst_dqs_div_out

Init val

ar_done

Arbitration logicWr_data_fifo

32

12

8

Rd_req

rd_data_fifo

32

12

8

Data read[31:0]

Control unit interface

DIMM Interface

Working PhasesWorking Phases1.1.General Tester – dsp unit - General Tester – dsp unit - internalinternal

DSP

Xsgacntrlr

Pixels data 8

Pixels’ valid

8

VGA_OUT_RGB

24

VGA_COMP_SYNCH

VGA_OUT_BLANK_Z

VGA_OUT_PIXEL_CLK

Controls

8

Working PhasesWorking Phases1.1.General Tester - Work planGeneral Tester - Work plan

1.1. Understanding the DIMM :Understanding the DIMM :1.1. mimic the data received by the Ethernet mimic the data received by the Ethernet a a

function that writes to the memory.function that writes to the memory.

2.2. Implement a DIMM controller using Xilinx Implement a DIMM controller using Xilinx CoreGen.CoreGen.

3.3. Impliment the Arbiter.Impliment the Arbiter.

4.4. Simulate the controller with the arbiter.Simulate the controller with the arbiter.

5.5. Make a DIMM model to work with the DIMM Make a DIMM model to work with the DIMM controller.controller.

6.6. read this data using hardware interface and read this data using hardware interface and write it to the uart. write it to the uart.

DoneDone √ √DoneDone √ √

DoneDone √ √ Fail X

Fail X

Working PhasesWorking Phases1.1.General Tester - Work planGeneral Tester - Work plan

2.2. Impliment the control Unit and test Impliment the control Unit and test it with the uart.it with the uart.

3.3. Impliment the Xsga Controller.Impliment the Xsga Controller.1.1. Understand the VGA interface.Understand the VGA interface.

2.2. Design a debug mode which write a Design a debug mode which write a test pattern picture on the screen test pattern picture on the screen

22..General TesterGeneral Tester– – DDR-PLB ControllerDDR-PLB Controller

Working PhasesWorking Phases2.2.General Tester – DDR-PLB ControllerGeneral Tester – DDR-PLB Controller

• Changing the strategy above. Changing the strategy above. instead of using a DMA, PPC = instead of using a DMA, PPC = DMA controller. DMA controller.

• The read fifo of the Control unit The read fifo of the Control unit produce interrupts- according to produce interrupts- according to these interrupts the system will these interrupts the system will then fetch the next streaming data then fetch the next streaming data from the memory.from the memory.

Working PhasesWorking Phases2.2.General Tester – DDR-PLB ControllerGeneral Tester – DDR-PLB ControllerBuilt DesignBuilt Design

Working PhasesWorking Phases2.2.General Tester – DDR-PLB ControllerGeneral Tester – DDR-PLB Controller

• We assumed that by working with We assumed that by working with processor clock of 300Mhz , using processor clock of 300Mhz , using the 64bit of the plb and reading the 64bit of the plb and reading 16bit@100Mhz, We can produce the 16bit@100Mhz, We can produce the proper rate.proper rate.

Working PhasesWorking Phases2.2.General Tester – DDR-PLB ControllerGeneral Tester – DDR-PLB ControllerControl UnitControl Unit

Control unitPLB IPIF User Logic

fifo

FIFO EMPTY

HALF EMPTY

Data Out

Working PhasesWorking Phases2.2.General Tester – DDR-PLB ControllerGeneral Tester – DDR-PLB ControllerSVGA CNTRLRSVGA CNTRLR

Working PhasesWorking Phases2.2.General Tester – DDR-PLB ControllerGeneral Tester – DDR-PLB ControllerSimulationSimulation

• We simulated the design in Hdl simulation tool • Surprise: The plb uses only the lower 32 bits.• Result: We had severe timing problem. • We couldn’t simulate the interrupt controller, but

in general, our control unit seemed to work fine and the special control unit drivers seemed to work properly.

• We’ve enabled user logic address range support, software slave registers and interrupt support.

• We have spent a great deal of time understanding the IPIF protocol of the above interfaces with the plb_controller.

Working PhazesWorking Phazes2.2.General Tester – DDR-PLB ControllerGeneral Tester – DDR-PLB ControllerReal TimeReal Time

• The above design has been built and compiled

• On the hard way we discovered that the interrupts are called ALL THE TIME. we are actually in a constant underflow state of the fifo inside the control unit.

• THIS IS A DESIGN BUG THAT COULDN’T BE RESOLVED

Working PhazesWorking Phazes2.2.General Tester – DDR-PLB ControllerGeneral Tester – DDR-PLB ControllerReal TimeReal Time

• Demonstration

33.. TransmitTransmit a Bitmap Picturea Bitmap Picture

Over the EthernetOver the Ethernet

Working PhasesWorking Phases3.3.General Tester – Transmit a Bitmap General Tester – Transmit a Bitmap Picture Over the EthernetPicture Over the Ethernet

Working PhasesWorking Phases3.3.General Tester – Transmit a Bitmap General Tester – Transmit a Bitmap Picture Over the EthernetPicture Over the EthernetServer and ClientServer and Client

• Using Xilnet Libs we have developed a server that listens to a specific port.

• Whenever a client requests the server response and receives data.

Working PhasesWorking Phases3.3.General Tester – Transmit a Bitmap General Tester – Transmit a Bitmap Picture Over the EthernetPicture Over the Ethernet

• We have designed a special FTP protocol. The client transmit size of a file (in bytes), and instantly transmits the file.

Working PhasesWorking Phases3.3.General Tester – Transmit a Bitmap General Tester – Transmit a Bitmap Picture Over the EthernetPicture Over the EthernetPLB tft controllerPLB tft controller

• While on the previous phase we used a pure hardware controller, the plb_ftf controller is xilinx’s IP designed to write to the xsga controller using the plb.

• We have written a function that produces test pattern and transmits it to the screen.

• As well as another function that accesses a memory address (on the ddr – because of the size) and transmits it to the screen.

Working PhasesWorking Phases3.3.General Tester – Transmit a Bitmap General Tester – Transmit a Bitmap Picture Over the EthernetPicture Over the Ethernet

• Demonstration + Bug Explanation

44.. Streaming DataStreaming Data TransmissionTransmission

using the Svga controllerusing the Svga controller

Working PhasesWorking Phases4.4.General Tester General Tester – – Streaming Data Streaming Data transmitted using the svga controllertransmitted using the svga controller

Working PhasesWorking Phases4.4.General Tester General Tester – – Streaming Data Streaming Data transmitted using the svga controllertransmitted using the svga controllerstream Unitstream Unit

Working PhasesWorking Phases4.4.General Tester General Tester – – Streaming Data Streaming Data transmitted using the svga controllertransmitted using the svga controllerstream Unitstream Unit

• Receives data (4BX1KB)from the opb, store it in a DPR 4BX2K.

• This dpr is divided into two. Once a load command receives the msb of read address is switched.

• Write clock is opb clk• Read clock is screen clk• The memory range is divided such that in

base address located control registers test mode/ switch addresses ranges.

• Base address + 0x10= write data to the Base address + 0x10= write data to the dpr.dpr.

Working PhasesWorking Phases4.4.General Tester General Tester – – Streaming Data Streaming Data transmitted using the svga controllertransmitted using the svga controllerstream Unitstream Unit - internal- internal

Working PhasesWorking Phases4.4.General Tester General Tester – – Streaming Data Streaming Data transmitted using the svga controllertransmitted using the svga controllerSoftwareSoftware

• Accessing the stream unit is divided to two as mentioned above. Lets follow the next example

• //clearing the control registers• XIo_Out32(XPAR_STREAM_UNIT_0_AR0_BASEADDR,

0x0);• //turn test mode on • XIo_Out32(XPAR_STREAM_UNIT_0_AR0_BASEADDR , 0x1);

//test mode • //switch memory array primary to secondary or vice

versa. • XIo_Out32(XPAR_STREAM_UNIT_0_AR0_BASEADDR ,

0x2);//load done• //clear the req above• XIo_Out32(XPAR_STREAM_UNIT_0_AR0_BASEADDR , 0x0);

// clear load

Working PhasesWorking Phases4.4.General Tester General Tester – – Streaming Data Streaming Data transmitted using the svga controllertransmitted using the svga controllerSoftwareSoftware

//write pixels data:• for(i=0; i< 1024;i++) • {• //set RGB values • r=0xFF;• g=0;• b=0;• pixel=r;• pixel= pixel << 8;• pixel += g;• pixel= pixel << 8;• pixel += b;• XIo_Out32(XPAR_STREAM_UNIT_0_AR0_BASEADDR + 0x10+i*4,i);• }• XIo_Out32(XPAR_STREAM_UNIT_0_AR0_BASEADDR , 0x2);//load done• XIo_Out32(XPAR_STREAM_UNIT_0_AR0_BASEADDR , 0x0); // clear

load STREAM_UNIT_Load (XPAR_STREAM_UNIT_0_AR0_BASEADDR);

Working PhasesWorking Phases4.4.General Tester General Tester – – Streaming Data Streaming Data transmitted using the svga controllertransmitted using the svga controller

Demonstration

Working PhasesWorking PhasesGeneral Tester General Tester – – Streaming Data Streaming Data transmitted using the svga controllertransmitted using the svga controller

• Questions ? ? ?

F I N