function function_name (parameter_list) return type is< declarations>begin<sequential statements>end function_name

architecture Behavioral of VHDL_test isfunction parity (input : std_logic_vector) return std_logic isvariable temp : std_logic := '0';begin for i in input'range loop

temp := temp xor input(i); end loop; return temp;end parity;begin data_out <= "000" & parity(data_in);end Behavioral;

for i in input'range loop temp := temp xor input(i);end loop;

entity VHDL_test is Port ( data_in : in std_logic_vector(7 downto 0); data_out : out std_logic_vector(3 downto 0));end VHDL_test;

para o nosso exemplo i vai ser alterado de 7 a 0

Esta função é válidapara qualquer tamanhode entrada (parâmetro

- input )

Example inVHDL_AF.zip

chamada da função

Exemplo 1

entity Function_test isgeneric (size : natural := 8);Port( data_in : in std_logic_vector(size-1 downto 0); data_out : out std_logic); end Function_test;

architecture Behavioral of Function_test is

function parity (input : std_logic_vector) return std_logic isvariable temp : std_logic := '0';begin for i in input'range loop

temp := temp xor input(i); end loop; return temp;end parity;

begin data_out <= parity(data_in);end Behavioral;

Exemplo 2entity Function_countOne isgeneric (size : natural := 8);Port( data_in : in std_logic_vector(size-1 downto 0); data_out : out std_logic_vector(3 downto 0); data_out_int : out integer range 0 to 8); end Function_countOne;

architecture Behavioral of Function_countOne is

function count_one (input : std_logic_vector) return integer isvariable temp : integer range 0 to 8 := 0;begin for i in input'range loop

if input(i) = '1' then temp := temp+1; end if; end loop; return temp;end count_one;

begin data_out <= std_logic_vector(to_unsigned(count_one(data_in),4)); data_out_int <= count_one(data_in);end Behavioral;

Exemplo 3 entity Function_countOneClk isgeneric (size : natural := 8);Port( clk : std_logic; data_in : in std_logic_vector(size-1 downto 0); data_out : out std_logic_vector(3 downto 0); data_out_int : out integer range 0 to 8); end Function_countOneClk;

architecture Behavioral of Function_countOneClk is

function count_one (input : std_logic_vector) return integer isvariable temp : integer range 0 to 8 := 0;begin for i in input'range loop

if input(i) = '1' then temp := temp+1; end if; end loop; return temp;end count_one;

beginprocess (clk)begin if rising_edge(clk) then data_out <= std_logic_vector(to_unsigned(count_one(data_in),4)); data_out_int <= count_one(data_in);end if;end process;end Behavioral;

procedure procedure_name (parameter_list) isdeclarations

beginsequential_statements

end procedure_name

architecture bhv of lcd is-- . . . . . . . . . . . . . . . . . . . . . procedure dec4_bcd (signal dec4 : in std_logic_vector(3 downto 0);

signal bcdM : out std_logic_vector(3 downto 0); signal bcdL : out std_logic_vector(3 downto 0)) is

begin case dec4 is

when "0---" | "100-" => bcdM <= (others=>'0'); bcdL <= dec4;

when others => bcdM <= "0001"; bcdL <= dec4 + "0110";

end case;end dec4_bcd; -- . . . . . . . . . . . . . . . . . . . . . begin-- . . . . . . . . . . . . . . . . . . . . .

Este procedimento converteum valor binário de 4 bits paraum valor BCD de 8 bits, onde

bcdL é o dígito menossignificativo e bcdM é odígito mais significativo

Exemploentity Procedute_test isgeneric (size : natural := 4);Port( data_in : in std_logic_vector(size-1 downto 0); data_outMS : out std_logic_vector(size-1 downto 0); data_outLS : out std_logic_vector(size-1 downto 0) ); end Procedute_test;

architecture bhv of Procedute_test isprocedure dec4_bcd (signal dec4 : in std_logic_vector(3 downto 0);

signal bcdM : out std_logic_vector(3 downto 0); signal bcdL : out std_logic_vector(3 downto 0)) is

begin case conv_integer(dec4) is

when 0 to 9 => bcdM <= (others=>'0'); bcdL <= dec4;

when others => bcdM <= "0001"; bcdL <= dec4 + "0110";

end case;end dec4_bcd; begin dec4_bcd(data_in,data_outMS,data_outLS);end bhv;

label: for parameter in range generateconcurrent statements

end generate label;

A construção for … generate pode ser usada para criar um array de componentes,por exemplo:

generic ( R : integer := 3; -- outros generic statements);

-- . . . . . . . . . . . . . . . . . . . . . . . . . . . .

FSM_reg: -- registo de MEFfor i in 0 to R-1 generateREG: FDC port map (CS(i),clk,rst,NS(i));end generate FSM_reg;

REG

next

sta

te (

NS

)

esta

do c

orre

nte

(CS

)

D Flip-Flop with Asynchronous Clear da biblioteca do Xilinx

clk

rst

Exemplo

entity Flip_flop isPort( clk : in std_logic; rst : in std_logic; bit_in : in std_logic; bit_out : out std_logic); end Flip_flop;

architecture MyFF of Flip_flop isbegin process(rst,clk) begin if rst ='1' then bit_out <= '0'; elsif rising_edge(clk) then bit_out <= bit_in; end if; end process;end MyFF;

entity Generate_test isgeneric (size : natural := 8);Port( clk : in std_logic; rst : in std_logic; data_in : in std_logic_vector(size-1 downto 0); data_out : out std_logic_vector(size-1 downto 0)); end Generate_test;

architecture MyArch of Generate_test is component Flip_flop is Port( clk : in std_logic; rst : in std_logic; bit_in : in std_logic; bit_out : out std_logic); end component;begin

FSM_reg:-- registofor i in 0 to size-1 generateREG: Flip_flop port map (clk,rst,data_in(i),data_out(i));end generate FSM_reg;

end MyArch;

library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;use IEEE.NUMERIC_STD.ALL;

package empty is type columns is range 1 to 4; type row is array (columns) of std_logic;end empty;

package body empty is --begin end empty;

library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;use IEEE.NUMERIC_STD.ALL;

use work.empty.all;

entity Test_arrays isPort( Myr1,Myr2,Myr3,Myr4,Myr5 : out row ); end Test_arrays;

Architecture Beh of Test_arrays istype columns is range 1 to 4;type row is array (columns) of std_logic;signal r1 : work.empty.row := ('1', '0', '1', '1');signal r2 : work.empty.row := (1 => '1', 2 => '0', others => '1');signal r3 : work.empty.row := (1 => '1', 2 => '0', 3 to 4 => '1');signal r4 : work.empty.row := (2 => '0', others => '1');signal r5 : work.empty.row := (1 | 3 | 4 => '1', 2 => '0');

begin Myr1 <= r1; Myr2 <= r2; Myr3 <= r3; Myr4 <= r4; Myr5 <= r5;end Beh;