Simplifying SoC Verification using a Generic Approach Verilab are simplifying SoC verification A...

24
© Copyright 2006 Verilab Simplifying SoC Verification using a Generic Approach David Robinson Verilab [email protected]

Transcript of Simplifying SoC Verification using a Generic Approach Verilab are simplifying SoC verification A...

Page 1: Simplifying SoC Verification using a Generic Approach Verilab are simplifying SoC verification A self generating eVC for generic SoC verification •Provides automatic bus verification

© Copyright 2006 Verilab

Simplifying SoC Verification using a Generic Approach

David Robinson

Verilab

[email protected]

Page 2: Simplifying SoC Verification using a Generic Approach Verilab are simplifying SoC verification A self generating eVC for generic SoC verification •Provides automatic bus verification

© Copyright 2006 Verilab 2

Overview

How Verilab are simplifying SoC verification

A self generating eVC for generic SoC

verification•Provides automatic bus verification (infrastructure and

interconnect)

•Provides a platform for the rest of the verification

•Provides mechanisms to isolate the tests from the design

I'm talking about....

Page 3: Simplifying SoC Verification using a Generic Approach Verilab are simplifying SoC verification A self generating eVC for generic SoC verification •Provides automatic bus verification

© Copyright 2006 Verilab 3

Overview

Part 1 (For managers)• Solving my top four problems in SoC verification

• The value of this approach

Part 2 (For engineers)

• Technical overview

Something for everyone....

Page 4: Simplifying SoC Verification using a Generic Approach Verilab are simplifying SoC verification A self generating eVC for generic SoC verification •Provides automatic bus verification

© Copyright 2006 Verilab 4

Verification Problem 1

It's hard to find good verification engineers who

are also language experts

Problem

Remove the need to be a language expert

Solution

Page 5: Simplifying SoC Verification using a Generic Approach Verilab are simplifying SoC verification A self generating eVC for generic SoC verification •Provides automatic bus verification

© Copyright 2006 Verilab 5

Verification Problem 2

It takes too long to write the verification

environment

Problem

Automatically generate the verification

environment from a high-level description

Solution

Page 6: Simplifying SoC Verification using a Generic Approach Verilab are simplifying SoC verification A self generating eVC for generic SoC verification •Provides automatic bus verification

© Copyright 2006 Verilab 6

Verification Problem 3

Previous knowledge is not captured or reused

Problem

Build this knowledge into the verification

environment generator

Solution

Page 7: Simplifying SoC Verification using a Generic Approach Verilab are simplifying SoC verification A self generating eVC for generic SoC verification •Provides automatic bus verification

© Copyright 2006 Verilab 7

Verification Problem 4

Designers have a decision making problem

Problem

Accept that change will occur, and build the

verification environment to cope

Solution

Page 8: Simplifying SoC Verification using a Generic Approach Verilab are simplifying SoC verification A self generating eVC for generic SoC verification •Provides automatic bus verification

© Copyright 2006 Verilab 8

The Added Value

Cheaper

projectsBetter quality

Easier projects Safer projects

Page 9: Simplifying SoC Verification using a Generic Approach Verilab are simplifying SoC verification A self generating eVC for generic SoC verification •Provides automatic bus verification

© Copyright 2006 Verilab 9

Cheaper Projects

•Fewer people are needed

•They can be less skilled

•The verification phase can be shorter

•There are minimal delays when change occurs

Projects cost less because....

Page 10: Simplifying SoC Verification using a Generic Approach Verilab are simplifying SoC verification A self generating eVC for generic SoC verification •Provides automatic bus verification

© Copyright 2006 Verilab 10

Better Quality Verification

•Automatic reuse of verification knowledge

•Tried and tested solution used

Quality improves because....

Page 11: Simplifying SoC Verification using a Generic Approach Verilab are simplifying SoC verification A self generating eVC for generic SoC verification •Provides automatic bus verification

© Copyright 2006 Verilab 11

Easier Projects

•Easier to find the right people

•Easier to get a verification environment running

•Many of the technical and methodological issues of setting

up a complex testbench simply go away

•Reduced pressure on the verification team because they

start finding bugs earlier

Projects get easier because....

Page 12: Simplifying SoC Verification using a Generic Approach Verilab are simplifying SoC verification A self generating eVC for generic SoC verification •Provides automatic bus verification

© Copyright 2006 Verilab 12

Safer Project

•Uses pre-built and pre-verified verification environment that

contains a wealth of project experience and expert knowledge

•Less chance of resource shortages

•Functional bugs caught early (while the designers are still

working on the code)

•Change from the design team does not mean problems and

delays for the verification team

Projects get safer because....

Page 13: Simplifying SoC Verification using a Generic Approach Verilab are simplifying SoC verification A self generating eVC for generic SoC verification •Provides automatic bus verification

© Copyright 2006 Verilab 13

Part 1: Summary

On the latest design we found the first RTL bug

within one day of receiving the RTL and starting

the verification

•1xAHB multi-master bus

•1xAHB Bus Matrix (multi-layer point-to-point)

•2xAPB peripheral busses

•3 bridges

•6 masters

•20 slaves

This is valuable

Page 14: Simplifying SoC Verification using a Generic Approach Verilab are simplifying SoC verification A self generating eVC for generic SoC verification •Provides automatic bus verification

© Copyright 2006 Verilab 14

Part 2: Features

• A high-level text format for

specifying the design's topology,

protocol limitations, address maps,

access limitations, safe and unsafe

memory regions, etc

• Instantiation of the required 3rd party

bus eVCs

• Bus traffic scoreboards

• Customised functional coverage

What does it give me?

• A sequence library for

bus infrastructure tests

• APIs to access design

information without

knowing design details

• A working topology

definition

Page 15: Simplifying SoC Verification using a Generic Approach Verilab are simplifying SoC verification A self generating eVC for generic SoC verification •Provides automatic bus verification

© Copyright 2006 Verilab 15

eVC Usage and Structure

Database

Description of

design

Coverage

Scoreboards

Protocol Interface

Libraries

Virtual SequencesTest

A

P

I

TestTest

API

SequencesBus Inf Testbench

Working Topology

TestTestTestClock Testbench

Working Topology

TestTestTestSecurity Testbench

Working Topology

Project Specific

Customisations

Page 16: Simplifying SoC Verification using a Generic Approach Verilab are simplifying SoC verification A self generating eVC for generic SoC verification •Provides automatic bus verification

© Copyright 2006 Verilab 16

Defining an AHB Master

add master bus_interface dut_instance=<INST>{name : CPU__INST_IF;component: CPU;bus : INST_BUS;protocol : AHB;

<limitations>;add direction: WRITE; </limitations>;

<routing_table>;SRAM__S_IF;INST_BUS__DEFAULT_SLAVE_IF;</routing_table>;};

ahb master INST_BUS CPU__INST_IF 0 FALSE"hresetn" "hclk"

Page 17: Simplifying SoC Verification using a Generic Approach Verilab are simplifying SoC verification A self generating eVC for generic SoC verification •Provides automatic bus verification

© Copyright 2006 Verilab 17

The Working Topology

•Different testbenches need to see different

views of the design

•Or alternatively: Different testbenches do not

need to see the same view of the design

•The working topology file lets you specify:•Which subsystems are to be included

•Which items are black boxed in the HDL

•Which eVCs to use

The what?

Page 18: Simplifying SoC Verification using a Generic Approach Verilab are simplifying SoC verification A self generating eVC for generic SoC verification •Provides automatic bus verification

© Copyright 2006 Verilab 18

Example: Full Topology

CPU DMA

Main Bus (AHB)

Memory

M

CryptoBridge

M

M

S

SSS

Peripheral Bus (APB)

GPIOIRQ

S S

UART

S

Master bus interface

S Slave bus interface

M

Key

MInstruction Bus (AHB)

Memory

S

Memory

S

Page 19: Simplifying SoC Verification using a Generic Approach Verilab are simplifying SoC verification A self generating eVC for generic SoC verification •Provides automatic bus verification

© Copyright 2006 Verilab 19

Example: Instruction Subsystem Only

CPU DMA

Main Bus (AHB)

Memory

M

CryptoBridge

x

M

S

SSS

Peripheral Bus (APB)

GPIOIRQ

S S

UART

S

A black boxed component

xA black boxed bus interface

replaced by an active agent

M

Key

MInstruction Bus (AHB)

Memory

S

Memory

S

xA component removed from

the working topology

Page 20: Simplifying SoC Verification using a Generic Approach Verilab are simplifying SoC verification A self generating eVC for generic SoC verification •Provides automatic bus verification

© Copyright 2006 Verilab 20

Example: Use Case Testing

CPU DMA

Main Bus (AHB)

Memory

M

CryptoBridge

x

M

S

SSS

Peripheral Bus (APB)

GPIOIRQ

S S

UART

S

A black boxed component

replaced by an eVC

xA bus interface shadowed

by a passive agent

M

Key

MInstruction Bus (AHB)

MemoryS

MemoryS

Page 21: Simplifying SoC Verification using a Generic Approach Verilab are simplifying SoC verification A self generating eVC for generic SoC verification •Provides automatic bus verification

© Copyright 2006 Verilab 21

Example Working Topology

<use> AHB t; // use the eVC t[rue]/f[alse]APB f; // use the eVC t[rue]/f[alse]

</use>

<subsystem> MAIN_BUS t; // include the sub system t[rue]/f[alse]INST_BUS f; // include the sub system t[rue]/f[alse]PERIPH_BUS t; // include the sub system t[rue]/f[alse]

</subsystem>

<topology_item>bus hdl_included MAIN_BUS;bus hdl_included INST_BUS;com hdl_excluded CPU;bif hdl_excluded CPU__DATA_IF;bif hdl_excluded CPU__INST_IF;

</topology_item>

Page 22: Simplifying SoC Verification using a Generic Approach Verilab are simplifying SoC verification A self generating eVC for generic SoC verification •Provides automatic bus verification

© Copyright 2006 Verilab 22

Dealing with Change

TestA

P

I

eVC

TestTest

TestA

P

I

TestTest

RTL

RTL

TestA

P

I

TestTestRTL

Protects test writer from changes to

the testbench's implementation

Protects test writer from changes to

RTL implementation

Page 23: Simplifying SoC Verification using a Generic Approach Verilab are simplifying SoC verification A self generating eVC for generic SoC verification •Provides automatic bus verification

© Copyright 2006 Verilab 23

Example API

get_bus_sequence_driver(name)get_interface_sequence_driver(name)get_register_sequence_driver(name)

Accessing testbench components

get_bus_interfaces(filter)get_address_ranges_for_slave(slave_name)get_all_reachable_endpoints(master_name, filter)get_all_masters_who_can_reach_me(slave_name, filter)

Accessing database information

Page 24: Simplifying SoC Verification using a Generic Approach Verilab are simplifying SoC verification A self generating eVC for generic SoC verification •Provides automatic bus verification

© Copyright 2006 Verilab 24

Summary

Current Status:• Still adding new features

• Currently being used on three designs by different teams

• 1-4 days to first simulation

• Attracting attention from other design teams

• Influencing eVC and RTL IP design guidelines

It's bringing real value to SoC verification

projects

Download the paper from www.verilab.com


A Top Down Approach to Mixed Signal SoC Verification

A Top Down Approach to Mixed Signal SoC Verification

Interconnect Verification for SOC

Interconnect Verification for SOC

ARM v8 SoC HW/SW Integration & Verification Solutionarmtechforum.com.cn/2014/sz/C-4_Cadence_SZ.pdf · 2019-09-04 · ARMv8-Based SoC HW/SW Integration and Verification Solution. ...

ARM v8 SoC HW/SW Integration & Verification Solutionarmtechforum.com.cn/2014/sz/C-4_Cadence_SZ.pdf · 2019-09-04 · ARMv8-Based SoC HW/SW Integration and Verification Solution. ...

The Big Brain Theory -Visualizing SoC Design & Verification Data

The Big Brain Theory -Visualizing SoC Design & Verification Data

Solutions for Mixed-Signal SoC Verification Using Real ... · Solutions for Mixed-Signal SoC Verification Using Real Number Models Mixed-Signal Verification Challenges In all types

Solutions for Mixed-Signal SoC Verification Using Real ... · Solutions for Mixed-Signal SoC Verification Using Real Number Models Mixed-Signal Verification Challenges In all types

SOC verification using SV

SOC verification using SV

SoC Security Verification

SoC Security Verification

SoC Verification Strategies for Embedded Systems …ssal.kaist.ac.kr/~kyung/ppt-keynote/SoC Verification...SoC Verification Strategies for Embedded Systems Design November 5-6, 2003

SoC Verification Strategies for Embedded Systems …ssal.kaist.ac.kr/~kyung/ppt-keynote/SoC Verification...SoC Verification Strategies for Embedded Systems Design November 5-6, 2003

Rethinking SoC Verification - Synopsys Paper March 2014 Rethinking SoC Verification Enabling Next-Generation Productivity & Performance Rebecca Lipon Senior Product Marketing Manager,

Rethinking SoC Verification - Synopsys Paper March 2014 Rethinking SoC Verification Enabling Next-Generation Productivity & Performance Rebecca Lipon Senior Product Marketing Manager,

HPC Computing & SoC Design @ Sandia National Laboratories€¦ · HPC Computing & SoC Design @ Sandia National Laboratories Design Automation for HPC, Clouds, ... SoC Verification

HPC Computing & SoC Design @ Sandia National Laboratories€¦ · HPC Computing & SoC Design @ Sandia National Laboratories Design Automation for HPC, Clouds, ... SoC Verification

ARM Based SoC verification v1 - T&VS€¢ ARM based SoC Verification challenges ... • RISC processor cores for portable devices and mobile ... • Pre-empts verification done with

ARM Based SoC verification v1 - T&VS€¢ ARM based SoC Verification challenges ... • RISC processor cores for portable devices and mobile ... • Pre-empts verification done with

MIPI DevCon 2016: Verification of Mobile SOC Design (UFS)

MIPI DevCon 2016: Verification of Mobile SOC Design (UFS)

FPGA-based Verification Methodology of SOC-type …soc.yonsei.ac.kr/Abstract/International_conference/pdf/FPGA-based... · FPGA-based Verification Methodology of SOC-type CMOS Image

FPGA-based Verification Methodology of SOC-type …soc.yonsei.ac.kr/Abstract/International_conference/pdf/FPGA-based... · FPGA-based Verification Methodology of SOC-type CMOS Image

SoC Level Formal Verification - Test and Verification … Verification and SoC‐Level Verification • Formal verification – Traditionally operates at block level – Focuses on

SoC Level Formal Verification - Test and Verification … Verification and SoC‐Level Verification • Formal verification – Traditionally operates at block level – Focuses on

SOC Testing - University of Cincinnatiwjone/soc.pdf · SOC testing.26 SOC Testable Design Flow ... Verification SOC Testable Design Rules. SOC testing.27 Conclusions! SOC testing

SOC Testing - University of Cincinnatiwjone/soc.pdf · SOC testing.26 SOC Testable Design Flow ... Verification SOC Testable Design Rules. SOC testing.27 Conclusions! SOC testing

Approaches for Power Management Verification of SOC

Approaches for Power Management Verification of SOC

Addressing SOC/IP Verification Framework Creation with UVM ... · PDF fileAddressing SOC/IP Verification Framework Creation with UVM ... • IP verification using Re-use of IP level

Addressing SOC/IP Verification Framework Creation with UVM ... · PDF fileAddressing SOC/IP Verification Framework Creation with UVM ... • IP verification using Re-use of IP level

Design Verification to Application Validation of a Multiprocessor SoC

Design Verification to Application Validation of a Multiprocessor SoC

ARM Based SOC Design and Verification - TVS | Test and

ARM Based SOC Design and Verification - TVS | Test and

SoC Verification Strategies for Embedded Systems Design

SoC Verification Strategies for Embedded Systems Design