Simplification of Boolean functions There are 3 common methods: 1. Boolean algebra
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Simplification of Boolean functions There are 3 common methods: 1. Boolean algebra – The basis for all methods – Difficult to see the best path to take and to know when you are finished 2. Karnaugh maps – Fast and easy for 2 – 6 variables – Pictorial approach based on recognition of patterns – Difficult for large numbers of variables 3. Tabulation methods – Tedious to perform by hand, but well suited to computer implementation – No limit on the number of variables – Examples: Quine-McCluskey, Expresso-II by UC Berkeley – Discussed in online supplement (not covered in this course) Reading Assignment: Chapter 2 in Logic and Computer Design Fundamentals, 5 th Edition by Mano 1 Chapter 2 EGR 270 – Fundamentals of Computer Engineering
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Chapter 2 EGR 270 – Fundamentals of Computer Engineering. 1. Reading Assignment: Chapter 2 in Logic and Computer Design Fundamentals, 4 th Edition by Mano. Simplification of Boolean functions There are 3 common methods: 1. Boolean algebra The basis for all methods - PowerPoint PPT Presentation
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Simplification of Boolean functionsThere are 3 common methods:1. Boolean algebra
– The basis for all methods– Difficult to see the best path to take and to know when you are finished
2. Karnaugh maps – Fast and easy for 2 – 6 variables– Pictorial approach based on recognition of patterns– Difficult for large numbers of variables
3. Tabulation methods– Tedious to perform by hand, but well suited to computer implementation– No limit on the number of variables– Examples: Quine-McCluskey, Expresso-II by UC Berkeley– Discussed in online supplement (not covered in this course)
Reading Assignment: Chapter 2 in Logic and Computer Design Fundamentals, 5th Edition by Mano
1Chapter 2 EGR 270 – Fundamentals of Computer Engineering
Karnaugh Maps (K-maps)• Essentially a 2D truth table arranged in a table or map so that adjacent cells in
the map differ in only one bit position.• Each cell in the map corresponds to a minterm.• Combining 1’s in the Kmap into groups of 1, 2, 4, 8, etc. can yield a quick minimization of a Boolean function.• Kmaps are most commonly used for functions involving 2-6 variables.
2-variable K-mapsThe K-map has 22 = 4 cells.
mx
y 0 1
0
1
0
m3 m2
m1
MSB
Example: Use a K-map to minimize the function f(x,y) = x’y + xy’ + xy
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3-variable K-mapsThe K-map has 23 = 8 cells.
Example: Use a K-map to minimize each function below.1.
m x
yz 00 01
0
1
0 m
5 m
4
m 1
MSB m 11 10
3 m
6 m
7
m 2
Note the strange ordering
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0 0 1 1
1 0 0 1
x yz
00 01 11 10
0
1
Group is x’y(x = 0 and y = 1)
“Wraparound” group is xz’
(x = 1 and z = 0)Answer: f(x,y,z) = x’y + xz’
2. f(x, y, z) = (0, 1, 5, 7)
3. f(x, y, z) = xyz + x’yz + x’y’z’ + y’z
4. f(a, b, c) = ab’ + ac + ab + b
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4-variable K-maps The K-map has 24 = 16 cells.
Example: Use a K-map to minimize each function below.
mAB
CD 00 01
00
01
0
m5 m4
m1
A = MSB m 11 10
3
m6 m7
m2
Note the strange ordering
m11
10
12
m9 m8
m13 m15
m10 m11
m14
0 1 1 0
0 0 0 1
0 0 0 0
1 1 1 1
AB CD 00 01 11 10
00
01
11
10
1 1 0 1
1 1 0 0
0 0 0 1
1 1 0 1
AB CD 00 01 11 10
00
01
11
10
1. 2.
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Example: Use a K-map to minimize each function below.1. f(A, B, C, D) = A’B’C’ + A’CD + B’CD’ + ABD + AB’D + AB’C’D’2. f(A, B, C, D) = B’D’ + C’D + BD’ + A’D + BC
Group size vs. number of literals:Note how the number of literals in a term is reduced by one each time the size of grouping is doubled. For the 4-variable K-map:
Size of Number ofGrouping Literals
1 42 34 28 1
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Prime ImplicantsPrime Implicant – a product term which cannot be combined with other terms to yield a term with fewer literals. Hint: A prime implicant corresponds to a maximal grouping in a Kmap.Essential Prime Implicant – a prime implicant that covers at least one minterm of the function that is not covered by any other prime implicant.A good way to approach finding minimal expressions in Karnaugh maps is to find essential prime implicants first. Once those groups have been drawn on the map, it is easier to see what other groupings would most efficiently cover the rest of the minterms.In general, a function can be expressed as:F = sum of essential prime implicants + (some combination of non-essential prime implicants)
Example: Identify all prime implicants and all essential prime implicants in f(A, B, C, D) = (0, 1, 3, 4, 5, 7, 11, 15)
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Example: Use a K-map to minimize each function below. Identify the essential prime implicants in each problem.
0 1 1 0
1 1 0 1
1 0 1 0
1 0 1 1
AB CD 00 01 11 10
00
01
11
10
1 1 0 1
1 1 1 0
0 1 1 1
1 1 0 1
AB CD 00 01 11 10
00
01
11
10
1. 2.
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5-variable K-maps The K-map has 25 = 32 cells. Note odd arrangement of the variables ABCDE. This arrangement results in the left half of the K-map having the same minterm ordering as a 4-variable map. Note that groups combine as if the left map was over the top of the right map (like 3D chess).
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These two groups combine to form B’DE’
m0
BCADE
000 001 011 010
00
01
11
10
1 00 101 111 110
m1 m3 m2
m4 m5 m7 m6
m12 m13 m15 m14
m8 m9 m11 m10
m16 m17 m19 m18
m20 m21 m23 m22
m28 m29 m31 m30
m24 m25 m27 m26
These two groups do NOT combine!
5-variable K-maps (alternate minterm ordering) Shown below is an alternate arrangement for the variables A, B, C, D and E.Note that changing the arrangement of the variables changes the ordering of the minterms.
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m0
ABCDE
000 001 011 010
00
01
11
10
1 00 101 111 110
m1 m3 m2
m8 m9 m11 m10
m24 m25 m27 m26
m16 m17 m19 m18
m4 m5 m7 m6
m12 m13 m15 m14
m28 m29 m31 m30
m20 m21 m23 m21
These 8 minterms combine to form AE’
(A = 1 and E = 0)
Example: Use a K-map to minimize the function below. Carefully consider how to label A, B, C, D, and E on the K-map.
F(A, B, C, D, E) = (1, 2, 5, 6, 8, 10, 12, 14, 17, 18, 21, 22, 24, 26, 28, 30)
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000 001 011 010
00
01
11
10
1 00 101 111 110
SOP and POS Expressions from K-mapsThe examples so far have all generated minimal SOP expressions. POS expressions can be formed as follows:1. Group 0’s in the K-map instead of 1’s (these groupings correspond to F’).2. Find a minimal SOP expression for F’.3. Find F from F’ by applying DeMorgan’s theorem. This yields a minimal
POS expression.
Example: Determine a POS expression for F(A, B, C, D) = (1 - 3, 6, 9 - 11). Draw the corresponding circuit.
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0 1 1 1
0 0 0 1
0 0 0 0
0 1 1 1
AB CD 00 01 11 10
00
01
11
10
DBDCBA F
BD DC AB F
BD DC AB F
BD DC AB F
:Solution
With practice it is easy to go straight from the first to the last step.
Example: Determine SOP and POS expressions for f(A, B, C, D) = (0, 2, 4-9, 13-15). Draw the corresponding circuits.
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ABCD 00 01 11 10
00
01
11
10
ABCD 00 01 11 10
00
01
11
10
Example: Determine SOP and POS expressions for f(A, B, C, D) = (0-2, 4-5, 8-10,14). Draw the corresponding circuits.
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ABCD 00 01 11 10
00
01
11
10
ABCD 00 01 11 10
00
01
11
10
Note: We cannot in general predict whether the minimal SOP expression or minimal POS expression will result in the fewest gates. It is often useful to check both expressions to see which gives the best result.
“Don’t Care” conditionsThere are often unused input combinations or input combinations that are illegal and should never occur. In such cases, we often “don’t care” what the output is since the input should never occur anyway. We typically represent “don’t cares” in a K-map using either “d” or “X”.
Example: Find a minimal SOP expression for f(A, B, C, D) = (1, 8, 9 ) + d(0, 6, 10, 11).
Rule: Include a “don’t care” in a grouping only if it helps to make for larger groupings. It is not necessary to include all “don’t cares” in groupings.
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X 1 0 0
0 0 0 X
0 0 0 0
1 1 X X
AB CD 00 01 11 10
00
01
11
10
Solution: F = B’C’(Note that AB’ and A’BCD’are both unnecessary)
Example: BCD inputs are used to represent the digits 0 – 9, so the input codes corresponding to 10 – 15 are illegal inputs. Find both minimal SOP and POS expressions for f(A, B, C, D) = (0, 2-5, 7) + d(10-15).
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ABCD 00 01 11 10
00
01
11
10
Recognizing XOR and XNOR functions from K-mapsFirst a review of the various ways to express the outputs of XOR and XNOR gates: x
y
x y
Note: Diagonal or staggered groupings in K-maps often indicate that using XOR gates will yield a simpler solution than either SOP or POS form.Example: Minimize each function shown below. Make use of XOR gates as much as possible. Compare the number of gates using XOR’s to the number that would be required in SOP form.
xyz
00 01
0
1
11 10
0 1 0 1
1 0 01
1. x
yz 00 01
0
1
11 10
0 0 0 0
0 1 10
2.
yx y xy x F
y xy x yx yx y xy x F
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Example: Minimize each function shown below. Make use of XOR gates as much as possible. Compare the number of gates using XOR’s to the number that would be required in SOP form.
1 0 1 0
0 1 0 1
1 0 1 0
0 1 0 1
ABCD
00 01 11 10
00
01
11
10
0 0 1 1
1 1 0 0
0 0 1 1
1 1 0 0
ABCD
00 01 11 10
00
01
11
10
3. 4.
0 0 0 1
0 0 1 0
0 1 0 0
1 0 0 0
ABCD
00 01 11 10
00
01
11
10
5.
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Cost CriteriaWe need some sort of measure that will indicate how efficiently logic expressions can be implemented. Different methods include:1) Literal cost2) Number of logic gates3) Gate input cost4) Number of gate delays
Literal cost – defined earlier as the number of literal appearances in a logic expression. A literal is any complemented or uncomplemented variable.
Example: F = AB + A’B’ + AC has 6 literals
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Propagation delay – the amount of time for the output of a gate to respond to a change in the input. Example: tp = 10 ns
Number of gate delays – The number of gate delays for the longest path through a logic circuit. For example, in the logic diagram below:• If D changes, there is only 1 gate delay before F responds• If C changes, there are 2 gate delays before F responds• If A or B change, there are 3 gate delays before F responds (the path for
signal A is highlighted in green)• So the number of gate delays (longest path) = 3
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B
A
F
C
D
21Chapter 2 EGR 270 – Fundamentals of Computer EngineeringGate Input CostGate input cost is simply the number of inputs to all gates if the implementation corresponds exactly to the expression given. Note that input inverters are typically not counted as inputs are often available in complemented or uncomplemented form.
Example: Find the gate input cost for the circuit below. It is easy! Just count the inputs (numbered 1-6 below)
1
2
3
4
5
6
B
A
F
C
D
Gate input cost = 6
Example: Evaluate each expression using various cost criteria.
F = ABCD + A’B’C’D’ Literal cost: __________ Number of gates: _______Gate input cost: __________Number of gate delays: __________
F = (A’+B)(B’+C)(C’+D)(D’+A) Literal cost: __________ Number of gates: _______Gate input cost: __________Number of gate delays: __________
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Which method is best? Gate input cost is considered to be a better measure than literal cost of the number of logic gates. Gate input cost is a good measure for contemporary logic implementations since it is proportional to the number of transistors and wires used in implementing a logic circuit. However, the number of gate delays is also important as it relates to the speed of the circuit. There is often a tradeoff between these two.
Gate input cost(area or size of the circuit)
Number of gate delays(speed of the circuit)tradeoff
Minimizing Circuits with Multiple OutputsWhen circuits have multiple outputs, each output can be minimized separately, but there may be opportunities to share gates between the output expressions. Additionally, it may be useful to consider K-map groupings that are less than maximal in order to share gates.
Example: A circuit has two outputs, F1(A,B,C) = (1,3,4,5) andF2(A,B,C) = (1,3,6,7). Implement the circuit with the minimum number of gates for the entire circuit.Solution: Note that both outputs include the term x’z so they can share a gate.
23Chapter 2 EGR 270 – Fundamentals of Computer Engineering
xyz
00 01
0
1
11 10
0 1 1 0
1 1 00
xyz
00 01
0
1
11 10
0 1 1 0
0 0 11
Shared term (gate)
F1 = x’z + xy’ F2 = x’z + xy
Shared term (gate)
y’x
x’z
xy
F1
F2
Sharedgate
Example: A circuit has two outputs, F1(A,B,C,D) = (0,1,4-7,13) andF2(A,B,C,D) = (0-3,6,7,13). A) Minimize each circuit separately. Find the total number of gates and the
gate input cost.B) Implement the circuit to achieve the minimum number of gates for the
entire circuit. (Hint: Look for non-maximal groups in order to share gates.) Find the total number of gates and the gate input cost.
C) Compare A and B.Solution:
24Chapter 2 EGR 270 – Fundamentals of Computer Engineering
