Stéphane Bernabé, Ségolène Olivier, Bertrand Szelag, Daivid Fowler,

Christophe Kopp | OPTICS, Dresden, 23-03-16

Silicon Photonics :

Towards Heterogeneous and Multi-layer

Integration for High Density Circuits

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• Silicon Photonics at Leti

History

Devices library & process flow

Examples of circuits and modules

Next challenges

• III-V integration

Process development

Achievements

• Advanced multilayer platforms

Process developments

Achievements

• Other platform evolution

TSV

Copper pillar for self alignment of microoptics

• Conclusion

PACKAGING FOR PHOTONICS

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PHOTONICS AT LETI

French research-and-technology organization with activities in energy, IT, healthcare, defence and security. Budget 318 M€.

1,900 collaborators (250 PhDs)2800 patents (>300 /yr)680 publications /yr, 64 stratups

Photonic DepartmentEst. 1978, 300 researchers, 60M€ budget

Dedicated Silicon Photonics Lab

8,500 m² clean roomsFor 200 and 300 mm wafers fab, operated 24/7

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SILICON PHOTONICS STORY

1985 Soref’s paper

on Si optical

properties for

modulation 1988-2003 Bookham

ASOC devices

2001 Luxtera creation

2016 : Intel, ST,

Acacia,…

launch SiPho

products

2002 J.M. Fedeli

Pioneered SiPho at Leti

2008-2012

HELIOS

project

2012-…

III-V Lab

IRT Nanoelec

2017

O-Band MPW offer

Si

SiO

2

SiO2

DFB@1310nm + 32G EAM + SOA

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BUILDING BLOCKS FOR OPTICAL DATA

TRANSMISSION

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TECHNOLOGY KEY PROCESS FEATURES

• 200 mm Si photonics platform Substrates : 8’’ SOI 310nm, compatible

with ST foundry (300mm) 190 steps 24 litho levels 40 metrology/control steps

• 300mm Si photonics platform (dev)

• Process building blocks Multilevel silicon patterning PN Silicon junctions PiN Germanium junctions Integrated resistance (heater) Planarized BEOL : 2 AlCu routing levels UBM for flip-chip assembly

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BASELINE TECHNOLOGY INTEGRATION SCHEME

o Define all the photonic deviceso Several silicon thicknesses and waveguide architectures

o Modulator junction formation & activation

o Photodetector patterningo Germanium selective epitaxy

o Photodetector contact formation

o Si Modulator contact silicidation

o Metal interconnectiono Metal heater definition for wave length tuning

CMOS standard process

CMOS-based process with photonic dedicated optimizations

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TECHNOLOGY PASSIVE DEVICE LIBRARY

Ins. Loss 2-3dB

Xtalk >20dB

1dB BW 1.5nm

Ins. Loss <2.5dB

1dB BW 30 nm

Ins. Loss < 4dB

1dB BW 30 nm

Width 400 nm

Prop. loss 1.5dB/cm

Width 1.8µm

Prop. loss 0.15dB/cm

Width 320nm

Prop. loss 3.5dB/cm

Width 350nm

Prop. loss 3.5 dB/cm

Loss < 0.5dB

balance 3%

Loss < 0.25dB

Xtalk >35dB

O-Band, 1310nm

Szelag et al., "Multiple wavelength silicon photonic 200mm R&D platform for 25Gb/s and above applications”, Photonics Europe 2016Szelag et al., ” CMOS compatible 200mm silicon photonic platform suitable for high bandwidth applications” SSDM, 2017

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1D – single pol.

2D – Dual pol.

Kopp et al., Silicon photonic circuits: on CMOS integration, fiber optical coupling and packaging, IEEE-JSTQE, 2010

S. Plantier, D. Fowler, K. Hassan, O. Lemonnier and R. Orobtchouk, "Impact of scattering element shape on polarisation dependent loss

in two dimensional grating couplers," 2016 IEEE 13th International Conference on Group IV Photonics (GFP), Shanghai, 2016, pp. 76-77.

FIBER COUPLERS – O BAND

200mm process line

2D

1D

PDL < 0,5 dB (2D grating)

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INTEGRATED PN JUNCTION MODULATOR

MZM Length Vpi.Lpi RF BW 3dB Popt OUT MZM

4mm 1.9 V.cm 25GHz -11.8dBm

3mm 1.9 V.cm 28GHz -9.5dBm

2mm 1.9 V.cm 35GHz -8.5dBm

Losses 0.55 dB/mm

Electro-optical characteristics Modulation characteristics

B. Szelag, SSDM 2017

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BUTT-COUPLED SIGESI PHOTODIODE

W=0.8µm - 30Gb/s NRZ

W=0.8µm

Width 0.8µm

Length 15µm

Responsivity > 1.05A/W

Dark current @ -2V 5 nA

BW @ -2V > 40GHzB. Szelag, SSDM 2017

O-Band , 1310nm

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HIGH DATA RATE MODULES

4 × 25Gbps receiver module • WDM and SDM versions

• < -12dBm sensitivity at 10-9 BER

• EIC with 4pJ/bit consumption

• TIA design : ST microelectronics

Bernabé et al., OIC 2016, Paper MB3

Castany et al., ESTC 2016

Reflective Tx for FTTH (EU FABULOUS

project)• QAM16 transmission on a single fiber

• Dedicated MZM segmented CMOS driver

Straullu et al., ECOC PDP, 2016

Menezo et al., JLT, 34,10,2016

EIC

0.8 x 1.3 mm²

Low power 25Gbps

photoreceiver• 50µm pitch microbump

• 170 fJ/bit

• -15 dBm sensitivity

• TIA design : Caltech

Saaedi et al.. J. Lightwave Tech.,

2015

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NEXT CHALLENGES

• Silicon Photonics address circuits of increasing

complexity• Hundreds of optical functions on a chip

• Requires dedicated PDK in EDA tools

• Broadband coupling required for WDM modules

• Ease routing using multilayer photonics

• Laser source integration• Several competing technologies

• Direct bonding approach : require CMOS compatibility

• Co-integration with complex « host chips »• FPGA or switches with optical IOs

• Manycore computers architectures

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Growth of the III-V wafers

2’’, 3’’, 4’’III-V die or wafer bonding

on processed SOI InP substrate

removal

Processing of SOI wafers

8’’ or 12’’

(modulators, detectors,

passive waveguides, etc.)

Processing of III-V dies/wafer 4’’ or 8’’

Metallization of lasers, modulators and detec tors

Heterostructure

3µm- thick

HETEROGENEOUS III-V INTEGRATION

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INTEGRATED TRANSMITTER

Co-integration of hybrid III-V/Si DBR laser + Si Mach-Zehnder modulator

• Laser drive current : 100 mA• Laser wavelength : 1303.5 nm

• MZM length : 4 mm• Voltage sweep : 2.5 Vpp in push-pull

T. Ferrotti et al., « Co-integrated 1.3 µm hybrid III-V/Silicontunable laser and silicon Mach-Zehnder modulatoroperating at 25 Gb/s », Opt. Exp. , 30379 (2016)

25 Gb/s Transmissionover 10 kmER=4.7 dB

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HYBRID III-V/SI LASER – TARGETED PROCESS

Final objectives:o CMOS compatible process for silicon parto III-V die bonding on silicono 200 or 300mm Si waferso Compatible with mature silicon photonic platformo Laser process steps cmos compatible process:

No noble metals Conventional patterning steps

o Planarized multi-metal level BEOL

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PRELIMINARY STUDIES:

CMOS COMPATIBLE CONTACTS ON III-V

o Best choice: Ni2P wo annealing for n-InP and Ni with 350°C annealing for P-InGaAs

o Integration constraint & process cost => use the same contact for n-InP and P-InGaAs

E. Ghegin, Ph. Rodriguez, M. Pasquali, I. Sagnes, J. L. Labar, V. Delaye, T. Card, J. Da Fonseca, C. Jany, F.

Nemouchi, CMOS-Compatible Contacts to n-In, IEEE Trans. Electron Devices 64 (2017) 4408-4414.

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OPTICAL CHARACTERIZATION

B. Szelag, IEDM 2017

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• Silicon on silicon

Switching matrix, …

• Silicon Nitride on silicon circuits

Low loss platform (<1dB/cm)

Reduced optical confinement

Low thermal sensitivity

MULTIPLE PHOTONIC LAYERS

[1] C; Kopp, “Mature 25Gb/s silicon photonic platform towards multi-layer circuits for high integration level applications”, Photoptics 2017

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ADVANCED GRATING COUPLERS

• Leveraging Si/SiN multilayer

Stack

• Hybrid SiN/Si fibre grating couplers

allow a better IL/BW compromise for

cWDM

Si std: (black line)

IL median: 2dB

-1dB BW median: ~25nm

SiN/Si: (green line)

IL median: 2,9dB

-1dB BW median: >50nm

Q. Wilmart et al, unreleased paper

O-BAND CWDM GRATING COUPLERS

Wavelength (nm)

(c)

SiN

/Si S

PG

C M

ax

. cW

DM

IL (d

B)

Wavelength (nm)

(c)

SiN

/Si S

PG

C M

in. IL

(dB

)

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SIN MUX/DEMUX: ECHELLE GRATING

DEMUX sensitivity to temperature

DEMUX transmission (DUV litho) DEMUX transmission (e-beam litho)

DUV ebeam

IL (dB) 1.5 -

4.7

0.8 – 2.4

BW @-

1dB

10nm 10nm

X-talk 10 dB >20 dB

C. Sciancalepore, SSDM 2017

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ADVANCED PACKAGING

“Standalone” “System-in-package”

TL ~ 50 mm

TL ~ 20 mm

S. Bernabé, K. Rida, S. Menezo,

IEEE Trans. Comp. Mfg and Pkg, 2016

L. Fourneaud, Internal report

Abs(S12)

TSV

WB

THROUGH SILICON VIAS / PHOTONIC INTERPOSER

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• Photonic assisted processorMulti-cores bottlenecks

OPTICAL NETWORK ON CHIP

Y. Thonnart, ISSCC 2018

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TAKE AWAY

Standard SiPho platforms need to be upgraded to

adress future applications (CWDM, ONoC…)

• Multilayer Photonics• Definitely needed for WDM applications

• Laser source integration• Full flow integration validated

• 3D Advanced packaging for photonics• Enabler for System In Package and ONoC architectures

Thank you for your attention