Silicon – On - Insulator (SOI). SOI is a very attractive technology for large volume integrated...
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Transcript of Silicon – On - Insulator (SOI). SOI is a very attractive technology for large volume integrated...
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Silicon – On - Insulator
(SOI)
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SOI is a very attractive technology for large volume integrated circuit production and is particularly good for low – voltage, low power and high speed digital systems
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Advantages of SOI technology over bulk technology
SOI wafers potentially offer:•Perfect transistor isolation•Higher packaging density•Reduced parasitic drain capacitance
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Advantages of SOI technology over CMOS technology
• Excellent lateral and vertical isolation of active devices from substrate
eliminating inter-device leakage and latch-up in CMOS devices
Effective reduction of substrate coupling, allowing higher quality inductors with increased Q factor
Effective reduction of interference and cross talk between mixed signal devices
Reduced soft errors from radiation (electron – hole pair generation)
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• Faster device operation due to reduced parasitic capacitance
• Lower power consumption due to lower operating voltages
• Reduced die area per function – reduced area required for lateral junction isolation, resulting from the absence of wells and the possibility of the possible direct contact of the source and drain diodes in the NMOS and PMOS transistors
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• Performance improvement equivalent to the next technology node without scaling
• Potential to simplify device fabrication steps fewer mask and ion implantation steps, due to
the elimination of wellsLess complex lithography and etching required
to achieve next generation performance
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SOI structure
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SOI applications
This can be segmented into three categories depending on the BOX layer asThick BOX layer wafers Thin BOX layer wafers Ultra thin BOX layer wafers
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Thick BOX layer wafers
Si layer thicker than one micron – 1000nm•Power switching devices•High speed bipolar devices•MEMSi.Military ii.Aerospaceiii.Industrial
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Thin BOX layer wafers
• CMOS IC applicationsi. PDA / Hand setsii. Mainframesiii.Portable wireless devicesiv.Automotivev. Workstations
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Ultra thin BOX layer wafers
• 0.1 micron CMOS fabricationi. High end PCii. Servers
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SOI challenges• Cost• Continuity and thickness uniformity of the BOX
layer• Defects like voids and inclusions in BOX• SOI CMOS devices exhibit parasitic phenomenon• Floating body effects• Self heating effects - due to thermal insulation of
the device from the substrate by the BOX layer• Floating body leading to increased D-S leakage
currents
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Types of SOI wafers
• PDSOI – silicon surface layer is thicker than the depth of the depletion region in the transistor’s channel
• FDSOI - silicon surface layer is equal to the depth of the depletion region in the transistor’s channel
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• This also depends on the silicon layer thickness above the BOX layer and the doping concentration in the channel
• FDSOI – channel doping concentration is low enough such that the gate depletion region extends throughout the entire thickness
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• Si surface layer thicker than 200nm – PDSOI• Si surface layer thickness reduced to about
100nm - FDSOI • The depletion layer of PDSOI does not reach
through the entire silicon channel / body region• PD material usually has a Si thickness greater
than 0.15μm• For FD devices, the SOI film is thinner than the
device depletion width• In FDSOI, there is no body region of the MOS
device that can be charged, hence no floation body
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SOI fabrication
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Separation by Implantation
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Smart Cut
Implant with hydrogen and anneal
Oxidized, annealed
Flip implanted wafer onto substrate and bond the wafers
Split wafer along the stress fracture
Polish
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Smart cut - unibond
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Grind and etch back process
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Epitaxial Layer transfer (Eltran)
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