Silicon Analog Components978-1-4939-2751... · 2017. 8. 26. · Badih El-Kareh PIYE Cedar Park, TX...

Silicon Analog Components

Badih El-Kareh • Lou N. Hutter

Silicon Analog ComponentsDevice Design, Process Integration,Characterization, and Reliability

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Badih El-KarehPIYECedar Park, TXUSA

Lou N. HutterLou Hutter ConsultingPlano, TXUSA

ISBN 978-1-4939-2750-0 ISBN 978-1-4939-2751-7 (eBook)DOI 10.1007/978-1-4939-2751-7

Library of Congress Control Number: 2015937528

Springer New York Heidelberg Dordrecht London© Springer Science+Business Media New York 2015This work is subject to copyright. All rights are reserved by the Publisher, whether the whole or partof the material is concerned, specifically the rights of translation, reprinting, reuse of illustrations,recitation, broadcasting, reproduction on microfilms or in any other physical way, and transmissionor information storage and retrieval, electronic adaptation, computer software, or by similar or dissimilarmethodology now known or hereafter developed.The use of general descriptive names, registered names, trademarks, service marks, etc. in thispublication does not imply, even in the absence of a specific statement, that such names are exempt fromthe relevant protective laws and regulations and therefore free for general use.The publisher, the authors and the editors are safe to assume that the advice and information in thisbook are believed to be true and accurate at the date of publication. Neither the publisher nor theauthors or the editors give a warranty, express or implied, with respect to the material contained herein orfor any errors or omissions that may have been made.

Printed on acid-free paper

Springer Science+Business Media LLC New York is part of Springer Science+Business Media(www.springer.com)

To my family:Itte-Dorothee, Oliver, Linda,Robert, and Kay

B.E.K

For my mother.L.N.H

Foreword

I came home from work one night sometime in early 2001 and told my wife andkids that I had been promoted to run part of the analog business at TexasInstruments. Both my kids looked at me with an odd expression, then my son said,“Why would you want to be in anything analog—analog is dead and the world isgoing digital!”

Well, he was both right and wrong.Computers have evolved significantly since their invention decades ago. They

have moved from being specialized instruments housed in top secret rooms thatonly a few people knew how to use to being ubiquitous, handheld (or evenimplanted!) devices that nearly everyone uses on a daily basis, and hardly anyonecan live without. The digitization of the world enabled this and has fostered thesignificant growth of many new markets. To make things digital, you have to firstconvert them from the “real world”—which of course is analog. And to do this, youneed analog components. In fact, every time you make something more digital, youneed to use even more analog to do that!

Music is a great example. We have moved from records, to 8-track, to cassette,to CD, and now to MP3. It started off analog and progressively became moredigital, and with MP3, you have a completely digital manifestation of music:searching for great songs, sampling them, buying them, storing them, and listeningto them—all done digitally. Yet the MP3 player has more analog content than itspredecessors, and the record player had almost none.

The analog business is the second largest segment of the semiconductor businessand is arguably the most important. Analog chips are used in the widest variety ofapplications, and their performance—things such as signal-to-noise ratio (SNR),spurious free dynamic range (SFDR), and effective number of bits (ENOB)—canmake or break the performance of a system. The analog market is also quitefragmented, with hundreds of thousands of different parts used by hundreds ofthousands of customers in countless applications. It is a market that will continue toexpand and will continue to provide great opportunities for those of you who studyin this field.

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I was once asked by a non-technical friend to tell him the difference betweenanalog and digital. What he knew about digital was that it was made up of a bunchof 1s and 0s and that analog was all about “squiggly lines.” Well, that made methink about how to answer that question. What I came up with was this: In theworld, you care about two things: (1) Are you a 1 or a 0? and (2) How fast can youchange from a 1 to a 0? In the digital world, you care only about the destination,and what happens in between is irrelevant. In the analog world, you care about whathappens in the transition from being a 1 to a 0, or vice versa. You have to care,because what happens in that transition makes all the difference. You care as muchabout the journey as you do the destination—maybe even more so.

That makes analog both difficult and exciting.Badih El-Kareh and Lou Hutter have written a book about an important topic—

the world of analog design. They have simplified some of the circuit concepts tohelp clarify how to build great components that enable great analog chips. Andhopefully, this will inspire you to pursue a career in the field, so even greater analogcomponents can enable even more digital products that will continue to revolu-tionize the markets and create new markets for decades to come.

I hope you enjoy the analog world as much as I do.

Gregg LoweCEO, Freescale Semiconductor

viii Foreword

Preface

In recent years, the focus on analog integrated circuits has become more pro-nounced due to their ubiquitous use in electronic products. This has placed moreattention on analog process technologies. Whereas analog technology was once theexclusive domain of a small circle of integrated device manufacturers, it has pro-liferated to foundries worldwide and hence is available to all design houses. At theroot of analog technologies are components—transistors, resistors, capacitors,inductors, and varactors—that embody the performance requirements of the analogproducts.

This book was written for undergraduate electrical engineering students and forpracticing engineers in the field of analog, power, and RF silicon integrated tech-nologies. Its primary purpose is to provide a unified treatment of design, integra-tion, and applications of analog components fabricated on silicon. There are severalbooks available on semiconductor physics, but few if any that have focused on thecomponents and characteristics aimed at analog applications. The authors hope thatthis book constitutes a foundation, using device physics to help the reader get adeeper understanding of how the component functions and highlighting thosesalient attributes important for analog applications, with examples along the way toreinforce key concepts and best practices. Overviews of selected product applica-tions are presented, showing how these analog components are used, whileavoiding complex circuit analysis. At the end of each chapter, problems are pro-vided to test and stretch the reader’s understanding, and several references arelisted, allowing the reader to delve deeper into the topics discussed.

The level at which this book is written assumes that the reader has had intro-ductory physics, calculus, statistics, and an undergraduate college-level course onsemiconductor devices.

This book is based on years of experience by the authors in analog technology atboth integrated device manufacturers and foundries, and on industrial and academicteaching. This includes direct experience in defining analog component specifica-tions based on circuit performance and scaling requirements, integrating thosecomponents into an analog process technology, validating the reliability, and thenqualifying that technology for eventual production.

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This book is organized into eleven chapters and six appendices. Silicon isemphasized since this is the main material used in most analog, power, and RFtechnologies.

Chapter 1 is an introduction to the “world of analog.” It provides an overview,framing the importance of analog products in everyday life.

Chapters 2–4 give a review of silicon properties, pn junctions, and rectifying andohmic contacts, establishing the proper device physics background for the reader tomove into the more analog-oriented components. While several excellent books onthese topics have already been published, these chapters are intended to presentengineers and scientists, in a concise form, those parts of semiconductor and devicephysics that are most important to the discussion of analog components.

Chapter 5 covers fundamentals of bipolar junction transistors and junction field-effect transistors, which are constructed in a base CMOS technology with no orlittle added complexity. This chapter also provides an understanding of importantbipolar effects in CMOS, such as subthreshold current, snapback, and latch-up.

Chapter 6 deals with analog and RF CMOS components. This chapter includes aconcise discussion of the surface effects and the metal–oxide–silicon (MOS)structure that is a key part of the MOSFET and a powerful device and processcharacterization tool. Both digital and analog/RF CMOS device topics are thendiscussed. The modes of transistor operation and different transistor types arecovered. Transistor current–voltage characteristics are then detailed with anemphasis on analog applications.

High-voltage and power devices are presented in Chap. 7, focusing onDECMOS and LDMOS transistors. Concepts such as the drift region are covered,and key figures of merit such as specific on-resistance and gate charge are intro-duced, many of these areas leveraging concepts introduced in Chap. 6. High-voltage effects, such as quasi-saturation, impact ionization, self-heating, and safeoperating area, are detailed.

Chapter 8 describes passive components, which are fundamental components inanalog, mixed-signal, RF CMOS, and power applications. Device design andproperties of integrated precision resistors, capacitors, varactors, and inductors arecovered in detail, with examples of their use in circuit applications.

Chapter 9 discusses process integration of active and passive analog compo-nents. This includes analog CMOS, mixed-signal CMOS, RF CMOS, and BCDtechnologies. The description is illustrated with many cross sections, highlightingkey technology features, trade-offs, and best practices.

Component matching and noise are parameters that can have critical importancein analog applications. They are covered in detail in Chap. 10 for both active andpassive devices.

Chapter 11 covers component reliability. Basic concepts, models, and distribu-tions are introduced, highlighting their use for specific failure mechanisms andemphasizing analog reliability considerations. Practical examples are provided forillustration.

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http://dx.doi.org/10.1007/978-1-4939-2751-7_1http://dx.doi.org/10.1007/978-1-4939-2751-7_2http://dx.doi.org/10.1007/978-1-4939-2751-7_4http://dx.doi.org/10.1007/978-1-4939-2751-7_5http://dx.doi.org/10.1007/978-1-4939-2751-7_6http://dx.doi.org/10.1007/978-1-4939-2751-7_7http://dx.doi.org/10.1007/978-1-4939-2751-7_6http://dx.doi.org/10.1007/978-1-4939-2751-7_8http://dx.doi.org/10.1007/978-1-4939-2751-7_9http://dx.doi.org/10.1007/978-1-4939-2751-7_10http://dx.doi.org/10.1007/978-1-4939-2751-7_11

Acknowledgments

The authors acknowledge many individuals who helped make this book possibleand who improved it through their inputs, suggestions, patient review of chapters,and their critique. We could not have written this book without their help.

First and foremost, we acknowledge and thank Prof. Carlton Osburn, who tire-lessly and meticulously read each chapter and provided invaluable advicethroughout this endeavor. Jim Hellums patiently reviewed a number of topics acrossmultiple chapters, providing valuable feedback, as did John Pigott, Marie Denison,John Krick, and Il-Yong Park. We also acknowledge the following people who readand commented on several parts of the manuscript: Konrad Bach, Jonathan Brodsky,Steve Chaney, Wayne Chen, Sundar Chetlur, Claudio Contiero, Imelda Donnelly,Mark England, Randy Geiger, Sarma Gunturi, David Hannaman, Mark Harward,Alan Hastings, Alan Holden, Felicia James, Clif Jones, David Jones, Taek-Soo Kim,Lars Larsson, Mankoo Lee, Praful Madhani, Ken Maggio, Andrew Marshall, JoeMcPherson, Alessandra Merlini, Daniele Merlini, Bill Nehrer, Andrea Paleari,Sameer Pendharkar, Marcel Pelgrom, Angelo Pinto, Wolfgang Ploss, Sam Shichijo,Howard Test, Jim Victory, and Pieter Vorenkamp. Finally, we express our thanks tothe process development team at Dongbu HiTek for valuable discussions during thecourse of preparing the manuscript.

Badih El-KarehLou N. Hutter

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Contents

1 The World Is Analog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.2 What’s Different About Analog . . . . . . . . . . . . . . . . . . . . . . 3

1.2.1 Digital Design Considerations . . . . . . . . . . . . . . . . . 31.2.2 Analog Design Considerations . . . . . . . . . . . . . . . . . 51.2.3 Analog Technology and Manufacturing

Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81.3 Integration or Not . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121.4 Analog Process Technologies . . . . . . . . . . . . . . . . . . . . . . . . 14

1.4.1 Mixed-Signal CMOS Technology . . . . . . . . . . . . . . . 141.4.2 RF CMOS Technology . . . . . . . . . . . . . . . . . . . . . . 161.4.3 High-Speed BiCMOS . . . . . . . . . . . . . . . . . . . . . . . 161.4.4 Analog CMOS Technology . . . . . . . . . . . . . . . . . . . 171.4.5 Nonvolatile Memory . . . . . . . . . . . . . . . . . . . . . . . . 20

1.5 Analog Technology Roadmaps . . . . . . . . . . . . . . . . . . . . . . . 21References. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

2 Review of Single-Crystal Silicon Properties . . . . . . . . . . . . . . . . . 252.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252.2 Crystal Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252.3 Energy-Gap and Intrinsic Carrier Concentration . . . . . . . . . . . 27

2.3.1 Energy Band Model . . . . . . . . . . . . . . . . . . . . . . . . 282.3.2 The Boltzmann Distribution . . . . . . . . . . . . . . . . . . . 302.3.3 Fermi–Dirac Distribution and Density of States . . . . . 31

2.4 Doping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 342.4.1 Dopants from the Fifth Column—Donors . . . . . . . . . 342.4.2 Dopants from the Third Column—Acceptors . . . . . . . 352.4.3 Band Model for Impurities in Silicon . . . . . . . . . . . . 37

2.5 Carrier Transport . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 402.5.1 Carrier Transport by Drift—Low Field . . . . . . . . . . . 412.5.2 Carrier Transport by Drift—High Field . . . . . . . . . . . 48

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2.5.3 Carrier Transport by Diffusion . . . . . . . . . . . . . . . . . 502.5.4 Total Drift and Diffusion Current Density . . . . . . . . . 512.5.5 Non-uniform Doping Concentration . . . . . . . . . . . . . 522.5.6 Einstein Relation . . . . . . . . . . . . . . . . . . . . . . . . . . 53

2.6 Non-equilibrium Conditions . . . . . . . . . . . . . . . . . . . . . . . . 542.6.1 Carrier Lifetime . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Problems. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61References. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

3 PN Junctions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 653.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 653.2 Structure and Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

3.2.1 Cylindrical and Spherical Approximations . . . . . . . . . 693.3 Junction Characteristics at Thermal Equilibrium . . . . . . . . . . . 69

3.3.1 Step Junction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 703.4 Forward-Biased Junction . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

3.4.1 Effect of Series Resistances . . . . . . . . . . . . . . . . . . . 853.4.2 Effect of Surface Recombination. . . . . . . . . . . . . . . . 86

3.5 Reverse-Biased Junction . . . . . . . . . . . . . . . . . . . . . . . . . . . 883.5.1 Reverse Leakage Current . . . . . . . . . . . . . . . . . . . . . 903.5.2 Impact Ionization and Avalanche Breakdown . . . . . . . 933.5.3 Reverse Recovery Time. . . . . . . . . . . . . . . . . . . . . . 96

3.6 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 993.6.1 Zener Diode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 993.6.2 PIN Diode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103


4 Rectifying and Ohmic Contacts . . . . . . . . . . . . . . . . . . . . . . . . . . 1114.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1114.2 Rectifying Contacts, Schottky Barrier Diode. . . . . . . . . . . . . . 112

4.2.1 Metal–Semiconductor Barriers . . . . . . . . . . . . . . . . . 1124.2.2 Current–Voltage Characteristics . . . . . . . . . . . . . . . . 1174.2.3 Schottky Barrier Diode Applications . . . . . . . . . . . . . 131

4.3 Ohmic Contacts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1344.3.1 Specific Contact Resistivity . . . . . . . . . . . . . . . . . . . 135


5 Bipolar and Junction Field-Effect Transistors . . . . . . . . . . . . . . . 1475.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1475.2 Bipolar Junction Transistor, BJT. . . . . . . . . . . . . . . . . . . . . . 149

5.2.1 Idealized Structure . . . . . . . . . . . . . . . . . . . . . . . . . 1495.2.2 NPN Transistor in a CMOS Technology . . . . . . . . . . 157

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5.2.3 PNP Transistors in CMOS Technology . . . . . . . . . . . 1805.2.4 Frequency Response . . . . . . . . . . . . . . . . . . . . . . . . 1825.2.5 BJT Applications . . . . . . . . . . . . . . . . . . . . . . . . . . 185

5.3 Junction Field-Effect Transistor, JFET . . . . . . . . . . . . . . . . . . 1875.3.1 Idealized Normally On NJFET . . . . . . . . . . . . . . . . . 1875.3.2 JFET in a CMOS Technology . . . . . . . . . . . . . . . . . 1965.3.3 JFET Applications . . . . . . . . . . . . . . . . . . . . . . . . . 198


6 Analog/RF CMOS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2056.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2056.2 Review of MOS Properties . . . . . . . . . . . . . . . . . . . . . . . . . 206

6.2.1 Flatband Condition . . . . . . . . . . . . . . . . . . . . . . . . . 2066.2.2 Accumulation and Depletion . . . . . . . . . . . . . . . . . . 2116.2.3 Weak and Strong Inversion . . . . . . . . . . . . . . . . . . . 2126.2.4 MOS C-V Technique . . . . . . . . . . . . . . . . . . . . . . . 217

6.3 CMOS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2216.3.1 Review of MOSFETs, Long and Wide Channel . . . . . 2226.3.2 Analog Specific MOSFETs . . . . . . . . . . . . . . . . . . . 2446.3.3 Small-Size Effects. . . . . . . . . . . . . . . . . . . . . . . . . . 251

6.4 Analog Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2636.4.1 Differential Amplifier . . . . . . . . . . . . . . . . . . . . . . . 2646.4.2 Current Mirror . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2646.4.3 Native NMOS . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2656.4.4 Buried Channel MOSFET . . . . . . . . . . . . . . . . . . . . 2666.4.5 Depletion-Mode MOSFET . . . . . . . . . . . . . . . . . . . . 266


7 High-Voltage and Power Transistors . . . . . . . . . . . . . . . . . . . . . . 2757.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2757.2 The Drift Region . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2777.3 On-State Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277

7.3.1 On-Resistance, RDS(on). . . . . . . . . . . . . . . . . . . . . . . 2787.3.2 Specific On-Resistance, RSP . . . . . . . . . . . . . . . . . . . 279

7.4 Off-State Analysis. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2827.4.1 A Simple One-Dimensional Analysis of BVDSS . . . . . 2837.4.2 Reduced Surface Field, RESURF . . . . . . . . . . . . . . . 286

7.5 Trade-Offs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2927.5.1 Trade-Off Between RSP and BVDSS. . . . . . . . . . . . . . 2937.5.2 Switching Performance, RDS(on) × QG . . . . . . . . . . . . 294

7.6 Design and Characteristics of DEMOS . . . . . . . . . . . . . . . . . 2987.6.1 Complementary DEMOS . . . . . . . . . . . . . . . . . . . . . 298

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7.6.2 Field-Gap DENMOS. . . . . . . . . . . . . . . . . . . . . . . . 2997.6.3 Subthreshold Leakage Current . . . . . . . . . . . . . . . . . 3007.6.4 Asymmetric and Symmetric DEMOS . . . . . . . . . . . . 3007.6.5 Dielectric RESURF. . . . . . . . . . . . . . . . . . . . . . . . . 3017.6.6 Key Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . 3027.6.7 Specific on-Resistance Versus Breakdown Voltage . . . 303

7.7 Design and Characteristics of LDMOS . . . . . . . . . . . . . . . . . 3037.7.1 NLDMOS Configurations . . . . . . . . . . . . . . . . . . . . 3047.7.2 PLDMOS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3067.7.3 Laterally Graded Channel Effects . . . . . . . . . . . . . . . 3067.7.4 The Superjunction Concept . . . . . . . . . . . . . . . . . . . 3087.7.5 Key Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . 3107.7.6 SOI Devices. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3127.7.7 Trade-Off Between RSP and BVDSS. . . . . . . . . . . . . . 314

7.8 High-Voltage and High-Current Effects . . . . . . . . . . . . . . . . . 3157.8.1 Quasi-Saturation . . . . . . . . . . . . . . . . . . . . . . . . . . . 3157.8.2 Impact Ionization and Body Current . . . . . . . . . . . . . 3257.8.3 On-State Breakdown Voltage . . . . . . . . . . . . . . . . . . 3277.8.4 Self-heating and Temperature Effects . . . . . . . . . . . . 328

7.9 Safe Operating Area (SOA) . . . . . . . . . . . . . . . . . . . . . . . . . 3337.9.1 Electrical SOA . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3347.9.2 Electrothermal SOA . . . . . . . . . . . . . . . . . . . . . . . . 335

7.10 Circuit Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3367.10.1 Half H-Bridge Circuit . . . . . . . . . . . . . . . . . . . . . . . 3367.10.2 H-Bridge Motor Driver—LDMOS Reverse

Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3387.10.3 DC–DC Converter—Switching Effects . . . . . . . . . . . 3417.10.4 AC–DC Converter . . . . . . . . . . . . . . . . . . . . . . . . . 344


8 Passive Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3578.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3578.2 Resistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 357

8.2.1 Definition of Terms. . . . . . . . . . . . . . . . . . . . . . . . . 3598.2.2 Polysilicon Resistor. . . . . . . . . . . . . . . . . . . . . . . . . 3648.2.3 Silicon Resistors . . . . . . . . . . . . . . . . . . . . . . . . . . . 3758.2.4 Thin-Film Resistors, TFR . . . . . . . . . . . . . . . . . . . . 377

8.3 Capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3788.3.1 Definition of Terms. . . . . . . . . . . . . . . . . . . . . . . . . 3798.3.2 MOS Capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . 3848.3.3 Poly–Insulator–Poly Capacitor, PIP . . . . . . . . . . . . . . 3868.3.4 Metal–Insulator–Metal Capacitors . . . . . . . . . . . . . . . 386

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8.4 Varactors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3898.4.1 Definition of Terms. . . . . . . . . . . . . . . . . . . . . . . . . 3898.4.2 Junction Varactors . . . . . . . . . . . . . . . . . . . . . . . . . 3908.4.3 MOS Varactors. . . . . . . . . . . . . . . . . . . . . . . . . . . . 393

8.5 Planar Spiral Inductors . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3978.5.1 Definition of Terms. . . . . . . . . . . . . . . . . . . . . . . . . 397

8.6 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3998.6.1 Resistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3998.6.2 Capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4008.6.3 Inductors and Varactors . . . . . . . . . . . . . . . . . . . . . . 402


9 Process Integration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4119.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4119.2 Analog, Mixed-Signal, and RF Components . . . . . . . . . . . . . . 4149.3 Unit Processes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4149.4 Digital CMOS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 416

9.4.1 Isolation Module. . . . . . . . . . . . . . . . . . . . . . . . . . . 4179.4.2 Wells . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4199.4.3 Gate Stack Module . . . . . . . . . . . . . . . . . . . . . . . . . 4199.4.4 Source–Drain Module . . . . . . . . . . . . . . . . . . . . . . . 4209.4.5 BEOL Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . 421

9.5 MS and RF CMOS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4279.5.1 High-Voltage CMOS. . . . . . . . . . . . . . . . . . . . . . . . 4289.5.2 Low-Voltage Analog CMOS . . . . . . . . . . . . . . . . . . 4289.5.3 Isolated NMOS . . . . . . . . . . . . . . . . . . . . . . . . . . . 4299.5.4 Drain-Extended CMOS . . . . . . . . . . . . . . . . . . . . . . 4309.5.5 Bipolar Junction Transistors . . . . . . . . . . . . . . . . . . . 4319.5.6 Polysilicon and Silicon Resistors. . . . . . . . . . . . . . . . 4329.5.7 Lateral Flux Capacitor, LFC. . . . . . . . . . . . . . . . . . . 4339.5.8 Vertical MIM Capacitor in Aluminum BEOL . . . . . . . 4349.5.9 Vertical MIM Capacitor in Copper BEOL . . . . . . . . . 4359.5.10 Inductor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 437

9.6 Analog CMOS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4379.6.1 HV Analog CMOS Transistors . . . . . . . . . . . . . . . . . 4379.6.2 Native NMOS . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4389.6.3 Depletion-Mode NMOS. . . . . . . . . . . . . . . . . . . . . . 4389.6.4 Buried Channel PMOS . . . . . . . . . . . . . . . . . . . . . . 4399.6.5 Junction Field-Effect Transistor . . . . . . . . . . . . . . . . 4409.6.6 High Sheet Poly Resistor . . . . . . . . . . . . . . . . . . . . . 4409.6.7 Thin-Film Resistor . . . . . . . . . . . . . . . . . . . . . . . . . 4429.6.8 Poly–Insulator–Poly Capacitor . . . . . . . . . . . . . . . . . 4439.6.9 Buried (Subsurface) Zener Diode . . . . . . . . . . . . . . . 445

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9.7 Bipolar-CMOS-DMOS, BCD . . . . . . . . . . . . . . . . . . . . . . . . 4459.7.1 NLDMOS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4469.7.2 High-Frequency NLDMOS . . . . . . . . . . . . . . . . . . . 4489.7.3 Low-Complexity NLDMOS . . . . . . . . . . . . . . . . . . . 4499.7.4 Isolated-Drain NLDMOS . . . . . . . . . . . . . . . . . . . . . 4519.7.5 PLDMOS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 451


10 Mismatch and Noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45710.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45710.2 Mismatch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 457

10.2.1 Layout Configurations . . . . . . . . . . . . . . . . . . . . . . . 45910.2.2 Inverse Area Law . . . . . . . . . . . . . . . . . . . . . . . . . . 46110.2.3 MOSFET Mismatch . . . . . . . . . . . . . . . . . . . . . . . . 46210.2.4 Bipolar Transistor Mismatch . . . . . . . . . . . . . . . . . . 46910.2.5 Resistor Mismatch . . . . . . . . . . . . . . . . . . . . . . . . . 47110.2.6 Capacitor Mismatch . . . . . . . . . . . . . . . . . . . . . . . . 472

10.3 Noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47510.3.1 Classification of Noise. . . . . . . . . . . . . . . . . . . . . . . 47610.3.2 1/f Noise in CMOS. . . . . . . . . . . . . . . . . . . . . . . . . 48110.3.3 1/f Noise in Resistors . . . . . . . . . . . . . . . . . . . . . . . 48610.3.4 1/f Noise in Bipolar Junction Transistors, BJT . . . . . . 48810.3.5 1/f Noise in Junction Field-Effect Transistors, JFET. . . 489

10.4 Circuit Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49010.4.1 Mismatch in Current Mirrors . . . . . . . . . . . . . . . . . . 49010.4.2 Noise in Two-Stage Transconductance Amplifier . . . . 491


11 Chip Reliability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50311.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50311.2 Definition of Terms and Basic Reliability Concepts. . . . . . . . . 50411.3 Reliability Models. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 509

11.3.1 Exponential Distribution . . . . . . . . . . . . . . . . . . . . . 51011.3.2 Normal Distribution . . . . . . . . . . . . . . . . . . . . . . . . 51111.3.3 Lognormal Distribution . . . . . . . . . . . . . . . . . . . . . . 51311.3.4 Weibull Distribution . . . . . . . . . . . . . . . . . . . . . . . . 51611.3.5 Power Law Model . . . . . . . . . . . . . . . . . . . . . . . . . 519

11.4 Failure Mechanisms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52011.4.1 Dielectric Reliability . . . . . . . . . . . . . . . . . . . . . . . . 52011.4.2 Electromigration and Stress Migration . . . . . . . . . . . . 53211.4.3 Hot-Carrier Effects . . . . . . . . . . . . . . . . . . . . . . . . . 54111.4.4 Bias Temperature Instability . . . . . . . . . . . . . . . . . . . 549

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11.4.5 Joule Heating and Resistor Reliability . . . . . . . . . . . . 55111.4.6 Plasma Charging and Damage . . . . . . . . . . . . . . . . . 55311.4.7 Latch-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55711.4.8 High-Voltage MOSFET Reliability . . . . . . . . . . . . . . 56311.4.9 Electrostatic Discharge and Voltage Snapback . . . . . . 566


Appendix A: Universal Physical Constants . . . . . . . . . . . . . . . . . . . . . 583

Appendix B: Properties of Silicon and GermaniumCrystals (300 K) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 585

Appendix C: Properties of SiO2 and Si3N4 (300 K) . . . . . . . . . . . . . . . 589

Appendix D: International System of Units . . . . . . . . . . . . . . . . . . . . . 591

Appendix E: The Greek Alphabet . . . . . . . . . . . . . . . . . . . . . . . . . . . 593

Appendix F: Conversion Factors . . . . . . . . . . . . . . . . . . . . . . . . . . . . 595

Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 597

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Abbreviations and Acronyms

ADC Analog-to-digital converterAF Accelerating factorALD Atomic layer depositionAR Antenna ratioAR Aspect ratio, ratio of depth to width of openingBCD Bipolar-CMOS-DMOSBC PMOS Buried channel PMOSBEOL Back-end of the lineBGR Bandgap referenceBiCMOS Bipolar CMOSBJT Bipolar junction transistorBody MOSFET region where the channel is formedBOX Buried oxide (SOI)BPSG Borophosphosilicate glassBTI Bias temperature instabilityBulk MOSFET region under which the channel is formedCDF Cumulative distribution functionCLM Channel-length modulationCM Current mirrorCMP Chemical mechanical polishingCNL Charge neutrality levelCPU Central processing unitCSOA Commutating SOACT Computed tomographyCVD Chemical vapor depositionDA Dielectric absorption (capacitor)DAC Digital-to-analog converterDebiasing Typically, IR drop in the opposite polarity of the built-in voltageDECMOS Drain-extended CMOSDENMOS Drain-extended NMOSDEPMOS Drain-extended PMOS

xxi

DIBL Drain-induced barrier loweringDMOS Double-diffused MOSDNW Deep N-wellDSP Digital signal processorDTI Deep-trench isolationEFR Early failure rateEHP Electron–hole pairEM ElectromigrationEOT Equivalent oxide thicknessESD Electrostatic dischargeF Cumulative failures (in %)FBSOA Forward-bias safe operating areaFEOL Front end of the lineField gap Thick oxide in drift region under gate, DEMOS, LDMOSFIT Failure in timeFN Fowler–NordheimFOM Figure of meritFSG Fluorinated silicate glassGap-fill Filling the gap between lines or in openings with, e.g., oxideGGNMOS Grounded-gate NMOSGIDL Gate-induced drain leakageGOI Gate oxide integrityHCI Hot-carrier injectionHDP High-density plasmaHigh-K High dielectric constantHRS High-resistance substrateHS High side (LDMOS)HS High speedHSR High sheet resistance resistorHTGS High-temperature gate stressHTRB High-temperature reverse-bias stressHV High voltageHVCMOS High-voltage CMOSIC Integrated circuitIDM Integrated device manufacturerIEC International Electrotechnical CommitteeIF Intermediate frequencyIFR Intrinsic failure rateIH Holding currentIMD Intermetal dielectricIoT Internet of ThingsIPD Interpoly dielectricITRS International Technology Roadmap for SemiconductorsJFET Junction field-effect transistor

xxii Abbreviations and Acronyms

LAA Length of active areaLc Critical length, Blech effectLDD Lightly doped drainLDMOS Lateral double-diffused MOSLED Light-emitting diodeLER Line-edge roughnessLFC Lateral flux capacitorLNA Low-noise amplifierLO Local oscillatorLOCOS Local oxidation of silicon (isolation)Low-K Low dielectric constantLPCVD Low-pressure CVDLS Low side (LDMOS)LSR Low sheet resistanceLV Low voltageLVCMOS Low-voltage CMOSMESFET Metal–semiconductor FETMIGS Metal-induced gap statesMIM Metal–insulator–metal (capacitor)MS Mixed signalMSR Medium sheet resistanceMTF Median time to failureMTTF Mean time to failureNBL N-buried layerNBTI Negative bias temperature instabilityNCE Narrow-channel effectN-JFET n-channel junction field-effect transistorNLDMOS n-channel LDMOSNMOS n-channel MOSFETNO Nitrided oxideNVM Nonvolatile memoryOED Oxidation-enhanced diffusionONO Oxide–nitride–oxideOp-amp Operational amplifierOTA Operational transconductance amplifierPA Power amplifierPBL P-buried layerPBTI Positive bias temperature instabilityPDK Process delivery kitPECVD Plasma-enhanced chemical vapor depositionPEN Plasma-enhanced nitride depositionPETEOS Plasma-enhanced TEOS depositionPIN P–intrinsic–N (diode)PIP Polysilicon–insulator–polysilicon (capacitor)PJFET p-channel junction field-effect transistor

Abbreviations and Acronyms xxiii

PLDMOS p-channel LDMOSPMD Poly (ore pre) metal dielectricPMIC Power management ICPMOS p-channel MOSFETPNO Plasma nitrided oxidePOCl3 PhosphooxychloridePoE Power over EthernetPSD Power spectral densityPSG Phosphosilicate glassPVD Physical vapor depositionPWM Pulse-width modulationQ Quality factorQBD Charge to breakdownRBSOA Reverse-bias safe operating areaRESURF Reduced surface fieldRF Radio frequencyRFID Radio frequency identificationRIE Reactive-ion etchingRNCE Reverse narrow-channel effectRSCE Reverse short-channel effectRTA Rapid thermal annealRTN Random telegraph noiseRTS Random telegraph (signal) noiseSAR Successive approximation registerSBD Schottky barrier diodeSCE Short-channel effectSCR Silicon-controlled rectifierSiGe Silicon–germaniumSiGe:C Silicon–germanium–carbonSILC Stress-induced leakage currentSJ SuperjunctionSM Stress migrationSOA Safe operating areaSoC System on a chipSOI Silicon-on-insulator (oxide)SOS Silicon on sapphireSPC Statistical process controlSPICE Simulation program with integrated circuit emphasisSRAM Static random access memorySRF Self-resonance frequencySRH Shockley–Read–Hall (generation–recombination)STI Shallow-trench isolationTCC Temperature coefficient of capacitanceTCE Temperature coefficient of expansionTCP Temperature compensation point

xxiv Abbreviations and Acronyms

TCR Temperature coefficient of resistanceTDDB Time-dependent dielectric breakdownTED Transient-enhanced diffusionTEOS Tetraethylorthosilicate (oxide)TFR Thin-film resistorTLP Transmission line pulseVCC Voltage coefficient of capacitanceVCO Voltage-controlled oscillatorVCR Voltage coefficient of resistanceVDMOS Vertical double-diffused MOSVDP van der PauwVH Holding voltageWLR Wafer-level reliability

Abbreviations and Acronyms xxv

Symbols

a JFET metallurgical channel width (cm)a Lattice constant (cm)a Critical field parameter (−)A Geometry-dependent factor (−)A Area (cm2)A Richardson constant (A/cm2 K2)A Tunneling parameter (−)A* Effective Richardson constant (A/cm2 K2)AE Emitter area (cm

2)AC Cross-sectional area (cm

2)AP Process-related parameter mismatch factor (−)AID Drain current mismatch factor (%-μm)

1

AVT Threshold voltage mismatch factor2 (mV-μm)2

AG Gate area (cm2)

AS Surface area (cm2)

AV Intrinsic voltage gain (=gmr0)b Mobility ratio (μn/μp)b Critical field parameter (−)B, B* Tunneling parameters (−)BIB Base current mismatch factor (%-μm)

3

BIC Collector current mismatch factor (%-μm)4

BV Breakdown voltage (V)BVCBO Collector–base breakdown voltage, emitter open (V)BVCBS Collector–base breakdown voltage, emitter–base shorted (V)BVCEO Collector–emitter breakdown voltage, base open (V)

1If ΔID in % and channel area in μm2.

2If ΔID in % and channel area in μm2.

3If ΔIB in % and channel area in μm2.

4If ΔIC in % and channel area in μm2.

xxvii

BVDGO Drain-gate breakdown voltage, source open (V)BVDGS Drain-gate breakdown voltage, source-gate shorted (V)BVDSS Drain-source breakdown voltage, source-gate-body shorted (V)BVEBO Emitter-base breakdown voltage, collector open (V)BVEBS Emitter-base breakdown voltage, collector–base shorted (V)C Capacitance per unit area (F/cm2)c Velocity of light (2.998 × 1010 cm/s)Cb Barrier capacitance per unit area—SBD (F/cm

2)CD Diffusion capacitance per unit area (F/cm

2)CDS Drain-to-source capacitance (F)CDB Drain-to-body capacitance (F)Cdecap Decoupling capacitance (F)Cdeep Deep deletion capacitance per unit area, CV plot (F/cm

2)CDF Cumulative distribution function (−)CG Total gate capacitance per unit area (F/cm

2)CGD Gate-to-drain capacitance per unit area (F/cm

2)CGG Total gate capacitance (F)CGch Gate-to-channel capacitance per unit area (F)CGD Gate-to-drain capacitance (F)CGS Gate-to-source capacitance (F)CHF High-frequency capacitance per unit area, CV plot (F/cm

2)Ci Intrinsic capacitance, varactor (F)CILD Interlevel dielectric capacitance (F)Cinv Silicon inversion capacitance per unit area, CV plot (F/cm

2)Cj Junction capacitance per unit area (F/cm

2)CjC Collector–base junction capacitance (F)CjE Emitter–base junction capacitance (F)CL Load capacitance (F)CLF Low-frequency capacitance per unit area, CV plot (F/cm

2)CLL Line-to-line capacitance (fF/μm)Cmax Maximum capacitance per unit area, CV plot (F/cm

2)Cmin Minimum capacitance per unit area, CV plot (F/cm

2)CNW N-well to substrate capacitance (fF)Cox Oxide capacitance per unit area, CV plot (F/cm

2)Cpar Parasitic capacitance (F)CPMD Premetal dielectric capacitance (F)Cpoly Polysilicon, e.g., depletion capacitance per unit area, (F/cm

2)CS Storage node capacitance (F)CSi Silicon capacitance per unit area, CV plot (F/cm

2)CSidep Silicon depletion capacitance per unit area, CV plot (F/cm

2)CSiFB Silicon capacitance at flatband per unit area, CV plot (F/cm

2)CSimin Silicon minimum capacitance per unit area, CV plot (F/cm

2)CSTI Shallow-trench capacitance per unit area (F/cm

2)d Distance (cm)D Diffusion constant (cm2/s)

xxviii Symbols

D Duty cycle [=ton/(ton + toff)] (−)~D Effective diffusion constant (cm

2/s)Dn Electron diffusion constant (cm

2/s)Dp Hole diffusion constant (cm

2/s)E Energy (eV)E Electric field (V/cm)e Tensile strain (Pa)e Electron charge (1.6 × 10−19 C)EA Activation energy (eV)EBD Field to breakdown (−)Ec Critical field (V/cm)EC Bottom of conduction band energy level (eV)ED Donor energy level (eV)EF Fermi level (eV)EFm Metal Fermi level (eV)EFn Electron quasi-Fermi level (eV)EFp Hole quasi-Fermi level (eV)Eg Energy gap (eV)Ei Intrinsic silicon energy level (eV)Ei Ionization energy (eV)Ei(A) Acceptor ionization energy (eV)Ei(D) Donor ionization energy (eV)En Nitride field Qn ≈ 0 (V/cm)Eox Oxide field (V/cm)EOO Characteristic tunneling energy (eV)EP Phonon energy (eV)Epeak Peak electric field (V/cm)Es Surface field (V/cm)Esat Field at onset of saturation velocity (V/cm)ESi Field in silicon (V/cm)ET Trap energy level (eV)EV Top of valence band energy level (eV)Ex Field in silicon normal to surface (V/cm)Ey Surface field parallel to silicon surface (V/cm)F Force (N)f Frequency (Hz)fc Corner frequency (Hz)f(E) Fermi function (−)FIT Failure in time number of fails in 109 device-hours (−)fT Gain–bandwidth product, cutoff frequency (Hz)F(t) Failure probability function (−)fmax Maximum frequency of operation (Hz)G Power gain (−)G Bulk generation rate (cm−3 s−1)

Symbols xxix

g Acceleration of earth (m/s2)gC Collector conductance (S)gD Channel (drain) conductance (S)gD-lin Linear channel (drain) conductance (S)gD-sat Saturated channel (drain) conductance (S)gm Transconductance (S)gm-lin Linear transconductance (S)gm-sat Saturated transconductance (S)GR Generation–recombinationG0 Lumped JFET parameter (Eq. 6.9)H Heat conduction (W)I Current (A)IB Base current (A)IB Body current (A)IBC Base–collector current (A)IBE Base–emitter current (A)IC Collector current (A)ICBO Collector–base current, emitter open (A)ICEO Collector–emitter current, base open (A)ICsat Collector saturation current (A)ID Drain current (A)IDiff Diffusion current (A)IDlin Linear drain current (A)IDsat Saturated drain current (A)ID0 Constant drain current per channel square at threshold (A)IDS Drain-to-source current, (A)IE Emitter current (A)IEBO Emitter–base current, collector open (A)IEsat Emitter saturation current (A)IF, If Forward-bias current (A)IG, IGG Total gate current (A)Igen Generation current (A)Igen-bulk Bulk generation current (A)Igen-surf Surface generation current (A)IH Holding current, latch-up (A)Ileak Total leakage current (A)In Electron current (A)in Current noise (A)i2n Current noise power (A

2)

INW Current in n-well (A)Ioff MOSFET off-current (A)Ion MOSFET on-current (A)Ip Hole current (A)IPT Punch-through current (A)

xxx Symbols

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IPT0 Current at onset of punch-through (A)IPW Current in p-well (A)IR,Ir Reverse current (A)IS Source current (A)IS Saturation current (A)Is Surface generation–recombination current (A)IsB Base saturation current (A)IsC Collector saturation current (A)Isub Substrate current (A)I0 Drain current at VG = VT (A)j Current density (A/cm2)jdirect Direct tunneling current density (A/cm

2)jF Forward current density (A/cm

2)jFN Fowler–Nordheim tunneling current density (A/cm

2)jG Gate current density (A/cm

2)jDC Average DC current density, conductors (A/cm

2)jn Electron current density (A/cm

2)jn(dif) Electron diffusion current density (A/cm

2)jn-drift Electron drift current density (A/cm

2)jp Hole current density (A/cm

2)jpeak Absolute maximum current density, conductors (A/cm

2)jp(dif) Hole diffusion current density (A/cm

2)jp-drift Hole drift current density (A/cm

2)jR Reverse current density (A/cm

2)jrms Root-mean-square current density, conductors (A/cm

2)js Saturation current density (A/cm

2)jT Total current density (A/cm

2)jT Tunneling current density (A/cm

2)K Dielectric constant = ε/ε0 (−)K Defined parameter in ID equation (CMOS)k Boltzmann constant ≈ 8.618 × 10−5 eV/KKF Process, bias-dependent parameter in SPICE noise model (−)kT Thermal energy (=0.0258 eV at 300 K)kT/q Thermal voltage (= 0.0258 V at 300 K)L Length (cm)L Inductance (H)Lc Contact length (μm)LD Debye length (cm)LD Drawn length (cm)Ldrift Length of drift region, DEMOS, LDMOS (μm)LE Emitter length (μm)LE Electrical length, e.g., resistor (cm)Le Extrinsic Debye length (cm)Leff Effective channel length (μm)leff Effective mean-free path (cm)

Symbols xxxi

LI Impact-ionization mean-free path (cm)Li Intrinsic Debye length (cm)Lmet Metallurgical channel length (μm)Ln Electron diffusion length (cm)LnB Electron diffusion length in base (cm)Lp Hole diffusion length (cm)LpE Hole diffusion length in emitter (cm)Lpoly Polysilicon line-width, channel length (μm)Lr Optical phonon mean-free path (cm)LT Contact transfer length (cm)M Multiplication factor (−)m Mean of logarithm of times to fail (−)mD Density of states, effective mass (Kg)m0 Electron mass (≈9.1 × 10

−31 Kg)m�n Electron effective mass (Kg)mox Oxide electron effective mass (kg)m�p Hole effective mass (kg)MTF Median time to failure (h)MTTF Mean time to failure (h)N Number of electrons per unit area (cm−2)n Electron concentration (cm−3)�n Thermal equilibrium electron concentration (cm−3)n Number of squares (−)n Ideality factor (−)n Index of refraction (−)n Power law exponent (−)NA Acceptor concentration (cm

−3)N�A Ionized acceptor concentration (cm

−3)NA0 Acceptor concentration at x = 0 (cm

−3)NA(x) Acceptor concentration as function of depth (cm

−3)NB Background dopant concentration (cm

−3)NB Concentration of lightly doped region (cm

−3)�nb Equilibrium electron concentration in bulk (cm

−3)NC Effective density of states at conduction band edge (cm

−3)ND Donor concentration (cm

−3)NþD Ionized donor concentration (cm

−3)ND(x) Donor concentration as function of depth (cm

−3)ND0 Donor concentration at x = 0 (cm

−3)Nf Number of fixed oxide charges per unit area (=Qf/q cm

−2)NI Number of mobile ions per unit area (cm

−2)ni Intrinsic carrier density (cm

−3)ni0 Intrinsic carrier density without energy gap lowering (cm

−3)Ninv Number of inversion electrons per unit area (cm

−2)Nit Number interface traps per unit area (cm

−2)

xxxii Symbols

NM Noise margin (−)NMH High noise margin (−)NML Low noise margin (−)nn Majority electron concentration in n-region (cm

−3)�nn Thermal equilibrium electron concentration in n-region (cm

−3)nn0 Electron concentration in n-region at x = 0 (cm

−3)np Minority electron concentration in p-region (cm

−3)�np Thermal equilibrium electron concentration in p-region (cm

−3)np0 Electron concentration in p-region at x = 0 (cm

−3)Nref Fitting parameter (−)ns Surface electron concentration (cm

−3)ns0 Surface electron concentration at flatband (cm

−3)nS0 Surface electron concentration at source boundary (cm

−3)Ns Number of secondary carrier pairs (−)nsL Surface electron concentration at drain (cm

−3)nso Surface electron concentration at source (cm

−3)Nsub Substrate doping concentration (cm

−3)Nt Density of generation–recombination centers (cm

−3)Nteff Effective density of generation–recombination centers (cm

−3)NV Effective density of states at valence band edge (cm

−3)N0 Fixed diffusion source concentration (cm

−3)n0 Electron concentration at x = 0 (cm

−3)P Parameter (−)P Perimeter (cm)P Power (W)P Probability (−)p Hole concentration (cm−3)p Momentum (N s)�pb Equilibrium hole concentration in bulk (cm

−3)pb Bulk hole concentration (cm

−3)pdf, f(t) Probability density function (−)Pj Junction perimeter (cm)pn Concentration of minority holes in n-region (cm

−3)�pn Thermal equilibrium hole concentration in n-region (cm

−3)pn0 Hole concentration in n-region at x = 0 (cm

−3)�pn0 Equilibrium minority hole concentration at x = 0 (cm

−3)pp Concentration of majority holes in p-region (cm

−3)�pp Thermal equilibrium hole concentration in p-region (cm

−3)�pp0 Equilibrium majority hole concentration at x = 0 (cm

−3)pp0 Majority hole concentration in p-region at x = 0 (cm

−3)ps Surface hole concentration (cm

−3)PSD Power spectral density (A2/Hz or V2/Hz)Ptop Top RESURF p-region (−)

Symbols xxxiii

Q Charge per unit area (C/cm2)Q Quality factor (−)q Electron charge (≈1.6 × 10−19 C)QB Minority carrier charge in base (C)Qb Bulk depletion charge per unit area, CMOS (C/cm

2)Qbmax Maximum bulk depletion charge per unit area (C/cm

2)QBD Charge to fail (C)Qb-deep Bulk charge in deep depletion per unit area (C/cm

2)Qeff Effective dielectric charge per unit area (C/cm

2)Qf Oxide fixed charge per unit area (C/cm

2)Qit Silicon oxide interface trap charge per unit area (C/cm

2)Qm Charge induced at gate-oxide interface per unit area (C/cm

2)Qm Mobile charge per unit area (C/cm

2)Qmax Maximum quality factor (−)Qn Surface electron charge per unit area (C/cm

2)Qot Oxide trap charge per unit area (C/cm

2)Qp Surface hole charge per unit area (C/cm

2)Qpeak Peak charge, e.g., pn-junction depletion (C/cm

2)QS Stored charge per unit area (C/cm

2)Qs Surface charge per unit area (C/cm

2)QT Total charge (C/cm

2)R Resistance (Ω)r Radius of curvature (cm)r Correlation coefficient (−)r Fraction (−)rA Auger recombination rate (cm

6/s)ri Medium rank, Benard’s rule (−)Racc Resistance of accumulated region, DEMOS, DMOS (Ω)rAn Electron Auger recombination rate (cm

6/s)rAp Hole Auger recombination rate (cm

6/s)RB Base resistance (Ω)RBext Extrinsic base resistance (Ω)RBint Intrinsic base resistance (Ω)RB0 Base resistance without applied bias (Ω)RC Time delay (s)RC Collector resistance (Ω)Rc Contact resistance (Ω)Rch Channel resistance (Ω)RD Drain resistance (Ω)Rdrift Resistance of drift region, DEMOS, DMOS (Ω)RDS(on) Drain-to-source resistance for VG = VGmax, VD = 0.1 V (Ω)RE Emitter resistance (Ω)rE Emitter dynamic resistance (=kT/qIC, Ω)Redge Leading-edge resistance of source or drain (Ω-μm)Rext Extrinsic resistance (Ω)

xxxiv Symbols

Rext-S Source extrinsic resistance (Ω)Rext-D Drain extrinsic resistance (Ω)RG Gate resistance (Ω)RKS Resistance from point K to source, DEMOS, DMOS, (Ω)RL Load resistance (Ω)RLDD Resistance of lightly doped drain region (Ω)RM Metal resistance (Ω)Rn Resistance equivalent of noise (Ω)RNBL n-buried layer resistance (Ω)RNW N-well resistance (−)r0 Output resistance (−)Rp Projected range (cm)RPBL p-buried layer resistance (Ω)Rpinch Intrinsic base (pinched) resistance (Ω)Rprobe Test probe resistance (Ω)RPW P-well resistance (−)RR Ramp rate (V/s)RS Source resistance (Ω)RS Sheet resistance (Ω/Square)RS Sum of all resistances (Ω)RSD Source–drain resistance (Ω)RS-drift Sheet resistance of drift region, DEMOS, DMOS (Ω/Square)RSi Silicon resistance (Ω)RS0 Sheet resistance at T = T0 (Ω/Square)RSp Spreading resistance (Ω)RSP Specific on-resistance (=RDS(on) · Area, mΩ-mm

2)R(t) Reliability function (−)Rth Thermal resistance (K/W)Rwire Wiring resistance (Ω)r0 Output wiring resistance (Ω)S Subthreshold swing (V/decade)S Cross-sectional area (cm2)s Space (μm)s Standard deviation of logarithm of times to fail (−)s, s0 Surface recombination velocity (cm/s)SI Current noise power spectral density (A

2/Hz)SV Voltage noise power spectral density (V

2/Hz)SVG Input (gate) referenced PSD (V

2/Hz)t Time (s)t Thickness (nm)ti Insulator thickness (nm)T Temperature (K)tBD Time to breakdown (s, m)Tamb Ambient temperature (K)TCC Temperature coefficient of capacitance (ppm, %)

Symbols xxxv

TCR Temperature coefficient of resistance (ppm, %)T0 Reference temperature (K)tdrift Thickness of drift region, DEMOS, LDMOS (μm)teq Equivalent oxide thickness (cm)tm Metal thickness (μm)Tn Temperature equivalent of noise (K)tn Nitride thickness (cm)tox Oxide thickness (cm)tox-phys Physical oxide thickness (cm)tpoly Polysilicon thickness (cm)tS Storage time (s)tSi Path length in silicon (cm)tsilicide Silicide thickness (cm)tSTI Shallow-trench isolation thickness (cm)t50 Median time to fail (hr)U Generation–recombination rate (cm−3 s−1)Us Surface generation rate (cm

−3 s−1)v Velocity (cm/s)VA Early voltage (V)Va,Vapp Applied voltage (V)VB, VBS Body-to-source voltage (V)Vb Barrier height (V)Vbi Built-in voltage (V)VBC Collector–base voltage (V)VBE Base–emitter voltage (V)VCBO Collector–emitter voltage, emitter open (V)VCBS Collector–emitter voltage, emitter shorted to base (V)VCC Power supply voltage, bipolar transistor (V)VCE Collector–emitter voltage (V)VCEO Collector–emitter voltage, base open (V)VCEsat Collector saturation voltage (V)Vch Channel-to-source voltage, FET (V)VCC Voltage coefficient of capacitance (ppm/V)VCR Voltage coefficient of resistance (ppm/V)VD,VDS Drain-to-source voltage (−)VDK Drain-to-point K voltage, DEMOS, LDMOS (V)vd Drift velocity (cm/s)VDA Measured dielectric absorption (V)VDD Power supply voltage, MOSFET (V)VDG Drain-to-gate voltage, (V)VDS Drain-to-source voltage, (V)VDsat Saturation drain voltage, MOSFET (V)vdy Drift velocity along surface in y-direction (cm/s)VEBS Emitter–base voltage, collector shorted to base (V)VF Forward voltage (V)

xxxvi Symbols

VFB Flatband voltage (V)VG, VGS Gate-to-source voltage (V)VGmax Maximum allowed gate voltage, (V)VH Holding voltage, latch-up (V)VH High voltage (V)VIN Input voltage, latch-up (V)Vj Junction voltage (V)VjG Junction-to-gate voltage, gated diode (V)VKS Voltage between point K and source in DEMOS, DMOS (V)vn Electron velocity (cm/s)vn Voltage noise (V)v2n Voltage noise power (V

2)

VOUT Output voltage (V)Vop Operating voltage (V)Vox Voltage across oxide (V)VP Pinch-off voltage (V)vp Hole velocity (cm/s)VPT Punch-through voltage (V)VR Reverse voltage (V)VSS Typically ground potential, MOSFET (0 V)vsat, vs Saturation velocity (cm/s)vs-bulk Saturation velocity in bulk silicon (cm/s)vs-inv Saturation velocity in inversion layer (cm/s)VT Threshold voltage (V)VT-drain Threshold voltage at drain (V)vth Thermal velocity (≈10

7 cm/s at 300 K)VT-source Threshold voltage at source (V)Vt1, It1 Trigger voltage, current (snapback) (V, A)Vt2, It2 Voltage, current at second breakdown, snapback (V, A)v0 Initial velocity (cm/s)W, w Width (μm)Wb Neutral base width (cm)Wc Contact width (cm)WD Drawn width (cm)Wdrift Width of drift region, DEMOS, DMOS (μm)WE Emitter width (μm)WE Electrical width (μm)Weff Effective width (μm)Wm Metal width (μm)Wn Width of neutral n-region (μm)Wp Width of neutral p-region (μm)WTotal Sum of all on-chip MOSFET width (cm)WVia Via width (μm)

Symbols xxxvii

X Depth normal to the silicon surface (μm)xch Channel depth below the surface, thickness (nm)xd Depletion width (μm)xdD Depletion width at MOSFET drain (μm)xd-deep Depletion depth in deep depletion (μm)xd-field Depletion width under field oxide (μm)xd-inv Steady-state depletion depth in inversion (μm)xd-lat Lateral junction depletion width at surface (μm)xdmax Maximum depletion depth below surface (μm)xdn Depletion width in n-side of pn junction (μm)xdp Depletion width in p-side of pn junction (μm)xd-poly Depletion depth in poly gate (nm)xdS Depletion width at MOSFET source (μm)xds,xdsurf Junction depletion width at surface intercept (cm)xi Depth below surface where n = p = ni (μm)xinv Depth of inversion peak below surface (μm)xJ Junction depth (nm)xJbn Junction depth of buried n-layer (μm)xJbp Junction depth of buried p-channel (μm)xjC Collector–base junction depth (μm)xJE Emitter–base junction depth (μm)xjlat,xjl Lateral extent of junction at surface (cm)xm Depth of potential peak, image-force barrier lowering (nm)y Direction from source to drain (−)ydn Depletion width in n-side of junction, y-direction (μm)α Grounded base current gain (=IC/IE)αn, αp NPN, PNP grounded base current gainα Linear expansion coefficient (%/oC)α Temperature coefficient of resistance (K−1)α Fitting parameter (−)αAl Linear expansion coefficient of aluminum (%/

oC)α1 Linear coefficient (−)α2 Quadratic coefficient (−)αF Forward grounded base current gain (=IC/IE)αi Impact ionization rate (cm

−1)αR Reverse grounded base current gain (=IC/IE)αT Base transport factor (−)αT Pretunneling factor (−)β Grounded-emitter current gain (=IC/IB)β =μeff Cox·W/L (MOSFET)β Fitting parameter (−)β Defined parameter in ID equation (CMOS)β Frenkel–Poole emission coefficient (cm1/2 V1/2)β Weibull shape parameter (−)βF Forward grounded emitter current gain (=IC/IB)

xxxviii Symbols

βR Reverse grounded emitter current gain (=IC/IB)βR Ratio of NMOS β to PMOS βγ Injection efficiency (−)γ Field acceleration factor (−)γn Electron injection efficiency, NPN γn = In/(In + Ip) (−)γp Hole injection efficiency, PNP γp = Ip/(In + Ip) (−)δ Thickness of interface barrier gap (cm)δL Length of pinch-off region (μm)ΔE Energy difference (eV)ΔEC Change (offset) in minimum conduction band edge (eV)ΔEg Change in energy bandgap (eV)Δf Bandwidth (Hz)ΔIB Increment in base current (A)ΔIC Increment in collector current (A)ΔIE Increment in emitter current (A)ΔL Change in channel length (cm)Δn Change in electron concentration (cm−3)Δnp0 Change in minority electron concentration at x = 0 (cm

−3)Δns Change in surface electron concentration (cm

−3)Δp Change in hole concentration (cm−3)Δpn0 Change in minority hole concentration at x = 0 (cm

−3)Δps Change in surface hole concentration (cm

−3)ΔQG Increment in gate charge (C)ΔVBE Increment in emitter–base forward voltage (V)ΔVG Increment in gate voltage (V)ΔVR Increment in reverse voltage (V)ΔVT Change in threshold voltage (V)ΔW Change in channel width (cm)ΔϕΒ Barrier lowering (eV)ε0 Permittivity of free space (≈8.86 × 10

−14 F/cm)εox Oxide dielectric constant (≈3.9)εn Nitride dielectric constant (≈7.0)εSi Silicon dielectric constant (≈11.7)η Multiplier of inversion layer charge to calculate field (−)η Power efficiency (=power-out/power-in) (−)η Weibull scale parameter (−)θ Aperture (−)θ Mobility degradation factor (V−1)κ Same as K = ε/ε0 (−)κ Thermal conductivity(W/cm-K)λ Wavelength (cm)λ Channel length modulation factor = −1/VA, (V

−1)λ Mean-free path (nm)λ Tunneling attenuation length (nm)λ De Broglie wavelength (nm)

Symbols xxxix

λ0 Wavelength in vacuum (μm)λ(t) Failure rate (−)μ Mobility (cm2/V s)μeff Effective mobility (cm

2/V s)μh High mobility, normal to crystallographic axis (cm

2/V s)μI Ionized impurity scattering limited mobility (cm

2/V s)μl Lattice scattering limited mobility (cm

2/V s)μln Electron lattice mobility (cm

2/V s)μlp Hole lattice mobility (cm

2/V s)μmax Fitting parameter (cm

2/V s)μmin Fitting parameter (cm

2/V s)μn Electron mobility (cm

2/V s)~ln Effective electron mobility (cm

2/V s)μp Hole mobility (cm

2/V s)~lp Effective hole mobility (cm

2/V s)μ0 Surface mobility at VG = VT (cm

2/V s)μΔP Mean of mismatch of parameter P (−)ρ Resistivity (Ω-cm)ρ Volume charge concentration (C/cm3)ρC Specific contact resistance (Ω-cm

2)ρ0 Resistivity at T = T0 (Ω-cm)σ Conductivity (Ω−1-cm−1 or S/cm)σ Charge sheet (C/cm2)σ Capture cross section (cm2)σ Standard deviation (−)σΔP Standard deviation of mismatch in parameter P (−)σ2 Variance (−)r2DP Variance in mismatch in parameter P (−)τ Lifetime (s)τ Mean time between collisions (s)τ Time constant (s)τA Auger lifetime (s)τAn Auger electron lifetime (s)τAp Auger hole lifetime (s)τB Base transit time (s)τC Collector transit time (s)τE Emitter transit time (s)τn Electron transit time, lifetime (s)τnB Electron transit time, lifetime in base (s)τp Hole transit time, lifetime (s)τpE Hole transit time, lifetime in emitter (s)τSRH Shockley–Read–Hall recombination lifetime (s)τ0 Assumed same lifetime for electrons and holes (s)ϕ Potential (V)

xl Symbols

ϕ Dose (cm−2)ϕI Pulsed-shaped implant dose (cm

−2)ϕB, ϕBeff Barrier height, effective barrier height (V)ϕb Bulk Fermi potential (V)ϕbn Bulk electron Fermi potential (V)ϕbp Bulk hole Fermi potential (V)ϕFn Electron quasi-Fermi potential (V)ϕFp Hole quasi-Fermi potential (V)ϕHCI Minimum energy for hot-carrier injection (eV)ϕi Minimum energy for impact ionization (eV)ϕm Metal (gate) work function (V)ϕms Work function difference between metal (gate) and Si (V)ϕm-app Apparent metal (gate) work function (V)ϕn Electron Fermi potential (V)ϕp Hole Fermi potential (V)ϕs Surface Fermi potential (V)ϕSi Silicon work function (V)ϕ0 Surface neutrality level (V)χ Electron affinity (V)χ Stress (Pa)χSi Silicon electron affinity (V)χox Silicon dioxide electron affinity (V)ψ Band bending, potential (V)ψs Surface potential (V)ψsmax Maximum surface potential (V)ψs-field Surface potential under field oxide (V)ω Angular frequency (s−1)

Symbols xli

ForewordPrefaceAcknowledgmentsContentsAbbreviations and AcronymsSymbols

Silicon Analog Components978-1-4939-2751... · 2017. 8. 26. · Badih El-Kareh PIYE Cedar Park, TX...

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Transcript of Silicon Analog Components978-1-4939-2751... · 2017. 8. 26. · Badih El-Kareh PIYE Cedar Park, TX...