Si TECHNOLOGY ROADMAP FOR UBIQUITOUS COMPUTING,

SENSING, AND PERCEPTION

Dr Dennis BussTexas Instruments Inc

buss@ti.com

Si TECHNOLOGY ROADMAP FOR UBIQUITOUS

COMPUTINGAGENDA

►Moore’s Law Scaling• Design for Low Power• SOC Integration of Analog/RF

Functions• Digital Radio Processor• Integrated MEMS• Conclusion

Modern CMOS10 um

1 um

100 nm

10 nm

1 nm1970 1980 1990 2000 2010 2020

37 Years of Scaling History

Every generationFeature size shrinks by 70%Transistor density doublesWafer cost increases by 20%Chip cost comes down by 40%

Semi-Conductor Scaling

90 nm in 2004

Generations occur regularly

On average every 2.9 years over the past 35 yearsRecently every 2 years

65 nm in 2006

Presumed Limitto Scaling

Deep UV Litho

Beginning ofSubmicron CMOS

150X increase in die per wafer

Nano-meter

1994

500nm

6"

80.7

310

1997

350nm

8"

46.6

950

1999

250nm

8"

19.2

2550

2000

180nm

8"

10.7

4700

2002

130nm

12"

6.7

12,200

2004

90nm

12"

4.2

18,700

2006

65nm

12"

2.4

26,500

Dies per wafer

Wafer size

Die size (mm2)

Year 2008

45nm

12"

1.4

46,500

GSM Digital Baseband Evolution

Typical 65 nm Product: DBB chipTypical 65 nm Product: DBB chip

Features:• Die Size: 13.3mm2

• 5.9M bits SRAM• 1.9M gates of logic

eFuse (dieID) and repair ARM7 uC LEAD3 DSP (250K gates) MegaCell (300K gates) ASIC gates (1.3M gates)

• Volume Production

Lithography

Year of Production

Resolution (µm)

3

21.5

1

0.4 0.350.25

0.180.13

0.090.065

0.045

0.50.6

0.01

0.1

1

10

1980 1990 2000 2010

AboveWavelength

NearWavelength

BelowWavelength

g-line λ = 436nm

i-line λ = 365nm

DUV λ = 248nm 193

λ = 193nm

0.032

EUVλ = 13.5nm

i-193 λ‘ = 133nm

Design Data

• Vertical poly gates only• GHOST Poly• Poly not required to overlap

contact• Max Xstor width change within

ACTIVE

Silicon

STRUCTURED LAYOUT (45 nm)

Si Technology RoadmapIssues/Trends

• Design for Manufacturing Variations• Analog/RF & MEMS SOC Integration• Co-Development of Process, Design

Techniques and Architecture• CMOS processes customized to the

application• Relentless focus on power reduction.

Si TECHNOLOGY ROADMAP FOR UBIQUITOUS

COMPUTINGAGENDA

• Moore’s Law Scaling►Design for Low Power• SOC Integration of Analog/RF

Functions• Digital Radio Processor• Integrated MEMS• Conclusion

Memory Iddq vs. Power Management

1

10

100

1000

10000

180nm 130nm 90nm 65nm 45nm

Without PMWith PM

Idd

q

norm

.

0

100

200

300

400

500

600

700

1993 1995 1997 1999 2001 2003 2005 2007

MCU

MHz Phone Performance Requirement

Productavailable

Technology Node

Technology: memory Iddq

1

10

100

1000

10000

180nm 130nm 90nm 65nm 45nm

Idd

q

norm

.

Without PM

Talk Time: Pwr_Active = CV 2F + Leakage- C: Decrease/node,offset by

complexity - F: Increases/node- Leakage: Increases/node, temp.

Standby Time: Pwr_Idle = Leakage

- Leakage: Increases/node, temp

Deep Submicron Processes Demand Enhanced Power Management

Power Domain Partitioning

• Main Power Domains• DSP• Data Memory• Modem Logic

• Others• Power Mngmt

Control• MCU• DPLL• Analog• IO

Approaches to Power Reduction

SRAMSRAM PERIPERI

VNW VDD

VSS VSUB

LOGICLOGIC

VNW VDD

VSS VSUB

VDD for IO = 1.8V

VDD Core: ~1.0V in retention

VSS (0V)

retretz

ret ret

LDO

(0.5V)

SRAM

Flip FlopsFlip FlopsVNW VDD

VSS VSUBAlways OnAlways On

VNW VDD

VSS VSUBSRAMSRAM ARRAYARRAY

VNW VDD

VSS VSUB

LOGIC

Silicon Measurements

Si TECHNOLOGY ROADMAP FOR UBIQUITOUS

COMPUTINGAGENDA

• Moore’s Law Scaling• Design for Low Power►SOC Integration of Analog/RF

Functions• Digital Radio Processor• Integrated MEMS• Conclusion

Why Single-Chip Phone?• "Integration is like gravity”

– Already happened in hard-disk drives, ADSL, etc

– Not a single example of reversal

• “$20 phones”• Large untapped market in

India and China• More “real estate” space for

advanced features• Better reliability

– Today, more than half of the total components on a board are analog RF components

• Longer talk time

Typical Cell-Phone Block Diagram

DSM DigitalFLASH EEPROMAnalog

CMOS

SiGe BICMOS High voltageDiscrete

Passives (SAW Filters, etc.)

RadioCODE

C

Digital Baseband

Logic

Memory

UserInterfac

e

LNA

PA

RXSynt

hTX

Passives

Power Management

Aud

ioD

isp

lay

Area and cost must be reduced integrate !

High-power (typically GaAs)

What about SiP Integration?• Monolithic integration of DRAM would result in

significant cost increase due to the need for additional mask levels.

• Memory modules are highly reusable so modularity makes sense.

• No yield impact issue due to in-package integration of memory.

Si TECHNOLOGY ROADMAP FOR UBIQUITOUS

COMPUTINGAGENDA

• Moore’s Law Scaling• Design for Low Power• SOC Integration of Analog/RF

Functions►Digital Radio Processor• Integrated MEMS• Conclusion

Conventional Transceivers• RF transmitters in commercial wireless applications are

traditionally based on charge-pump PLL’s and IQ upconversion mixers

• RF receivers use continuous-time mixing, filtering and amplification

• Design flow and circuit techniques are analog intensive• Technology incompatible with modern digital

processors– Low-voltage deep-submicron CMOS

900

LPF

AD

AD

I

Q

LO

PADigital Baseband

LPF

LNA 900

LPF

DA

DA

Digital Baseband

I

Q

LO

LPF

DRP RF Architecture

LNTA

RF Out

RF In

DCO

Amplitude Regulation

LO clock

TX

DigitalLogic

RX

RX data

TX data

Channel

Current

sampler

Dig

ital B

aseb

and

an

dA

pp

lica

tion

P

roce

sso

r

Power Management (PM)

RF Built-in Self Test (RFBIST)

TX/RXCombin

erDPA

TDC

A/D Discrete

time

DigitalLogic

Σ∆

0.2, 1.25, 2.5,5,10, 15, 20MHz BW

450, 800, 900, 1800, 1900, 2100,2500, 3400MHz Transmission bands

GMSK, QPSK,8-PSK, 16QAM,64QAM Modulation

TDMA, FDMA, CDMA, OFDMA,IFDMA schemes

Looks like SDR!!

DRP/SoC Proven in Many Products

1/2 the board area

1/2 the power

1/2 the silicon

BlueLink™Bluetooth

NaviLink™A-GPS

WiLink™Wi-Fi

Hollywood™mDTV

“LoCosto”GSM/GPRS

More to come…

Single-Chip GSM Radio

DPA

Digital logic

DCO

Discretetime

Digital logic

Front-endModule

LNA

TX

RX

A/D

Current sampler

Dig

ital B

aseb

and

Pro

cess

or

AM

Σ∆

Power Management RF Built-in Self Test

SR

AM

DCXO Σ∆

XO

• 90 nm CMOS• All-digital PLL• All-digital TX• Digitally-

intensive RX• w/o

– 2-W PA– Battery

management

VBAT

Battery Management

New Paradigm

In a deep-submicron CMOS process, time-domain resolution of a digital signal edge transition is superior to voltage resolution of an analog signal

All-Digital PLL vs. Charge-pump PLL

• Charge-pump PLL:

• Suffers from reference spurs

• Tradeoff: bandwidth against spur level

FREF

TDC

Loop Filter

DCO

CKVΣ

FCW

Phase error

Variable phase

Reference phase

Tune

(fR) (fV)

PFD

÷N

Phase/Frequency Detector VCO

Tuning voltage

Frequency Divider

UP

DOWN

Charge Pump

Loop FilterFREF

(fR) (fV)

Σ∆

• All-digital PLL:• True phase

domain operation

• Exploits time resolution of TDC and DCO

Deep-Submicron CMOS Rules• Exploit:

– Fast switching characteristics of MOS transistors– Small device geometries and precise device

matching– High density of digital logic: 250 kgates/mm2 in 90-

nm CMOS– High density of SRAM memory: 1 Mbits / mm2 in 90-

nm CMOS• Avoid:

– Biasing currents for analog circuits– Reliance on voltage resolution– Nonstandard devices not needed for memory and

digital logic

90nm

DRP™

90nm

SoC Drives Cost Reduction• SoC Integration Includes:

– Digital baseband– SRAM– Power management– Analog– RF– Processors & Software

• Most advanced process technology used to maximize integration while minimizing cost

– 90nm (shipping) – 65nm (mature design) – 45nm and beyond (preliminary)

• The DRP technology enables digital implementation of traditional analog RF functions in standard CMOS

65nm65nm

45nm

Digital Radios Offer Many BenefitsWhy Digital?

Process Capability

We can now clock systems at radio frequencies

Digital technology takes advantage of advanced logic capability (and leverages the wafer process technology investment)

Entitlement

Digital systems scale with lithography and are easy to migrate

Node Migration

Performance improves with new technology, the job keeps getting easier

Performance

Digital radios offer excellent performance, low power consumption, high manufacturing yield, and low cost

Cost

Si TECHNOLOGY ROADMAP FOR UBIQUITOUS

COMPUTINGAGENDA

• Moore’s Law Scaling• Design for Low Power• SOC Integration of Analog/RF

Functions• Digital Radio Processor►Integrated MEMS• Conclusion

MEMS Integration

• MEMS Integration will also enable products for ubiquitous computing, sensing and perception– accelerometers– pressure sensors– rate gyros– integrated microphones– resonators– RF switches and tuneable capacitors– optical switches and phase modulators, – micro-fluidic pumps and valves – displays

• The Digital Mirror Device (DMD) is an example of integrated MEMS

How the DMD Works

0

How the DMD Works

0

How the DMD Works

0

How the DMD Works

0

How the DMD Works

0

MEMS Integration

Today•HDTV•Front Projection Products•Large Screen Movie Theaters

Tomorrow•Projection displays for cell phones and PDAs•3D imaging for medical

Si TECHNOLOGY ROADMAP FOR UBIQUITOUS

COMPUTINGAGENDA

• Moore’s Law Scaling• Design for Low Power• SOC Integration of Analog Functions• Digital Radio Processor• Integrated MEMS►Conclusion

Technology in the Next Decade

Moore’s Law is predicted to stagnate toward the end of the next decade …

Technology in the Next Decade

… but SOC Integration has the potential to continue IC cost reduction and to perpetuate growth of products for ubiquitous computing, perception & sensing.

Moore’s Law is predicted to stagnate toward the end of the next decade …

Systems on Si

2015

Syste

m F

un

cti

on

ality

Moo

re’s Law

Sca

ling

System-on-SiSystem-on-SiIntegrationIntegration