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Fast Electrical Correction Using Resizing and Buffering

Shrirang Karandikar, Charles J Alpert, Mehmet Yildiz, Paul Villarrubia, Steve

Quay, Tuhin Mahmud

C. J. Alpert ASP-DAC 2007 Tutorial: Physical Synthesis 2

Constructive versus Polishing

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Example Large ASIC

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What is Physical Synthesis?

Placement

Buffering

Repowering

Scan ChainsCloning

Routing

Timing Analysis

Legalization

Re-synthesis

PhysicalSynthesis

Combines multiple separate steps into one to Combines multiple separate steps into one to perform timing (design) closureperform timing (design) closure

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Big Challenges in Physical Synthesis

Designs are enormous 4 to 8 million objects nowMust be fast

Interconnect resistance increasingDensity / white space management Buffer explosionMultiple cycles to cross chip

Support for full design closureNoise, power, routability, yield

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Global Interconnect Dominance

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Building Blocks of Physical Synthesis

Placement(find non-overlapping locations

to minimize wirelength)

Electrical Correction(buffer and repower to

fix slew and cap constraints)

Timing Analysis(identify critical logic)

Legalization(place those buffers

and logic in legal locations)

Critical Path Opts(incremental synthesis to optimize

most critical regions)

Compression(Optimize rest of critical regions)

Area Recovery(reduce area without hurting timing)

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Example Physical Synthesis Flow

Placement

Electrical Correction

Legalization

Timing Analysis

Critical Path Opts

Compression

Timing Analysis

Net Weighting

Recovery

Detailed Placement

Electrical Correction

Critical Path Opts

Compression

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Slew violationsSize down sinkResize sourceBuffer net

Capacitance violationsFanout violations

Electrical Correction Necessary to Time Design

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Slew Model

( , ) ( , ) ln 9w i j i js v v ElmoreDelay v v= ⋅

2 2,( ) ( ) ( , )j b out i w i js v s v s v v= +

Upstream Downstream

S(vj)Sb,out(vi) Slew degradation on wire: Sw(vi,vj)

vi vj

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Get the Design Into Good Shape

Pick aggressive target slewBuffer / repower to meet targetPower down non-critical gatesPower up critical onesChoice of slew target has large impact on final area and timing

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Basic Approach to Electrical Correction

Process gates right to leftIf net has no violations, size source gate down

saves areareduce load on inputs

If net has violations, size gate upIf violations still exist, buffer the netLinear time algorithm

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EVE in Action

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Legalization

Electrical correction just repowered and performed massive buffering. How do you legalize?No bin modelBin-based modelIncremental legalization

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No Bin Model

Place every cell, buffer at ideal (x,y) coordinateLike having one giant binPermits “pile-ups”Let legalization handle it afterwardsAdvantage: faster for optimizationDisadvantage: things move far away

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Bin Model

Divide region into binsEach cell assigned to binIf inserting into bin, check areaFull bins prevent repowering /bufferingCould try finding adjacent bin with free spaceAdvantage: less likely that legalization will move things far awayDisadvantage: may prevent fixing violations

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Puzzle Fit Problem

FitsDoesn’t Fit

new cell

Two bins with same set of cells and same total area

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Puzzle Fit Example

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A Closer Look

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Buffering for Electrical Correction

Van Ginneken: prune on three variablesDelay/slackCapacitancePower/Area

What if you removed delayObtain minimum area solution such that slew constraints are satisfiedOrder of magnitude faster than Van GinnekenLinear “length based” in case of 1 buffer

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Chuck’s “Buffer Tree Philosophy”

Buffers completely inhibit routingMillions of buffer trees needed, so build them fastRequired for speed, simultaneous stuff too time consuming and not necessarily any betterClean up messes afterward

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Environmentally Friendly “Green” Buffering

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Congestion Mitigation High-level Illustration

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Plate Example

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Dual Plate Example

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Congestion Reduction Example

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Final Thoughts

On the surface, electrical correction simpleRight to leftFirst try repoweringThen buffering

Flow decisions affect solution qualityWhich legalization strategyHow tight a slew constraintSaving area versus getting design in good shape