Shift-Registers and Push Button Debounce Switching and Logic Lab Standard Laboratory Exercises.
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Transcript of Shift-Registers and Push Button Debounce Switching and Logic Lab Standard Laboratory Exercises.
Shift-Registers and Push Button Debounce
Switching and Logic LabStandard Laboratory
Exercises
Suggestions and Warnings Read for detail and comprehension Should be able to complete within
normal laboratory period. Make sure you program unused
pins as tri-state inputs or you may burnout EPM7128S device on PLDT-2.
Shift Registers Riding without training wheels Riding with training wheels Project 1 -- Basic Component
Shift Register as Behavioral VHDL Follow standard steps from project creation
to exercise of device Project 2 – Push Button Debounce
Count and display debounced presses Count and display non debounced presses Never let inputs float!
Shift Register Entity
ENTITY ShftRgstr ISPORT (
Dp : IN BIT_VECTOR(7 DOWNTO 0);Ld,Ds, CLK : IN BIT;Q : BUFFER BIT_VECTOR(7 DOWNTO 0));
END ShftRgstr;
Dp[7..0]
Ld
Ds
CLK
Q[7..0]
Shf tRgstr
Tx
Shift Register ArchitectureARCHITECTURE Behavioral OF ShftRgstr ISBEGINPROCESSBEGINWAIT UNTIL Clk'event AND Clk = '1';IF Ld = '1' THEN --parallel loadQ <= Dp;
Shift Register ArchitectureELSE --shift right LSb first
Q(0) <= Q(1); --Serial Data Out
Q(1) <= Q(2); --Continue ShiftQ(2) <= Q(3);Q(3) <= Q(4);Q(4) <= Q(5);Q(5) <= Q(6);Q(6) <= Q(7);Q(7) <= Ds; --Serial Data In
END IF;END PROCESS;END Behavioral;
Vector Waveform Format File
Overwrite
Clock
Arbitrary
Value
Waveform
EditingTool
Add Push Button Jumper Wires
Bounce on Release
Cross-Coupled NAND gates Requires
Two I/O pins Two resistors Double pole
switch Output changes
on first contact closure
Project 2 – Non Debounce Parallel In from DIP Switches and
Debounced Switches Serial Out
5 VDC
pb_in(Active-LOW)
nPb_in(Active-HIGH)
Pb_out(Active-HIGH)
Project 2 -- Debounce
4MHz 1KHz
pb_in(Active-LOW)
nPb_in(Active-HIGH)
Pb_out(Active-HIGH)
Debouncer Shift Register
LoadPB_INCLK
!=
nPb_in = Pb_out Parallel LoadnPb_in != Pb_out Shift
nPb_in
Pb_out
Bounce on Press
LoadPB_INCLK
!=nPb_in
Pb_out
nPB_in
Pb_out
Load
SR4
0…0 0 0 1 0 1 0 1 1 1 1 1 1 1 1…10…0 0 0 0 0 0 0 0 0 0 1 1 1 1 1…11…1 1 1 0 1 0 1 0 0 0 1 1 1 1 1…10…0 0 0 1 0 1 0 1 3 7 F F F F F…F
Bounce on Release
LoadPB_INCLK
!=nPb_in
Pb_out
nPB_in
Pb_out
Load
SR4
1…1 1 1 0 1 0 1 0 0 0 0 0 0 0 0…01…1 1 1 1 1 1 1 1 1 1 0 0 0 0 0…01…1 1 1 0 1 0 1 0 0 0 1 1 1 1 1…1F…F F F E F E F E C 8 0 0 0 0 0…0
8 Steps to Success
1. Create Project2. Capture Logic3. Analysis and Synthesis4. Pin Assignments5. Full Compile6. Timing Simulation7. Programming8. Exercise circuit
Unused Pins as Tri-State Inputs Select
“Assignments” Select “Device” Select “Device & Pin
Options” Select “Unused Pins”
Tab Select “As inputs, tri-
stated” OK