Sherief Reda Division of Engineering, Brown University...
Transcript of Sherief Reda Division of Engineering, Brown University...
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Physical Design of Digital Integrated Circuits(EN0291 S40)
Sherief RedaDivision of Engineering, Brown University
Fall 2006
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• Static timing analysis• STA for sequential circuits • Delay modeling: devices and interconnects• Statistical static timing analysis
Lecture 04: Timing Analysis
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Propagation delay definition
Logic block
time
voltagea y
propagation delay50%
Vmax(10)%
10% 90%
transitiontime
Definitions:
• rise/fall propagation delay
• rise/fall transition delay (slew (slope): ΔV/transition delay)
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Problem: Given a circuit, find the path(s) with the largest delay (critical paths)
• Solution: run SPICE and report the results of the simulation
• Problem: SPICE is computationally expensive to run except for small-size circuits
• WANTED: We need a fast method that produces relatively accurate timing results compared to SPICE
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Static timing analysis
1/2
2/4 3/5
1/22/4
2/3
1/2
I1I2I3I4
I5I6
O1
O2
C17 from ISCAS’85 benchmarks
All inputs are arrive at time 0
Assuming all interconnects have 0 delay
Each gate has rise/fall delay
1/2
2/4
1/2
7/7
6/4
9/10
9/11 In reality, each input pin has its own rise/fall delay and wires have delays
simplifiedanalysis
slack = arrival time – required arrival time⇒ paths with negative slacks need to be eliminated!
criticalpath
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Finding the critical path through breadth first search
• Initialize queue Q to empty• for all vertices i in V: nvisit[i]=0; • Add all primary input vertices to queue Q• While (Q ≠ 0)
– i = top of Q; remove i from Q; computer delay of i– for every edge (i, j):
• nvisit[j]++;• if(nvisit[j] == fanin[j]) add j to Q
2/1
4/21/1
3/24/3
3/2
2/2
I1I2
I3I4
I5
I6
O1
O2
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STA can lead to false critical paths
2×1MUX
delay = 5
delay = 3
delay = 5
delay = 3
2×1MUX
outa
b
0
1 1
0
• What is critical path delay according to STA?• Is this path realizable?
No, actual delay is less than estimated by STA
STA assumes a signal would propagate from a gate input to its output regardless of the values of other inputs
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• Static timing analysis• STA for sequential circuits • Delay modeling: devices and interconnects• Statistical static timing analysis
Lecture 04: Timing Analysis
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Timing analysis of sequential circuits
combinational circuit
input outputcycle time P
setuptime Ts
holdtime Th
[dmin .. dmax]
FF
clock
Δ
FF
clock
Δ
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Timing analysis of sequential circuits under presence of clock skew
combinational circuit
input output
[dmin .. dmax]
FFj
clock
Δ
FFi
clock
Δ
T=0
si
sj
cycle time P
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Sometimes introducing skew can be helpful
FFi FFjFFkdmax=8ns
dmax=10ns
si sj
Zero clock skew (si =0 & sj = 0) ⇒ clock period = 10ns, fmax = 100MHz
Si = -1 sj = 0 ⇒ clock period = 9ns, fmax = 111MHz (no timing violations)
Si = -2 sj = 0 ⇒ clock period = 8ns, fmax = 125MHz (no timing violations)
Introducing skew also helps minimize the simultaneous switching of FFs → less load on the P/G network
STA is relatively easy once we figure out how to calculate gate and interconnect delay
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• Static timing analysis• STA for sequential circuits • Delay modeling: devices and interconnects• Statistical static timing analysis
Lecture 04: Timing Analysis
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Elmore delay model: An upper bound to actual delay in RC trees
R1 R2 R3 RN
C1 C2 C3 CN
Sum the result of multiplying each resistance by the capacitance down stream from it
any tree structure
step input
[see Gupta/Pileggi’97 for more info]
What is the runtime complexity?
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Switch-level device RC delay models
PMOS modelNMOS model
[source: Weste/Harris]
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Modeling the delay of an inverter
Holes have half the mobility of electrons → PMOS width = 2× of the NMOS device to get the same current
(or resistance) during output rise→ equal rise and fall delays for CMOS inverter
loading affects gate delay
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Gate delay: rise delay
6C
2C2
2
224hC
B
Ax
Y
h copies
R
(6+4h)CY ( )6 4pdrt h RC= +
AB
Y
Assumption: interconnect delay is ignored (for the moment)
step input
rise propagation delay
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Gate delay: fall delay
h copies
fall delay is worse than rise delay in this case
AB
Y6C
2C2
2
224hC
B
Ax
Ystep input
(1)
( ) ( ) ( ) ( )( )
2 2 22 6 4
7 4
R R Rpdft C h C
h RC
= + + +⎡ ⎤⎣ ⎦= +
(6+4h)C2CR/2
R/2x Yfall propagation delay
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Gate delay is input pattern dependant
h copies
AB
Y6C
2C2
2
224hC
B
Ax
Ystep input
(1)
fall propagation delay
⇒ Connect the latest arriving signal closest to the output node whenever feasible
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Impact of transition time on gate delay
gateInput Output
Δ
Δ’
time
time
τi
In addition to capacitive load, input transition time affects • delay: τi > 0 → Δ’ > Δ• output transition time:
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Why does transition time affect delay?
During transition, gate current < saturation current→ higher effective output resistance → larger delay∴ Input transition time affects gate delay (and output transition time too!)
GateΔr/f(C, τi)
total capacitance(intrinsic + loading + interconnects)
tiτi
Ti+Δr/fτostored in a lookup
table for fast calculation
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Interconnect delay: the lumped case
0V
Vm Vout
Upper bound on delays in RC trees [Pileggi’97]
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Interconnect delay: lumped vs. distributed
R1 R2 R3 RN
C1 C2 C3 CN
lumped overestimates
delay
r = resistance per unit length
c = capacitance per unit length
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Carryout STA after annotating your circuit with gate/interconnect delays
• Annotate your circuit with gate/interconnect delay, and carry out STA
• Don’t ignore interconnect delay because it is currently responsible for ~80% of total path delays!
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• Static timing analysis• STA for sequential circuits • Delay modeling: devices and interconnects• Statistical static timing analysis
Lecture 04: Timing Analysis
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In Statistical STA (SSTA), delay is no longer deterministic
I1I2
I3I4
I5I6
O1
O2pd
f
delay
delay
delay?
Replace deterministic gate delay by a random delay variable thathas a normal pdf
What is the pdf of z = max(x, y), where x and y are two random normal variables?
z is not normal, but can be approximated reasonable using random variables [Jacobs/Berkelaar’00]
x
y
z
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Gate variations impact critical path(s) delay leading to an increase in the average delay
• Intra-chip (within-die) variations: arises within devices in the same die
• Inter-chip (die-to-die) variations: arises between different chips
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Assignments for next lecture
Reading assignments:• Statistical Timing Analysis for Intra-Die Process Variations with
Spatial Correlations, ICCAD'03 (Kundan + (Yiwen) (judge))• Incremental timing analysis, US Patent 5508937 (Cesare)• Industrial products:
– Cadence SignalStorm (Elif) – Synopsys PrimeTime (Brendan)
Projects overview:• 10-15 mins presentation on previous work + proposal
• 1½ → 2 page report