SHARC Processor Hardware Reference Manual

ADSP-214xx SHARC Processor Hardware ReferenceIncludes ADSP-2146x, ADSP-2147x, ADSP-2148x

Revision 1.0, February 2012 Part Number 82-000469-01

Analog Devices, Inc. One Technology Way Norwood, Mass. 02062-9106

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Copyright Information 2012 Analog Devices, Inc., ALL RIGHTS RESERVED. This document may not be reproduced in any form without prior, express written consent from Analog Devices, Inc. Printed in the USA.

DisclaimerAnalog Devices, Inc. reserves the right to change this product without prior notice. Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use; nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under the patent rights of Analog Devices, Inc.

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CONTENTS

CONTENTS PREFACEPurpose of This Manual .................................................................lxxi Intended Audience .........................................................................lxxi Manual Contents ......................................................................... lxxii Whats New in This Manual ......................................................... lxxv Technical or Customer Support ................................................... lxxvi Registration for MyAnalog.com ............................................ lxxvii EngineerZone ....................................................................... lxxvii Supported Processors ................................................................. lxxviii Product Information ................................................................. lxxviii Analog Devices Web Site ..................................................... lxxviii VisualDSP++ Online Documentation .................................... lxxix Technical Library CD ............................................................ lxxix Notation Conventions .................................................................. lxxx

INTRODUCTIONDesign Advantages ........................................................................ 1-1 SHARC Family Product Offerings ........................................... 1-2

ADSP-214xx SHARC Processor Hardware Reference

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Contents

Processor Architectural Overview .................................................. 1-2 Processor Core ........................................................................ 1-2 I/O Peripherals ....................................................................... 1-2 I/O Processor ..................................................................... 1-3 Digital Audio Interface (DAI) ............................................. 1-3 DAI System Interrupt Controller ........................................ 1-3 Signal Routing Unit ............................................................ 1-4 Digital Peripheral Interface (DPI) ....................................... 1-4 DPI System Interrupt Controller ......................................... 1-4 Signal Routing Unit 2 ......................................................... 1-4 Differences from Previous Processors ............................................. 1-4 I/O Architecture Enhancements .............................................. 1-5 Development Tools ....................................................................... 1-6

INTERRUPT CONTROLFeatures ........................................................................................ 2-1 Clocking ...................................................................................... 2-2 Register Overview ......................................................................... 2-2 Functional Description ................................................................. 2-3 Programmable Interrupt Priority Control ................................ 2-3 Peripheral Interrupt ............................................................ 2-5 Software Interrupt .............................................................. 2-5 Peripherals with Multiple Interrupt Request Signals ............. 2-5 System Interrupt Controller .................................................... 2-6 DAI/DPI Interrupt Sources ................................................. 2-7

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Contents

DAI Interrupt Latch Priority Option ................................... 2-8 DPI Interrupt Latch ............................................................ 2-9 DAI/DPI Interrupt Mask for Waveforms ............................. 2-9 DAI/DPI Interrupt Mask for Events .................................. 2-10 DAI/DPI Interrupt Service ................................................ 2-10 Interrupt Service ................................................................... 2-11 Core Buffer Service Request (I/O mode) ............................ 2-12 DMA Access ..................................................................... 2-12 Interrupt Latency .................................................................. 2-12 DMA Completion Types ................................................... 2-14 Debug Features ........................................................................... 2-15 Shadow Interrupt Register ..................................................... 2-15

I/O PROCESSORFeatures ........................................................................................ 3-2 Register Overview ......................................................................... 3-3 DMA Channel Registers .......................................................... 3-4 DMA Channel Allocation ................................................... 3-4 Standard DMA Parameter Registers ..................................... 3-4 Extended DMA Parameter Registers .................................... 3-8 Data Buffers ..................................................................... 3-10 Chain Pointer Registers ..................................................... 3-12 TCB Storage ............................................................................... 3-15 Serial Port TCB ..................................................................... 3-15 SPI TCB ............................................................................... 3-15


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Contents

UART TCB .......................................................................... 3-16 Link Port TCB ...................................................................... 3-16 FIR Accelerator TCB ............................................................ 3-17 IIR Accelerator TCB ............................................................. 3-18 FFT Accelerator TCB ............................................................ 3-19 External Port TCB ................................................................ 3-20 Clocking .................................................................................... 3-22 Functional Description ............................................................... 3-23 Automated Data Transfer ...................................................... 3-23 DMA Transfer Types ............................................................. 3-23 DMA Direction .................................................................... 3-25 Internal to External Memory ............................................. 3-25 Peripheral to Internal Memory .......................................... 3-25 Peripheral to External Memory (SPORTs) ......................... 3-26 Internal Memory to Internal Memory ............................... 3-26 DMA Controller Addressing .................................................. 3-26 Internal Index Register Addressing .................................... 3-27 External Index Register Addressing .................................... 3-29 DMA Channel Status ............................................................ 3-29 DMA Bus Architecture .......................................................... 3-30 Standard DMA Start and Stop Conditions ............................. 3-31 Operating Modes ........................................................................ 3-31 Chained DMA ...................................................................... 3-31 TCB Memory Storage ....................................................... 3-32

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Chain Assignment ............................................................. 3-33 Starting Chain Loading ..................................................... 3-34 Buffered Chain Loading Register ....................................... 3-35 TCB Chain Loading Priority ............................................. 3-35 Chain Insert Mode (SPORTs Only) ................................... 3-36 Peripheral DMA Arbitration .................................................. 3-36 Peripheral Group Stage 1 Arbitration ................................. 3-36 Peripheral DMA Bus Stage 2 Arbitration ........................... 3-38 External Port DMA Arbitration ......................................... 3-38 External Port Group Stage 1 Arbitration ............................ 3-41 SPORT/External Port Group Stage 2 Arbitration ............... 3-42 External Port DMA Bus Stage 3 Arbitration ....................... 3-42 Fixed Versus Rotating Priority ........................................... 3-44 Peripheral and External Port DMA Block Conflicts ............ 3-44 Interrupts ................................................................................... 3-44 Sources .................................................................................. 3-45 DMA Complete ................................................................ 3-45 Internal Transfer Completion ........................................ 3-45 Access Completion ........................................................ 3-46 Chained DMA Interrupts .................................................. 3-46 Masking ................................................................................ 3-47 Service .................................................................................. 3-47 Interrupt Versus Channel Priorities ........................................ 3-47 Effect Latency ............................................................................. 3-48


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Write Effect Latency ............................................................. 3-48 IOP Effect Latency ............................................................... 3-49 IOP Throughput .................................................................. 3-49 Programming Model ................................................................... 3-50 General Procedure for Configuring DMA .............................. 3-50 Debug Features ........................................................................... 3-50 Emulation Considerations ..................................................... 3-51

EXTERNAL PORTFeatures ........................................................................................ 4-2 Pin Descriptions ........................................................................... 4-3 Pin Multiplexing ..................................................................... 4-3 Register Overview ......................................................................... 4-4 External Port ........................................................................... 4-4 Asynchronous Memory Interface ............................................. 4-4 SDRAM Controller ................................................................. 4-4 DDR2 Controller ................................................................... 4-5 Shared DDR2 Memory ........................................................... 4-6 Clocking AMI/SDRAM (ADSP-2147x/ ADSP-2148x Models) ...... 4-6 Clocking AMI/DDR2 (ADSP-2146x Models) ............................... 4-7 External Port Arbiter .................................................................... 4-8 Functional Description ........................................................... 4-8 Operating Mode ................................................................... 4-10 Arbitration Modes ............................................................ 4-10 Arbitration Freezing .......................................................... 4-11

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Asynchronous Memory Interface ................................................. 4-12 Features ................................................................................. 4-12 Functional Description .......................................................... 4-12 Parameter Timing ............................................................. 4-13 Asynchronous Reads ...................................................... 4-14 Asynchronous Writes ..................................................... 4-15 Idle Cycles .................................................................... 4-15 Wait States .................................................................... 4-16 Hold Cycles .................................................................. 4-16 Data Storage and Packing .............................................. 4-16 External Instruction Fetch ..................................................... 4-17 Interrupt Vector Table (IVT) ............................................. 4-17 Instruction Packing ........................................................... 4-18 External Instruction Fetch from AMI Boot Space ............... 4-18 8-Bit Instruction Storage and Packing ................................ 4-19 16-Bit Instruction Storage and Packing .............................. 4-20 Mixing Instructions and Data in External Bank 0 .............. 4-21 Cache for External Instruction Fetch ............................. 4-22 Operating Modes ................................................................... 4-25 Data Packing .................................................................... 4-25 External Access Extension .................................................. 4-25 Predictive Reads ................................................................ 4-26 SDRAM Controller (ADSP-2147x/ADSP-2148x) .................................................... 4-27 Features ................................................................................. 4-27 ADSP-214xx SHARC Processor Hardware Reference ix

Contents

Pin Descriptions ................................................................... 4-28 Functional Description ......................................................... 4-28 SDRAM Commands ........................................................ 4-29 Load Mode Register ...................................................... 4-30 Bank Activation ............................................................ 4-31 Single Precharge ........................................................... 4-31 Precharge All ................................................................ 4-31 Read/Write ................................................................... 4-32 Auto-Refresh ................................................................ 4-34 No Operation/Command Inhibit .................................. 4-34 Command Truth Table ................................................. 4-34 Refresh Rate Control ........................................................ 4-35 Internal SDRAM Bank Access ........................................... 4-37 Single Bank Access ........................................................ 4-37 Multi-Bank Access ........................................................ 4-37 Multi-Bank Operation with Data Packing ..................... 4-39 Timing Parameters ............................................................ 4-40 Fixed Timing Parameters ............................................... 4-40 Data Mask ........................................................................ 4-40 Resetting the Controller .................................................... 4-41 16-Bit Data Storage and Packing ....................................... 4-41 External Instruction Fetch ................................................ 4-42 Interrupt Vector Table (IVT) ........................................ 4-42 Fetching ISA Instructions From External Memory ......... 4-42

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Contents

Instruction Packing ....................................................... 4-43 16-Bit Instruction Storage and Packing .......................... 4-43 Fetching VISA Instructions From External Memory ....... 4-44 Mixing Instructions and Data in External Bank 0 ........... 4-46 Cache for External Instruction Fetch ............................. 4-47 Address Versus SDRAM Types ....................................... 4-50 Operating Modes ................................................................... 4-50 Address Mapping .............................................................. 4-50 Address Translation Options .......................................... 4-51 Address Width Settings ................................................. 4-52 16-Bit Address Mapping .................................................... 4-53 Parallel Connection of SDRAMs ....................................... 4-56 Buffering Controller for Multiple SDRAMs ................... 4-57 SDRAM Read Optimization ............................................. 4-57 Core Accesses ................................................................ 4-59 DMA Access ................................................................. 4-60 Notes on Read Optimization ......................................... 4-61 Self-Refresh Mode ............................................................. 4-61 Forcing SDRAM Commands ............................................. 4-62 Force Precharge All ....................................................... 4-63 Force Load Mode Register ............................................. 4-63 Force Auto-Refresh ........................................................ 4-63 DDR2 DRAM Controller (ADSP-2146x) .................................... 4-63 Features ................................................................................. 4-64


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Contents

Pin Descriptions ................................................................... 4-64 Functional Description ......................................................... 4-65 DDR2 Controller ............................................................. 4-66 DDR2 Arbiter .................................................................. 4-66 DDR2 PHY ..................................................................... 4-67 DDR2 Memory DLL ........................................................ 4-68 Self Calibration Logic ....................................................... 4-69 Mode Registers ................................................................. 4-69 Load Mode Register ...................................................... 4-70 Load Extended Mode Register ....................................... 4-70 Load Extended Mode Register 2 .................................... 4-70 Load Extended Mode Register 3 .................................... 4-71 DDR2 Commands ........................................................... 4-71 Bank Activation ............................................................ 4-71 Precharge ...................................................................... 4-71 Precharge All ................................................................ 4-72 Burst Read .................................................................... 4-72 Burst Write ................................................................... 4-73 Auto-Refresh ................................................................ 4-74 Self-Refresh Entry ......................................................... 4-74 Self-Refresh Exit ........................................................... 4-75 Precharge Power-Down Entry ....................................... 4-76 Precharge Power-down Exit ........................................... 4-77 No Operation/Command Inhibit .................................. 4-77

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Refresh Rate Control ......................................................... 4-78 Data Mask ........................................................................ 4-80 Resetting the Controller .................................................... 4-80 Automated Initialization Sequence ..................................... 4-80 Initialization Time ........................................................ 4-82 Internal DDR2 Bank Access .......................................... 4-82 16-Bit Data Storage and Packing ................................... 4-87 External Instruction Fetch ............................................. 4-87 Operating Modes ................................................................... 4-88 Address Mapping .............................................................. 4-88 Address Translation Options .......................................... 4-88 Page Interleaving Map ................................................... 4-89 Bank Interleaving Map .................................................. 4-89 Address Width Settings ................................................. 4-90 16-Bit Address Mapping ................................................ 4-91 Address Map Tables ....................................................... 4-91 Parallel Connection of DDR2s .......................................... 4-95 Buffering Controller for Multiple DDR2s ...................... 4-95 Read Optimization ............................................................ 4-95 Read Optimization Modifier ......................................... 4-96 Self-Refresh Mode ............................................................. 4-99 Single-Ended Data Strobe ............................................... 4-101 On Die Termination (ODT) ........................................... 4-101 Additive Latency ............................................................. 4-102


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Contents

Forcing DDR2 Commands ............................................. 4-102 Force Precharge All ..................................................... 4-102 Force Load Mode Register ........................................... 4-103 Force Auto-Refresh ..................................................... 4-103 Force Extended Mode Register 13 ............................. 4-103 Force DLL External Bank Calibration ......................... 4-103 Shared Memory Interface (ADSP-2146x) .................................. 4-104 Features .............................................................................. 4-104 Pin Descriptions ................................................................. 4-104 Functional Description ....................................................... 4-105 Bus Transition Cycle ....................................................... 4-106 DDR2 Bus Mastership Transfer ...................................... 4-109 Bus Synchronization After Reset ..................................... 4-110 Operating Modes ................................................................ 4-112 Bus Mastership Time-Out ............................................... 4-112 Bus Lock ........................................................................ 4-113 Data Transfer ........................................................................... 4-115 Data Buffers ....................................................................... 4-115 Receive Buffer Unpacking ............................................... 4-115 Transmit Buffer Unpacking ............................................. 4-115 External Port DMA Buffer .............................................. 4-116 Buffer Status ............................................................... 4-116 Flush Buffer ............................................................... 4-116 Core Access ......................................................................... 4-116

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External Port Dual Data Fetch ......................................... 4-117 Conditional Instructions ................................................. 4-117 SIMD Access ....................................................................... 4-117 SDRAM ......................................................................... 4-118 DDR2 ............................................................................ 4-118 External Port DMA ................................................................... 4-120 Features ............................................................................... 4-120 DMA Parameter Registers .................................................... 4-120 Functional Description ........................................................ 4-122 DMA Addressing ............................................................ 4-122 Operating Modes ................................................................. 4-122 Standard DMA ............................................................... 4-124 Circular Buffered DMA .................................................. 4-124 Chained DMA Mode ...................................................... 4-126 Data Direction on the Fly ........................................... 4-126 Write Back Circular Index Pointer ................................... 4-127 Scatter/Gather DMA ....................................................... 4-128 Pre Modified Read/Write Index ................................... 4-129 Delay Line DMA ............................................................ 4-133 Pre-Modified Read Index ............................................. 4-136 External Port DMA Group Priority ................................. 4-137 Interrupts ................................................................................. 4-138 Sources ................................................................................ 4-138 Delay Line DMA ............................................................ 4-138


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Scatter Gather DMA ...................................................... 4-138 Internal Transfer Completion .......................................... 4-138 Access Completion ......................................................... 4-139 Chained DMA ............................................................... 4-139 Masking .............................................................................. 4-140 Service ................................................................................ 4-140 Interrupt Dependency on DMA Mode ................................ 4-140 External Port Throughput ......................................................... 4-141 Data Throughput ................................................................ 4-141 DMA Throughput .......................................................... 4-142 Core Throughput ........................................................... 4-143 DDR2 Read Optimization .............................................. 4-144 Throughput Conditional Instructions ............................. 4-148 External Instruction Fetch Throughput ............................... 4-148 SDRAM Throughput ..................................................... 4-148 DDR2 Throughput ........................................................ 4-149 AMI Throughput ........................................................... 4-149 Effect Latency .......................................................................... 4-149 Programming Models ............................................................... 4-150 AMI Initialization ............................................................... 4-150 AMI Instruction Fetch .................................................... 4-151 SDRAM Controller ............................................................. 4-151 Power-Up Sequence ........................................................ 4-151 Changing the SDRAM Clock on the Fly ......................... 4-152

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Contents

SDRAM Instruction Fetch .............................................. 4-153 Output Clock Generator Programming Model ................. 4-153 Self-Refresh Mode ........................................................... 4-154 Changing the VCO Clock During Runtime ..................... 4-154 DDR2 Controller ................................................................ 4-156 Power-Up Sequence ........................................................ 4-156 Changing the DDR2 Clock on the Fly ............................ 4-158 Changing the Clock Frequency During Precharge Power Down Mode ............................................................. 4-158 Changing the Clock Frequency During Self-Refresh Mode ....................................................................... 4-159 External Port DMA ............................................................. 4-160 Standard DMA .............................................................. 4-160 Chained DMA ................................................................ 4-161 Delay Line DMA ............................................................ 4-162 Disabling and Re-enabling DMA ..................................... 4-162 Additional Information ................................................... 4-163 External Instruction Fetch ................................................... 4-164 AMI Configuration ......................................................... 4-164 SDRAM Configuration ................................................... 4-164 DDR2 Instruction Fetch ................................................. 4-165 External Memory Access Restrictions ................................... 4-165 Debug Features ......................................................................... 4-166 Core FIFO Write ................................................................. 4-166


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LINK PORTS ADSP-2146XFeatures ........................................................................................ 5-2 Pin Descriptions ........................................................................... 5-3 Register Overview ......................................................................... 5-3 Clocking ...................................................................................... 5-4 Functional Description ................................................................. 5-4 Architecture ............................................................................ 5-4 Protocol .................................................................................. 5-5 Intercommunication ............................................................... 5-7 Self-Synchronization ............................................................... 5-9 Multi-Master Conflicts ............................................................ 5-9 Operating Modes ........................................................................ 5-10 Receive Link Service Request Mode ....................................... 5-10 Transmit Link Service Request Mode ..................................... 5-10 Example Token Passing ......................................................... 5-10 Data Transfer ............................................................................. 5-13 Packing Registers .................................................................. 5-13 Output Register ................................................................ 5-13 Input Register .................................................................. 5-13 Buffers .................................................................................. 5-14 Transmit Buffer ................................................................ 5-14 Receive Buffer .................................................................. 5-14 Buffer Status ..................................................................... 5-15 Buffer Reception Error ..................................................... 5-15

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Flushing Buffers ................................................................ 5-15 Buffer Hand Disable ......................................................... 5-15 Core Transfers ....................................................................... 5-15 DMA Transfers ...................................................................... 5-16 Link Port DMA Group Priority ............................................. 5-16 Interrupts ................................................................................... 5-17 Sources .................................................................................. 5-17 Core Buffer Service Request .............................................. 5-18 DMA Complete ................................................................ 5-18 Internal Transfer Complete ................................................ 5-18 Access Complete ............................................................... 5-18 Link Service Request ......................................................... 5-18 Chained DMA .................................................................. 5-19 Protocol Error ................................................................... 5-19 Masking ................................................................................ 5-19 Service .................................................................................. 5-19 Effect Latency ............................................................................. 5-20 Write Effect Latency .............................................................. 5-20 Link Port Effect Latency ........................................................ 5-20 Programming Model ................................................................... 5-20 Changing the Link Port Clock ............................................... 5-20 Receive DMA ........................................................................ 5-21 Transmit DMA ...................................................................... 5-22 Debug Features ........................................................................... 5-22


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Contents

Shadow Register .................................................................... 5-23 Buffer Hang Disable (BHD) .................................................. 5-23

MEMORY-TO-MEMORY PORT DMAFeatures ........................................................................................ 6-2 Register Overview ......................................................................... 6-2 Clocking ...................................................................................... 6-2 Functional Description ................................................................. 6-3 Data Transfer Types ...................................................................... 6-3 Buffer ..................................................................................... 6-3 Buffer Status ....................................................................... 6-4 Flushing the Buffer ............................................................. 6-4 DMA Transfer ........................................................................ 6-4 Interrupts ..................................................................................... 6-4 Sources ................................................................................... 6-5 DMA Complete ................................................................. 6-5 Masking .................................................................................. 6-5 Service .................................................................................... 6-6 MTM Throughput ....................................................................... 6-6 Effect Latency .............................................................................. 6-6 Write Effect Latency ............................................................... 6-6 MTM Effect Latency .............................................................. 6-6 Programming Model ..................................................................... 6-7

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FFT/FIR/IIR HARDWARE MODULESFFT Accelerator ............................................................................ 7-3 Features ................................................................................... 7-4 Register Descriptions ............................................................... 7-4 Clocking ................................................................................. 7-5 Functional Description ............................................................ 7-5 Compute Block ................................................................... 7-5 Data Memory ..................................................................... 7-6 Coefficient Memory ............................................................ 7-6 Accelerator States ................................................................ 7-6 Reset State ...................................................................... 7-6 Idle State ........................................................................ 7-7 Read State ....................................................................... 7-7 Processing State ............................................................... 7-7 Write State ...................................................................... 7-7 Internal Memory Storage ..................................................... 7-8 Small FFT N256 ........................................................... 7-9 Operating Modes ................................................................... 7-10 Small FFT Computation ( 256 Points) ............................. 7-11 Example for FFT Size N=512 ............................................ 7-11 Vertical FFT ................................................................. 7-11 Special ProductNumber of Iterations is N/128 = 4 ..... 7-12


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Contents

Horizontal FFT ............................................................ 7-13 No Repeat Mode .............................................................. 7-13 Repeat Mode .................................................................... 7-13 Unpacked Data Mode ....................................................... 7-14 Inverse FFT ...................................................................... 7-14 Data Transfer ........................................................................ 7-14 FFT Buffers ...................................................................... 7-15 Buffer Status ................................................................. 7-15 Flushing the Buffer ....................................................... 7-15 DMA Transfers ................................................................. 7-15 DMA Channels and TCB Structure .............................. 7-15 Chained DMA .............................................................. 7-16 Interrupts ............................................................................. 7-17 Sources ............................................................................. 7-18 DMA Complete ............................................................ 7-18 MAC Status ................................................................. 7-18 Chained DMA ............................................................. 7-18 Masking ........................................................................... 7-18 Service ............................................................................. 7-19 FFT Performance .................................................................. 7-19 Small FFT (N is = 256) ...................................................... 7-20 Vertical FFT Cycles .............................................................. 7-20 Special Prod Cycles ............................................................... 7-20

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Horizontal FFT Cycles .......................................................... 7-20 Effect Latency ....................................................................... 7-20 Write Effect Latency ......................................................... 7-21 FFT Accelerator Effect Latency ......................................... 7-21 Programming Model .............................................................. 7-21 N = 512, Repeat ............................................................. 7-26 Using Debug Mode ........................................................... 7-27 Write to Local Memory ................................................. 7-27 Read from Local Memory .............................................. 7-27 Debug Features ..................................................................... 7-28 Local Memory Access ........................................................ 7-28 Shadow Register ................................................................ 7-28 FIR Accelerator ........................................................................... 7-28 Features ................................................................................. 7-29 Register Overview ................................................................. 7-29 Clocking ............................................................................... 7-30 Functional Description .......................................................... 7-30


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Contents

Compute Block ................................................................ 7-32 Partial Sum Register .......................................................... 7-32 Delay Line Memory .......................................................... 7-32 Coefficient Memory ......................................................... 7-33 Pre Fetch Data Buffer ....................................................... 7-33 Processing Output ............................................................ 7-34 Internal Memory Storage .................................................. 7-36 Coefficients and Input Buffer Storage ............................ 7-36 Operating Modes .................................................................. 7-37 Single Rate Processing ...................................................... 7-37 Single Iteration ............................................................. 7-38 Multi Iteration .............................................................. 7-38 Window Processing ......................................................... 7-38 Multi Rate Processing ...................................................... 7-39 Decimation ...................................................................... 7-39 Interpolation .................................................................... 7-40 Channel Processing ........................................................... 7-41 Floating-Point Data Format .............................................. 7-41 Fixed-Point Data Format .................................................. 7-43 Data Transfer ........................................................................ 7-43 DMA Access ..................................................................... 7-43 Chain Pointer DMA ..................................................... 7-43 Interrupts ............................................................................. 7-45 Sources ............................................................................ 7-45

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Window Complete ........................................................ 7-46 All Channels Complete ................................................. 7-46 Chained DMA ............................................................. 7-46 MAC Status ................................................................. 7-46 Masking ............................................................................ 7-47 Service .............................................................................. 7-47 Effect Latency ....................................................................... 7-48 Write Effect Latency ......................................................... 7-48 FIR Accelerator Effect Latency .......................................... 7-48 FIR Throughput .................................................................... 7-49 Programming Model .............................................................. 7-49 Single Channel Processing ................................................. 7-50 Multichannel Processing .................................................... 7-51 Dynamic Coefficient Processing Notes ............................... 7-52 Debug Mode ..................................................................... 7-53 Write to Local Memory ................................................. 7-53 Read from Local Memory .............................................. 7-53 Single Step Mode .............................................................. 7-54 FIR Programming Example ............................................... 7-54 Computing FIR Output, Tap Length > Than 4096 ............ 7-56 Debug Features ..................................................................... 7-58 Local Memory Access ........................................................ 7-58 Single Step Mode .............................................................. 7-59 Emulation Considerations ................................................. 7-59


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IIR Accelerator ........................................................................... 7-59 Features ................................................................................ 7-59 Register Overview ................................................................. 7-60 Clocking ............................................................................... 7-60 Functional Description ......................................................... 7-61 Multiply and Accumulate (MAC) Unit .............................. 7-63 Input Data and Biquad State ............................................. 7-64 Coefficient Memory ......................................................... 7-64 Internal Memory Storage .................................................. 7-64 Coefficient Memory Storage ......................................... 7-64 Operating Modes .................................................................. 7-65 Window Processing .......................................................... 7-65 40-Bit Floating-Point Mode .............................................. 7-65 Save Biquad State Mode .................................................... 7-66 Data Transfers ....................................................................... 7-66 DMA Access ..................................................................... 7-67 Chain Pointer DMA ..................................................... 7-67 Interrupts ............................................................................. 7-68 Sources ............................................................................ 7-69 Window Complete ....................................................... 7-69 All Channels Complete ................................................. 7-69 Chained DMA ............................................................. 7-69 MAC Status ................................................................. 7-69 Masking ........................................................................... 7-70

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Service .............................................................................. 7-70 Effect Latency ....................................................................... 7-71 Write Effect Latency ......................................................... 7-71 IIR Accelerator Effect Latency ........................................... 7-71 IIR Throughput .................................................................... 7-72 Programming Model .............................................................. 7-72 Dynamic Coefficient Processing Notes ............................... 7-74 Writing to Local Memory .................................................. 7-74 Reading from Local Memory ............................................. 7-75 Single Step Mode .............................................................. 7-76 Save Biquad State of the IIR .............................................. 7-76 Programming Example ...................................................... 7-77 Throughput Comparison Accelerator Versus Core ............... 7-78 FFT .................................................................................. 7-79 FIR ................................................................................... 7-79 IIR ................................................................................... 7-81 Debug Features ..................................................................... 7-83 Local Memory Access ........................................................ 7-83 Single Step Mode .............................................................. 7-84 Emulation Considerations ................................................. 7-84 Application Guidelines for Effective Use of the FIR/IIR/FFT Accelerators .............................................................................. 7-85 Sample Versus Block Processing Operation ............................. 7-85 Adding Pipeline Stages ........................................................... 7-86 Splitting Tasks ....................................................................... 7-86 ADSP-214xx SHARC Processor Hardware Reference xxvii

Contents

PULSE WIDTH MODULATIONFeatures ........................................................................................ 8-2 Pin Descriptions ........................................................................... 8-4 Multiplexing Scheme .............................................................. 8-4 SRU Programming ....................................................................... 8-5 Register Overview ......................................................................... 8-5 Clocking ...................................................................................... 8-6 Functional Description ................................................................. 8-6 Two-Phase PWM Generator .................................................... 8-6 Switching Frequencies ......................................................... 8-6 Duty Cycles ........................................................................ 8-7 Dead Time ....................................................................... 8-12 Output Control Unit ............................................................ 8-13 Output Enable ................................................................. 8-13 Output Polarity ................................................................ 8-13 Complementary Outputs .................................................. 8-14 Crossover ......................................................................... 8-14 Emergency Dead Time for Over Modulation ......................... 8-15 Output Control Feature Precedence .................................. 8-16 Operation Modes ....................................................................... 8-17 Waveform Modes .................................................................. 8-17 Edge-Aligned Mode .......................................................... 8-18 Center-Aligned Mode ....................................................... 8-19 PWM Timer Edge Aligned Update ........................................ 8-21

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Single Update Mode .......................................................... 8-22 Double Update Mode ....................................................... 8-22 Effective Accuracy ................................................................. 8-23 Synchronization of PWM Groups ........................................... 8-24 Interrupts ................................................................................... 8-24 Sources .................................................................................. 8-25 PWM Period ..................................................................... 8-25 Masking ................................................................................ 8-25 Service .................................................................................. 8-25 Effect Latency ............................................................................. 8-27 Write Effect Latency .............................................................. 8-27 PWM Effect Latency ............................................................. 8-27 Debug Features ........................................................................... 8-27 Status Debug Register ............................................................ 8-27 Emulation Considerations ..................................................... 8-27

MEDIA LOCAL BUSFeatures ........................................................................................ 9-3 Pin Descriptions ........................................................................... 9-4 Register Overview ......................................................................... 9-4 Device Configuration and Status Registers ............................... 9-4 Channel Registers .................................................................... 9-5 Clocking ....................................................................................... 9-5 Functional Description ................................................................. 9-6 Media LB Protocol .................................................................. 9-7


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Operating Modes .......................................................................... 9-8 Logical Channel Control ......................................................... 9-8 Synchronous Channels ............................................................ 9-9 Asynchronous Channels ........................................................ 9-10 Control Channels ................................................................. 9-10 Data Transfer ............................................................................. 9-11 Core Access ........................................................................... 9-11 Threshold Depth .............................................................. 9-11 Status ........................................................................... 9-13 Flushing the Buffer ....................................................... 9-13 DMA .................................................................................... 9-13 MLB DMA Group Priority ................................................... 9-14 Ping-Pong DMA ............................................................... 9-15 Circular Buffer DMA ....................................................... 9-16 Interrupts ................................................................................... 9-18 Sources ................................................................................. 9-18 Core Buffer Service Request .............................................. 9-18 Threshold Transmit Request ............................................. 9-19 Threshold Receive Request ............................................... 9-19 DMA Complete ............................................................... 9-19 Receive Channel Errors ..................................................... 9-19 Masking ................................................................................ 9-19 Service .................................................................................. 9-20 Programming Model ................................................................... 9-20

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Contents

I/O Interrupt Mode ............................................................... 9-20 DMA Modes ......................................................................... 9-21 Debug Features ........................................................................... 9-23 Loop-Back Test Mode ............................................................ 9-23

DIGITAL APPLICATION/ DIGITAL PERIPHERAL INTERFACESSRU Features .............................................................................. 10-2 Register Overview ....................................................................... 10-3 Clocking ..................................................................................... 10-4 Functional Description ............................................................... 10-5 DAI/DPI Signal Naming Conventions ................................... 10-8 I/O Pin Buffers ..................................................................... 10-9 Pin Buffer Signals ............................................................. 10-9 Pin Buffer Input Signal ................................................. 10-9 Pin Buffer Enable Signal .............................................. 10-10 Pin Buffer Functions ....................................................... 10-10 Pin Buffers as Signal Input .......................................... 10-11 Pin Buffers As Signal Output ....................................... 10-11 Pin Buffers as Open Drain ........................................... 10-13 DAI/DPI Pin Buffer Status .......................................... 10-13 DAI/DPI Peripherals ........................................................... 10-14 Output Signals With Pin Buffer Enable Control .............. 10-14 Output Signals Without Pin Buffer Enable Control ......... 10-15 Signal Routing Units (SRUs) ............................................... 10-15


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Signal Routing Matrix by Groups .................................... 10-16 DAI/DPI Group Routing ................................................ 10-17 Rules for SRU Connections ............................................ 10-19 Miscellaneous Buffers and Functions ................................... 10-19 DAI/DPI Routing Capabilities ............................................ 10-22 DAI Routing Capabilities ................................................ 10-22 DPI Routing Capabilities ................................................ 10-24 DAI Default Routing .......................................................... 10-24 DPI Default Routing .......................................................... 10-27 Unused DAI/DPI Connections ............................................ 10-28 Operating Modes ...................................................................... 10-28 DAI Pin Buffer Polarity ....................................................... 10-29 DAI Miscellaneous Buffer Polarity ....................................... 10-29 Interrupts ................................................................................. 10-30 DAI/DPI Miscellaneous Interrupts ....................................... 10-30 Sources ........................................................................... 10-31 Edge Detection ........................................................... 10-31 Masking ......................................................................... 10-31 Service ........................................................................... 10-32 Effect Latency .......................................................................... 10-32 Write Effect Latency ........................................................... 10-32 Signal Routing Unit Effect Latency ...................................... 10-32 Programming Model ................................................................. 10-32 Making SRU Connections ................................................... 10-34

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DAI Example System ........................................................... 10-38 Debug Features ......................................................................... 10-39 Shadow Interrupt Registers .................................................. 10-39 Loopback Routing ............................................................... 10-39

SERIAL PORTS (SPORTS)Features ...................................................................................... 11-2 Serial Port Versus Input Data Port Features ............................ 11-4 Pin Descriptions ......................................................................... 11-5 SRU Programming ...................................................................... 11-6 SRU SPORT Receive Master ................................................. 11-7 SRU SPORT Signal Integrity ................................................. 11-7 Register Overview ....................................................................... 11-8 Clocking ..................................................................................... 11-9 Master Clock ....................................................................... 11-10 Master Frame Sync .............................................................. 11-10 General-Purpose Pulse Generator ......................................... 11-11 Slave Mode .......................................................................... 11-11 Mixed Mode ........................................................................ 11-12 Maximum Clock Rate Restrictions ....................................... 11-12 Clock Power Savings ............................................................ 11-12 Functional Description ............................................................. 11-13 Architecture ........................................................................ 11-13 Companding ................................................................... 11-14 Frame Sync and Data Sampling ........................................... 11-16


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Continuous Framed Data Transfers ................................. 11-17 SPORT Protocols ................................................................ 11-17 Standard Serial Protocol .................................................. 11-17 Protocol Configuration Options .................................. 11-17 Left-Justified Protocol ..................................................... 11-18 Protocol Configuration Options .................................. 11-18 I2S Protocol .................................................................... 11-19 Protocol Configuration Options .................................. 11-19 I2S Compatibility ....................................................... 11-19 Channel Order First .................................................... 11-20 Multichannel Protocol .................................................... 11-20 Protocol Configuration Options .................................. 11-21 Multiple Channels ...................................................... 11-21 Multichannel Frame Sync Delay .................................. 11-22 Number of Channels (NCH) ...................................... 11-23 Active Channel Selection Registers .............................. 11-23 Active Channel Companding Selection Registers ......... 11-24 Companding Limitations (ADSP-2146x) .................... 11-25 Transmit Data Valid Output Enable ............................ 11-25 Multichannel Protocol Backward Compatibility ........... 11-26 Packed Protocol .............................................................. 11-26 Protocol Configuration Options .................................. 11-27 Packed Words ............................................................. 11-27 Operating Modes ...................................................................... 11-28

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Mode Selection .................................................................... 11-32 Data Direction ................................................................ 11-32 Serial Word Length ......................................................... 11-32 Data Types Format .......................................................... 11-33 Sampling Edge ................................................................ 11-33 Frame Sync Modes .............................................................. 11-34 Framed Versus Unframed Frame Syncs ............................. 11-34 Early Versus Late Frame Syncs ......................................... 11-35 Internal Versus External Frame Syncs................................ 11-36 Polarity Frame Sync Level ................................................ 11-37 Frame Sync Generation ................................................... 11-37 Data-Independent Frame Sync ..................................... 11-37 Channel Dependency .................................................. 11-38 Frame Sync Error Detection ............................................ 11-39 Internal Frame Sync Errors .......................................... 11-39 External Frame Sync Errors ......................................... 11-39 Data Transfers ........................................................................... 11-40 Serial Shift Registers ............................................................ 11-41 Output Shift Register ...................................................... 11-41 Input Shift Register ......................................................... 11-41 Buffers ................................................................................ 11-41 Transmit Buffers ............................................................. 11-42 Receive Buffers ............................................................... 11-42 Buffer Packing ................................................................ 11-43


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Companding .............................................................. 11-43 Buffer Status .................................................................. 11-44 Buffer Errors .................................................................. 11-44 Reception Error .......................................................... 11-45 Transmission Error ..................................................... 11-45 Flushing Buffers ............................................................. 11-45 Core Transfers ..................................................................... 11-45 DMA Transfers ................................................................... 11-46 SPORT DMA Group Priority ......................................... 11-47 Standard DMA ............................................................... 11-48 DMA Chaining .............................................................. 11-49 DMA Chain Insertion Mode ........................................... 11-50 SPORT DMA to External Memory ................................. 11-50 SPORT SPEP Bus Priority .......................................... 11-51 Interrupts ................................................................................. 11-51 Sources ............................................................................... 11-52 Core Buffer Service Request ............................................ 11-52 Data Buffer Packing ........................................................ 11-52 DMA Complete ............................................................. 11-52 Internal Transfer Complete ............................................. 11-53 Access Complete ............................................................. 11-53 Chained DMA ............................................................... 11-53 Buffer Over/Underflow .................................................. 11-54 Unexpected Frame Sync Errors ........................................ 11-54

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Masking .............................................................................. 11-54 Service ................................................................................ 11-55 Throughput .............................................................................. 11-56 Effect Latency ..................................................................... 11-56 Write Effect Latency ....................................................... 11-57 SPORT Effect Latency .................................................... 11-57 Programming Model ................................................................. 11-57 Setting Up and Starting DMA Master Mode ........................ 11-57 Setting Up and Starting Chained DMA ................................ 11-58 Enter DMA Chain Insertion Mode ...................................... 11-58 Setting Up and Starting Multichannel Mode ........................ 11-59 Multichannel Mode Backward Compatibility ................... 11-60 Programming Packed Mode ................................................. 11-61 External Frame Sync Operation ........................................... 11-62 Companding As a Function ................................................. 11-62 Debug Features ......................................................................... 11-63 SPORT Loopback ............................................................... 11-64 LoopBack Routing .......................................................... 11-64 Buffer Hang Disable (BHD) ................................................ 11-64

INPUT DATA PORT (SIP, PDAP)Features ...................................................................................... 12-2 Pin Descriptions ......................................................................... 12-3 SRU Programming ...................................................................... 12-4 Register Overview ....................................................................... 12-5


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Clocking .................................................................................... 12-5 Functional Description ............................................................... 12-6 Operating Modes ........................................................................ 12-7 PDAP Port Selection ............................................................. 12-8 Data Hold ............................................................................ 12-9 PDAP Data Masking ........................................................... 12-10 PDAP Data Packing ............................................................ 12-10 No Packing ..................................................................... 12-10 Packing by 2 ................................................................... 12-11 Packing by 3 ................................................................... 12-12 Packing by 4 ................................................................... 12-13 Data Transfer ........................................................................... 12-14 Buffers ................................................................................ 12-14 Buffer Threshold Depth .................................................. 12-14 Buffer Status ................................................................... 12-15 Buffer Error Status .......................................................... 12-15 Flushing the Buffer ......................................................... 12-15 Buffer Hang Disable ....................................................... 12-15 Core Transfers ..................................................................... 12-16 SIP Data Buffer Format .................................................. 12-16 PDAP Data Buffer Format .............................................. 12-19 DMA Transfers ................................................................... 12-19 Data Buffer Format for DMA ......................................... 12-20 IDP DMA Group Priority ............................................... 12-20

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Standard DMA ............................................................... 12-20 Ping-Pong DMA ............................................................. 12-21 Multichannel DMA Operation ........................................ 12-22 Multichannel FIFO Status ............................................... 12-23 Interrupts ................................................................................. 12-24 Sources ................................................................................ 12-24 Core Buffer Service Request ............................................ 12-24 Interrupt Acknowledge .................................................... 12-24 Buffer Threshold ............................................................. 12-25 DMA Complete .............................................................. 12-25 Buffer Overflow .............................................................. 12-25 Masking .............................................................................. 12-26 Service ................................................................................ 12-26 Effect Latency ........................................................................... 12-26 Write Effect Latency ............................................................ 12-27 IDP Effect Latency .............................................................. 12-27 Programming Model ................................................................. 12-27 Setting Miscellaneous Bits ................................................... 12-27 Starting Core Interrupt-Driven Transfer ............................... 12-28 Additional Notes ............................................................. 12-29 Starting A Standard DMA Transfer ...................................... 12-30 Starting a Ping-Pong DMA Transfer ..................................... 12-31 Servicing Interrupts for DMA .............................................. 12-31 Debug Features ......................................................................... 12-33


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Status Register Debug ......................................................... 12-33 Buffer Hang Disable ........................................................... 12-33 Shadow Interrupt Registers .................................................. 12-34 Core FIFO Write ................................................................ 12-34

ASYNCHRONOUS SAMPLE RATE CONVERTERFeatures ...................................................................................... 13-2 Pin Descriptions ......................................................................... 13-3 SRU Programming ..................................................................... 13-4 Register Overview ....................................................................... 13-4 Clocking .................................................................................... 13-5 Functional Description ............................................................... 13-5 I/O Ports .............................................................................. 13-5 De-Emphasis Filter ............................................................... 13-6 Mute Control ....................................................................... 13-7 SRC Core ............................................................................. 13-7 RAM FIFO ...................................................................... 13-8 Digital Servo Loop ........................................................... 13-8 FIR Filter ......................................................................... 13-9 Sample Rate Sensing ......................................................... 13-9 Digital Filter Group Delay .............................................. 13-10 Data Format ....................................................................... 13-10 Operating Modes ...................................................................... 13-11 TDM Input Mode .............................................................. 13-11 TDM Output Mode ........................................................... 13-12

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Matched-Phase Mode (ADSP-21488) .................................. 13-13 Bypass Mode ....................................................................... 13-14 De-Emphasis Mode ............................................................. 13-15 Dithering Mode .................................................................. 13-15 Muting Modes ..................................................................... 13-15 Soft Mute ....................................................................... 13-16 Hard Mute ...................................................................... 13-16 Auto Mute ...................................................................... 13-16 Interrupts ................................................................................. 13-17 Sources ................................................................................ 13-17 SRC Mute Out ............................................................... 13-17 Masking .............................................................................. 13-17 Service ................................................................................ 13-18 Effect Latency ........................................................................... 13-18 Write Effect Latency ............................................................ 13-18 ASRC Effect Latency ........................................................... 13-18 Programming Model ................................................................. 13-19 Debug Features ......................................................................... 13-19 Shadow Interrupt Registers .................................................. 13-19

SONY/PHILIPS DIGITAL INTERFACEFeatures ...................................................................................... 14-2 Pin Descriptions ......................................................................... 14-3 SRU Programming ...................................................................... 14-4 Register Overview ....................................................................... 14-6


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Clocking .................................................................................... 14-6 S/PDIF Transmitter .................................................................... 14-7 Functional Description ......................................................... 14-7 Input Data Formats .......................................................... 14-9 Operating Modes ................................................................ 14-11 Full Serial Mode ............................................................. 14-11 Standalone Mode ............................................................ 14-11 Data Output Mode ......................................................... 14-12 S/PDIF Receiver ....................................................................... 14-13 Functional Description ....................................................... 14-13 Clock Recovery .............................................................. 14-15 Output Data Format ...................................................... 14-15 Channel Status ............................................................... 14-16 Operating Modes ................................................................ 14-16 Compressed or Non-linear Audio Data ............................ 14-16 Emphasized Audio Data .............................................. 14-17 Single-Channel Double-Frequency Mode .................... 14-18 Clock Recovery Modes ................................................... 14-18 Digital On-Chip PLL ................................................. 14-18 Interrupts ................................................................................. 14-19 Sources ............................................................................... 14-19 Transmit Block Start ....................................................... 14-19 Receiver Status ............................................................... 14-20 Receiver Error ................................................................ 14-20

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Masking .............................................................................. 14-20 Service ................................................................................ 14-21 Effect Latency ........................................................................... 14-21 Write Effect Latency ............................................................ 14-21 Programming Model ................................................................. 14-21 Programming the Transmitter .............................................. 14-22 Programming the Receiver ................................................... 14-22 Interrupted Data Streams on the Receiver ............................ 14-23 Debug Features ......................................................................... 14-25 Loopback Routing ............................................................... 14-25 Shadow Interrupt Registers .................................................. 14-25

PRECISION CLOCK GENERATORFeatures ...................................................................................... 15-2 Pin Descriptions ......................................................................... 15-3 SRU Programming ...................................................................... 15-4 Register Overview ....................................................................... 15-5 Clocking ..................................................................................... 15-5 Functional Description ............................................................... 15-6 Serial Clock ........................................................................... 15-6 Frame Sync ........................................................................... 15-7 Frame Sync Output ........................................................... 15-7 Divider Mode Selection ..................................................... 15-8 Phase Shift ........................................................................ 15-8 Pulse Width .................................................................... 15-10


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Default Pulse Width ....................................................... 15-11 Input Clock Source Considerations ................................. 15-11 Timing Example for I2S Mode ........................................ 15-11 Operating Modes ...................................................................... 15-12 Normal Mode ..................................................................... 15-12 Bypass Mode ....................................................................... 15-13 One-Shot Mode .................................................................. 15-14 External Event Trigger ......................................................... 15-15 External Event Trigger Delay .......................................... 15-15 Audio System Example ........................................................ 15-16 Clock Configuration Examples ............................................ 15-18 Effect Latency .......................................................................... 15-19 Write Effect Latency ........................................................... 15-19 PCG Effect Latency ............................................................ 15-19 Programming Model ................................................................. 15-20 Frame Sync Phase Setting .................................................... 15-21 External Event Trigger ......................................................... 15-21 Debug Features ......................................................................... 15-22

SERIAL PERIPHERAL INTERFACE PORTSFeatures ...................................................................................... 16-2 Pin Descriptions ......................................................................... 16-3 SRU Programming ..................................................................... 16-4 Register Overview ....................................................................... 16-5 Clocking .................................................................................... 16-6 xliv ADSP-214xx SHARC Processor Hardware Reference

Contents

Choosing the Pin Enable for the SPI Clock ............................. 16-7 Functional Description ............................................................... 16-8 SPI Transaction ..................................................................... 16-9 Single Master Systems .......................................................... 16-10 Multi Master Systems .......................................................... 16-11 Operating Modes ...................................................................... 16-12 Transfer Initiate Mode ......................................................... 16-13 SPI Modes ........................................................................... 16-14 Slave Select Outputs ............................................................ 16-15 Variable Frame Delay for Slave ............................................. 16-17 Data Transfers ........................................................................... 16-18 Serial Shift Register ............................................................. 16-18 Output Shift Register ...................................................... 16-18 Input Shift Register ......................................................... 16-19 Buffers ................................................................................ 16-19 Transmit Buffer ............................................................... 16-19 Receive Buffer ................................................................. 16-20 Buffer Packing ............................................................ 16-20 Buffer Errors ................................................................... 16-21 Transmission Error ...................................................... 16-21 Reception Error .......................................................... 16-21 Transmit Collision Error ............................................. 16-21 Flush Buffer ................................................................ 16-22 Core Buffer Status ........................................................... 16-22


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DMA Buffer Status ......................................................... 16-23 Core Transfers ..................................................................... 16-24 Backward Compatibility ................................................. 16-24 DMA Transfers .................................................................... 16-24 DMA Chaining .............................................................. 16-27 DMA Transfer Count ..............

SHARC Processor Hardware Reference Manual

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