Shannon decomposition - Amazon Web...
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Shannon decomposition
William Sandqvist [email protected]
Claude Shannon mathematician / electrical engineer (1916 –2001)
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William Sandqvist [email protected]
(Ex 8.6) Show how a 4-to-1 multiplexer can be used as a "function generator" for example to generate the OR function.
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William Sandqvist [email protected]
(Ex 8.6) Show how a 4-to-1 multiplexer can be used as a "function generator" for example to generate the OR function.
Multiplexer as function generator
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William Sandqvist [email protected]
(Ex 8.6)
=
Show how a 4-to-1 multiplexer can be used as a "function generator" for example to generate the OR function.
Multiplexer as function generator
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William Sandqvist [email protected]
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William Sandqvist [email protected]
BV 6.1 Show how the function
can be implemented using a 3-to-8 decoder and an OR gate. ∑= )7,5,4,3,2,0(),,( 321 mwwwf
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William Sandqvist [email protected]
BV 6.1 Show how the function
can be implemented using a 3-to-8 decoder and an OR gate. ∑= )7,5,4,3,2,0(),,( 321 mwwwf
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William Sandqvist [email protected]
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William Sandqvist [email protected]
Ex 8.7
A majority gate outputs the same value as the majority of the inputs. The gate can for example be used in fault-tolerant logic, or in image processing circuits. a) (Set up the gate's truth table and minimize the function with Karnaugh map. Realize the function with AND-OR gates. ) b) Realize the majority gate with an 8: 1 MUX. c) Use Shannon decomposition and realize the majority gate with a 2: 1 MUX and gates. d) Realize the majority gate with only 2:1 MUXes.
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William Sandqvist [email protected]
8.7c
=+++=
=+++=
)()( bccbcbabca
abccabcbabcaM
Shannon decomposition. 2-to-1 mux and gates.
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William Sandqvist [email protected]
8.7c
=+++=
=+++=
)()( bccbcbabca
abccabcbabcaM
Shannon decomposition. 2-to-1 mux and gates.
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William Sandqvist [email protected]
8.7c
=+++=
=+++=
)()( bccbcbabca
abccabcbabcaM
OR
Shannon decomposition. 2-to-1 mux and gates.
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William Sandqvist [email protected]
8.7c
=+++=
=+++=
)()( bccbcbabca
abccabcbabcaM
OR )()( cbabca ++=
Shannon decomposition. 2-to-1 mux and gates.
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William Sandqvist [email protected]
8.7c
=+++=
=+++=
)()( bccbcbabca
abccabcbabcaM
OR )()( cbabca ++=
Shannon decomposition. 2-to-1 mux and gates.
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William Sandqvist [email protected]
8.7d
1)1()(
0)()0(
)()(
⋅+⋅=++=++=++=+=
⋅+⋅=+=
+==++=
bcbcbcbbcbcbcbbbcbh
cbbcbbg
cbhbcgcbacbaM
Shannon decomposition. Only 2-to-1 muxes.
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William Sandqvist [email protected]
8.7d
1)1()(
0)()0(
)()(
⋅+⋅=++=++=++=+=
⋅+⋅=+=
+==++=
bcbcbcbbcbcbcbbbcbh
cbbcbbg
cbhbcgcbacbaM
Shannon decomposition. Only 2-to-1 muxes.
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William Sandqvist [email protected]
8.7d
1)1()(
0)()0(
)()(
⋅+⋅=++=++=++=+=
⋅+⋅=+=
+==++=
bcbcbcbbcbcbcbbbcbh
cbbcbbg
cbhbcgcbacbaM
Shannon decomposition. Only 2-to-1 muxes.
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William Sandqvist [email protected]
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BV 6.5
William Sandqvist [email protected]
For the function
use Shannon’s expansion to derive an implementation using a 2-to-1 multiplexer and any necessary gates.
)6,3,2,0(),,( 321 ∑= mwwwf
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BV 6.5
William Sandqvist [email protected]
For the function
use Shannon’s expansion to derive an implementation using a 2-to-1 multiplexer and any necessary gates.
)6,3,2,0(),,( 321 ∑= mwwwf
)()(
)()(
)110,011,010,000(),,(
321321
3213232321
321321321321
321
wwwwww
wwwwwwwwww
wwwwwwwwwwww
mwwwf
++=
=+++=
=+++=
==∑
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BV 6.5
William Sandqvist [email protected]
For the function
use Shannon’s expansion to derive an implementation using a 2-to-1 multiplexer and any necessary gates.
)6,3,2,0(),,( 321 ∑= mwwwf
)()(
)()(
)110,011,010,000(),,(
321321
3213232321
321321321321
321
wwwwww
wwwwwwwwww
wwwwwwwwwwww
mwwwf
++=
=+++=
=+++=
==∑
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BV 6.5
William Sandqvist [email protected]
For the function
use Shannon’s expansion to derive an implementation using a 2-to-1 multiplexer and any necessary gates.
)6,3,2,0(),,( 321 ∑= mwwwf
)()(
)()(
)110,011,010,000(),,(
321321
3213232321
321321321321
321
wwwwww
wwwwwwwwww
wwwwwwwwwwww
mwwwf
++=
=+++=
=+++=
==∑
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William Sandqvist [email protected]
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William Sandqvist [email protected]
(Ex 8.9)
Show how one four-input exorgate (XOR, odd parity function) is realized in an FPGA circuit. Show the contents of the SRAM cells ( LUT, Lookup Table )
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William Sandqvist [email protected]
(Ex 8.8)
Set up full adder truth table. Show how a full adder is implemented in an FPGA chip. Logic elements of an FPGA is able to cascade COUT and CIN between "neighbors." Show the contents of the SRAM cells ( LUT, Lookup Table ).
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William Sandqvist [email protected]
(BV ex 6.31) In digital systems it is often necessary to have circuits that can shift the bits of a vector one or more bit positions to the left or right. Design a circuit that can shift a four-bit vector W = w3w2w1w0 one bit position to the right when a control signal Shift is equal to 1. Let the outputs of the circuit be a four-bit vector Y = y3y2y1y0 and a signal k, such that if Shift = 1 then y3 = 0, y2 = w3, y1 = w2, y0 = w1, and k = w0. If Shift = 0 then Y = W and k = 0.
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William Sandqvist [email protected]
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William Sandqvist [email protected]
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William Sandqvist [email protected]
BV ex. 6.32 Barrel shifter
The shifter in Example 6.31 shifts the bits of an input vector by one bit position to the right. It fills the vacated bit on the left side with 0. If the bits that are shifted out are placed into the vacated position on the left, then the circuit effectively rotates the bits of the input vector by a specified number of bit positions. Such a circuit is called a barrel shifter. Design a four-bit barrel shifter that rotates the bits by 0, 1, 2, or 3 bit positions as determined by the valuation of two control signals s1 and s0.
A barrelshifter is used to speed up floating point operations.
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William Sandqvist [email protected]
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= Lowcost FPGA
William Sandqvist [email protected]
Key Benefits • Lowest FPGA unit cost starting at $0.49 • Ultra-low power in Flash*Freeze mode, as low as 2 µW • Nonvolatile FPGA eliminates unnecessary parts from BOM • Single-chip and ultra-low-power products simplify board design • Variety of cost-optimized packages reduce assembly costs • Low-power FPGAs reduce thermal management and cooling needs
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William Sandqvist [email protected]
BV 6.16
Actel Corporation manufactures an FPGA family called Act 1, which uses multiplexer based logic blocks. Show how the function can be implemented using only ACT 1 logic blocks.
323132 wwwwwwf ++=
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William Sandqvist [email protected]
BV 6.16 323132 wwwwwwf ++=
( ) ( )( ) ( )
( )1223223
122312123
21212322213213
22323
21323
1)10(
1)1(
)()(
)10()(
)()(
wwwwwwwf
wwwwwwwww
wwwwwwwwwwwwww
wwwww
wwwwwf
⋅+⋅+⋅+⋅=
⋅+⋅=++=
=++=++=+
⋅+⋅=
++=
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William Sandqvist [email protected]
BV 6.16 323132 wwwwwwf ++=
( ) ( )( ) ( )
( )1223223
122312123
21212322213213
22323
21323
1)10(
1)1(
)()(
)10()(
)()(
wwwwwwwf
wwwwwwwww
wwwwwwwwwwwwww
wwwww
wwwwwf
⋅+⋅+⋅+⋅=
⋅+⋅=++=
=++=++=+
⋅+⋅=
++=
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William Sandqvist [email protected]
BV 6.16 323132 wwwwwwf ++=
( ) ( )( ) ( )
( )1223223
122312123
21212322213213
22323
21323
1)10(
1)1(
)()(
)10()(
)()(
wwwwwwwf
wwwwwwwww
wwwwwwwwwwwwww
wwwww
wwwwwf
⋅+⋅+⋅+⋅=
⋅+⋅=++=
=++=++=+
⋅+⋅=
++=
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William Sandqvist [email protected]
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William Sandqvist [email protected]
VHDL BV 2.51a Write VHDL code to describe the following functions
)()()( 432421312
41214332311
xxxxxxxxf
xxxxxxxxxxf
++⋅++⋅+=
++++=
VHDL code is written with a text editor and saved in a file with the extension.vhd. The code always consists of two sections ENTITY and ARCHITECTURE. Entity is a description of how the circuit "looks from the outside" (the interface), and Architecture how it "looks like inside."
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William Sandqvist [email protected]
VHDL BV 2.51a
)()()( 432421312
41214332311
xxxxxxxxf
xxxxxxxxxxf
++⋅++⋅+=
++++=
Comments begin with –- If you wish, you can "draw" clarification ASCII graphics in the comment lines..
-- ___________ -- | | -- | Functions | -- ->-| x1 | -- ->-| x2 f1 |->- -- ->-| x3 f2 |->- -- ->-| x4 | -- |___________| --
Program code is written with a text editor. So we can only do text comments to the code. A fixed-width font is used ( eg. Courier New ).
One usually indent text blocks that belong together for greater clarity.
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William Sandqvist [email protected]
VHDL BV 2.51a
)()()( 432421312
41214332311
xxxxxxxxf
xxxxxxxxxxf
++⋅++⋅+=
++++=
ENTITY Functions IS PORT(x1, x2, x3, x4 :IN STD_LOGIC; f1, f2, :OUT STD_LOGIC ) END Functions ARCHITECTURE LogicFunc OF Functions IS BEGIN f1 <= (x1 AND NOT x3)OR(x2 AND NOT x3)OR (NOT x3 AND NOT x4)OR(x1 AND x2)OR (x1 AND NOT x4); f2 <= (x1 OR NOT x3)AND(x1 OR x2 OR NOT x4)AND (x2 OR NOT x3 OR NOT x4); END LogicFunc ;
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VHDL BV 6.21
William Sandqvist [email protected]
Using a selected signal assignement, write VHDL code for a 4-to-2 binary encoder. Only one of w0 …w3 is ”1” at a time. LIBRARY ieee; USE IEEE.std_logic_1164.all; ENTITY ENCODER IS PORT( w :IN STD_LOGIC_VECTOR( 3 DOWNTO 0 ) ; y :OUT STD_LOGIC_VECTOR( 1 DOWNTO 0 ) ); END ENCODER ARCHITECTURE Behavior OF ENCODER IS BEGIN WITH w SELECT y <= ”00” WHEN ”0001”, ”01” WHEN ”0010”, ”10” WHEN ”0100”, ”11” WHEN OTHERS; END Behavior ;
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William Sandqvist [email protected]
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Y
- -
- -
1 0 0 0
0
0 0 1
1 1 1 1
0233010102 xxxxxxxxxxY +++=
023 xxx
301 xxx
01xx
02 xx
Y
William Sandqvist [email protected]
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Y
- -
- -
1 0 0 0
0
0 0 1
1 1 1 1
x0 x1
0
1
0 1
3 2 (0,0)x x ⇒
x0 x1
0
1
0 1
3 2 (0,1)x x ⇒
x0 x1
0
1
0 1
3 2 (1,1)x x ⇒
x0 x1
0
1
0 1
3 2 (1,0)x x ⇒
Y
William Sandqvist [email protected]
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Y
- -
- -
1 0 0 0
0
0 0 1
1 1 1 1 - -
1 0
x0 x1
0
1
0 1
3 2 (0,0)x x ⇒
0 1 0 1
x0 x1
0
1
0 1
3 2 (0,1)x x ⇒
0 1 1 0
x0 x1
0
1
0 1
3 2 (1,1)x x ⇒
- - 1 0
x0 x1
0
1
0 1
3 2 (1,0)x x ⇒
Y
William Sandqvist [email protected]
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Y
- -
- -
1 0 0 0
0
0 0 1
1 1 1 1
0233010102 xxxxxxxxxxY +++=
- - 1 0
x0 x1
0
1
0 1
0
23 )0,0(
xY
xx
=
⇒
0 1 0 1
x0 x1
0
1
0 1
0
23 )1,0(xY
xx=
⇒
0 1 1 0
x0 x1
0
1
0 1
01
23 )1,1(xxY
xx⊕=⇒
- - 1 0
x0 x1
0
1
0 1
0
23 )0,1(
xY
xx
=
⇒
Y
0x0x0x
01 xx ⊕
William Sandqvist [email protected]
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Y
- -
- -
1 0 0 0
0
0 0 1
1 1 1 1
0233010102 xxxxxxxxxxY +++=
- - 1 0
x0 x1
0
1
0 1
3 2
1 0
(0,0)x xY x x
⇒= ⊕
0 1 0 1
x0 x1
0
1
0 1
0
23 )1,0(xY
xx=
⇒
0 1 1 0
x0 x1
0
1
0 1
01
23 )1,1(xxY
xx⊕=⇒
- - 1 0
x0 x1
0
1
0 1
3 2
1 0
(1,0)x xY x x
⇒= ⊕
Y 0x
01 xx ⊕
01 xx ⊕
01 xx ⊕
William Sandqvist [email protected]
Or …
Or if you don’t have acess to the variable x0 inverted …
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William Sandqvist [email protected]