SH-2A CPU Core Part 1 - Renesas e-Learning course provides an overview of the SH-2A 32-bit RISC CPU...

1© 2008, Renesas Technology America, Inc., All Rights Reserved

Course Introduction

� Purpose:

� This course provides an overview of the SH-2A 32-bit RISC CPU core built intonewer microcontrollers in the popular SH-2 series

� Objectives:

� Gain a basic overview of the SH-2A CPU architecture

� Understand key features of this powerful 32-bit RISC CPU

� Learn about the internal CPU registers

� Acquire knowledge about the CPU’s addressing modes

� Explore the SH-2A instruction set, including the new instructions added to thoseof the SH-2 set

� Content:� 15 pages� 3 questions

� Learning Time:� 35 minutes


Overview of SH-2A CPU Core

� GeneralSH-2A: The 32-bit RISC CPU for newer SH-2 series Renesasmicrocontrollers that . . .

� Is a member of the SuperH® family

� Powers the SH7206 device and others

� Operates at clock speeds up to 200MHz

� Executes up to two instructions per cycle

– Delivers up to 360 MIPS performance

� Software� Has RISC-type instruction set and addressing modes

– Is based on “C”

– Includes delayed branch instructions

� Includes 16-bit fixed-length basic instructions for high code density

� Is upwardly software compatible with SH-1/SH-2 CPUs at object-code level.

� Adds 32-bit instructions for high performance

� Incorporates new bit-manipulation instructions


SH-2A CPU Overview

�Hardware� Has a superscalar and Harvard architecture

� Executes two instructions/cycle

� Is a load-store design

� Has a five-stage pipeline

� Includes 16 general-purpose 32-bit registers

� Uses register banks for fast interrupt response

� Has built-in hardware multiplier-accumulate unit (MAC) for DSP-type operations

� Provides a 4GB address space

� Offers an optional FPU: SH2A-FPU core

5-stage Pipeline(*Two instructions are fetched and executed

simultaneously)

SystemRegisters

Clock

HardwareMultiplier

GeneralRegisters

ControlRegisters

RegisterBanks

SH-2A CPU

Superscalar* RISC Design

CPU Instruction Fetch Bus

CPU Data Fetch Bus

On-chipCache

FPU(SH2A-FPU only)

�Support� Is supported by a comprehensive set of Renesas software and hardware tools

� Is also supported by many products and services from a large

community of vendors


SH-2A CPU Model

R0

R1

R2

R3

R4

R5

R6

R7

R8

R9

R10

R11

R12

R13

R14

R15

031- - - - - - - - - - - - - - - - - BO CS - - -M Q I[3:0] - - S T

031

Status Register (SR)

GBR031

Global Base Register (GBR)

VBR031

Vector Base Register (VBR)

TBR031

Jump Table Base Register (TBR)

MACH031

Multiply and accumulate registers

MACL

PR

Procedure Register (PR)

PC

Program Counter (PC)

031

031

© 2008, Renesas Technology America, Inc., All Rights Reserved

Load-Store Architecture

�Arithmetic instructions have operands in theregister

� A generous register set is required and provided

� Operands must be loaded from memory

� Execution time is very fast andpredictable.

� Local arithmetic execution time isindependent of data path

�Standard data length is 32 bits(longword)

�Any 8- or 16-bit data is sign-extended forarithmetic operations, or zero-extended forlogic operations

OperatedUpon

Memory

Register

PROPERTIES

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Immediate Data

� Byte immediate data is stored in instruction code

�Word or longword immediate data is located in memory tables (literal pool) accessed via a PC-relative addressing mode MOV instruction

� SH-2A CPU allows 17- to 28-bit immediate data to be stored in the instruction code

� For 21- to 28-bit data, an OR or AND instruction must be executed after the transfer instruction


Addressing modes define how/where to find operands

SH-2A: A Single-Address Machine

�Because the SH-2A is a SINGLE-ADDRESS machine . . .

� At least one operand is always stored in a register

� The other operand is defined by the addressing mode

� The addressing mode defines the Effective Address (EffA) calculation

Exception: MAC @Rm+,@Rn+

Example: Store contents of register R1 in memory;

address of memory is in R2

• MOV.L R1,@R2

- Source operand is general register R1

- Destination is memory; address is in R2

(Addressing mode: Register indirect)


Addressing Modes

� Register direct: Rn

� Register indirect: @Rn

� Register indirect with post-increment: @Rn+

� Register indirect with pre-decrement: @-Rn

� Register indirect with displacement: @(dd:4,Rn)

@(dd:12,Rn)

� Indexed register indirect: @(R0,Rn)

� GBR indirect with displacement: @(dd:8,GBR)

� Indexed GBR indirect: @(R0,GBR)

� TBR duplicate indirect with displacement @@(dd:8,TBR)

� PC indirect with displacement: @(disp:8,PC)

� PC relative disp:8

disp:12

Rn

� Immediate: #imm:20

#imm:8

#imm:3

Used by standard arithmetic

& logic operations

Used for array handling &

popping values from stackUsed to push values onto

the stackGreat for accessing C/C++

structure contents

Efficient calling of functions

via a function pointer tableUsed to access 16-bit and

32-bit constant data from

memory tables/literal poolsFacilitates far branching to

anywhere in address space

20-bit immediate data can be

held in a 32-bit instruction8-bit and 3-bit (bit

instructions) data can be

held in 16-bit instructions


New Instructions - Part 1

� Immediate data transfers

� MOVI20, MOVI20S– MOVI20 transfers 20-bit immediate data to a register

– MOVI20S instruction enables the generation of a 28-bit address, making it possible to specify on-chip addresses up to 256MB

�Structure-access instructions using 12-bit displacement

� e.g., MOV.B/W/L Rm@(disp:12,Rn)

�Bit-manipulation instructions operating on memory and general registers

� e.g., BAND.B #imm:3, @(disp:12, Rn),

� BCLR.B #imm:3, Rn



�Multiplication result instruction

� MULR R0, Rn

� Store the lower 32-bits of a 32x32-bit multiply in Rn

�Batch division of 32-bit signed and unsigned data

� DIVS, DIVU

�Saturation value comparison instructions

� CLIPS, CLIPU

�Barrel shift instructions

� SHAD, SHLD

�Multiple register save/restore instructions

� MOVML, MOVMU



�T-bit inversion and transfer instructions

� E.g. MOVRT, NOTT

�Register banking instructions

� RESBANK, STBANK, LDBANK

�Reverse stack transfer instructions

� MOV.B/W/L R0, @Rn+

� MOV.B/W/L @-Rn, R0

�Unconditional branch instructions with no delay slot

� JSR/N, RTS/N

�Cache prefetch instruction

� PREF

PROPERTIES



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Features of Instruction Set

Types of Operations:

� Data transfer

� Arithmetic

� Logic

� Shift / Rotate

� System control

� Program flow control

� Bit manipulation

� Floating point

MOV.B @(3,R15),R0

EXTU.B R0,R0

MOV.L L278+14,R3

ADD R0,R3

MOV.B @(3,R15),R0

EXTU.B R0,R0

MOV.L L278+22,R1

MOV.B @(R0,R1),R2

MOV.B R2,@R3

MOV.B @(3,R15),R0

ADD #1,R0

MOV.B R0,@(3,R15)

MOV.B @(3,R15),R0

EXTU.B R0,R0

MOV #6,R3

CMP/GT R3,R0

BF L268


Data Transfer Instruction: Move

�MOV: General move to / from registers;

� byte, word and longword operand

� No modification of status register (in contrast to H8 series)

� Immediate 8-bit: MOV.B #value:8,Rn

� Immediate 20-bit: MOVI20 #value:20,Rn

� Immediate 16-bit: MOV.W @(displ:8,PC),Rn

� address: displ*2 + PC

� Immediate 32-bit: MOV.L @(displ:8,PC),Rn

� address: displ*4 + PC

In

Literal Pools

R0

R1

R2

R3

R4

R5

R6

R7

R8

R9

R10

R11

R12

R13

R14

R15

31 0

(SP)

Memory

or I/O

In Instruction


Arithmetic/Logic Instructions

�ADD, SUB

�Compare: CMP

�Divide support: DIV

�Multiply Rn * Rm MUL

�Multiply @Rn * @Rm MAC

�Negate: NEG

�AND, OR, TST, XOR

� Addressing modes for AND, OR, TST, XOR:

– AND Rm,Rn, AND #dd:8,Rn, AND #dd:8,@(R0,GBR)

�TAS:

� TAS.B @Rn ;"test and set" operates on byte and T-bit

�NOT:

� NOT Rm,Rn ; ~Rm Rn


Shift/Rotate Instructions

�Shift / rotate one bit

�Shift / rotate one bit with T-bit

�Barrel shift

�Shift n bit(s), n=2, 8, 16

� n=2: x4 or /4

� n=8: shift by one byte (or x256, /256)

� n=16: shift by one word (or x65536, /65536)

>>

<<Note: These instructions are only suitable

for unsigned arithmetic!


System Control Instructions

�Set/clear T-bit: SETT, CLRT

�MAC clear: CLRMAC

� Load/Store system registers (SR, GBR, VBR): LDS, STS

� Copy contents of system register to/from

any general-purpose register or memory,

using @-Rn/@Rn+ addressing (stack compatible)

� Load/Store control registers (MAC, PR): LDC, STC

� Copy contents of control registers to/from

any general-purpose register or memory,

using @-Rn/@Rn+ addressing (stack compatible)

�Sleep (either standby or sleep)

�Return from exception: RTE

�Save and restore register bank

�TRAPA


Program Flow Instructions

�Conditional & unconditional delayed branches (same as SH-2 CPU)

�Conditional branch coding and handling sequence:

� T-bit handling with COMPARE instruction

� Result of condition is tested in T-bit

� Then branch conditional

�Unconditional branch with no delay slot (added instruction)

�A subroutine call instruction causes the hardware to:

� Copy PC contents in PR

� Put new value into PC

� Go to next instruction

�A return from subroutine instruction causes the hardware to:

� Copy PR contents in PC

� Go to next instruction

�Exception handling


Bit Manipulation Instructions

� Logical

� AND, OR, XOR, NOT-AND, NOT-OR

� Bit set

� Bit clear

� Bit store

� Bit load

� Bit NOT load


Boosts program execution speed and reduces code size!

Subroutine Calls

� Instructions: BSR, JSR, RTS

�Hardware support for single-level

subroutine calls

�Multiple-level calls require support:

"PUSH" and "POP" of previous PC under

software control

Sequence:

�Enter subroutine (BSR/JSR):

�Hardware: Copy PC to PR

� Load new value to PC

� (Software: Push PR to stack)

�Execute next instruction

� ...code...

�Exit subroutine:

� (Software: Pop PR from stack)

�Hardware: RTS instruction

�Copy PR to PC

�Continue

PR

Procedure Register

Program Counter = One-level-deep buffer!

PC

PROPERTIES



Allow user to leave quiz: After user has completed quiz

User may view slides after quiz: At any time



Course Summary

� Overview of SH-2A RISC CPU features, architecture

� Internal CPU registers

� Addressing modes

� Instruction set

SH-2A CPU Core Part 1 - Renesas e-Learning course provides an overview of the SH-2A 32-bit RISC CPU...

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