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Abstract—The design of single flux-quantum (SFQ) circuits

requires well-defined inductances. In many cases these are created by irregular geometries and a computer aided design tool is necessary for inductance calculations. This becomes a challenging task in cases where no ground plane is used and thus three-dimensional calculations are required. For this purpose, InductEx was developed and verified successfully for simple structures. In this work we take the next step and demonstrate the applicability of InductEx to the design of Rapid Single Flux-Quantum (RSFQ) cells. We use InductEx for inductance modeling as an integral part of the design cycle for an RSFQ cell with flux quantum transfer via mutual inductance and for a DC-reprogrammable logic circuit with similar inductive coupling. The relation between coupling factor and self-inductance is optimized in the circuit layout. All coupling structures are duplicated in SQUID modulation test circuits to measure and verify calculation accuracy. We find excellent agreement between the calculated and measured inductance values. Furthermore, the operational area of the basic cell is determined and compared with similar investigations reported earlier. Based on this comparison we conclude that InductEx is a valuable inductance design tool, and that mutual coupling in structures using ground plane holes and RSFQ-compatible self-inductances can be modeled and designed reliably.

Index Terms—Current recycling, dc-reprogrammable logic, ground plane holes, inductance calculations, InductEx, inductive coupling, layout extraction, low-power RSFQ, LR-biasing, serial biasing.

I. INTRODUCTION

APID Single Flux Quantum (RSFQ) circuits (and SFQ circuits in general) are composed of three elemental

building blocks: resistors, Josephson junctions and inductances [1]. For physical layout, the resistors and junctions are implemented as regular simple structures, resulting in linear or quadratic relations respectively between their dimensions and realized values.

The inductances are in many cases defined by microstrip line configurations and perform two tasks in an RSFQ circuit:

Manuscript received October 9, 2012. This work was supported in part by

the South African National Research Foundation, grant numbers 69006 and 78789.

C. J. Fourie is with Stellenbosch University, Stellenbosch, South Africa (phone: +2721 808-4029; fax: +2721 808 4981; e-mail: coenrad@sun.ac.za).

O. Wetzstein, J. Kunert and H.-G. Meyer are with the Institute of Photonic Technology, Jena, Germany (e-mail: juergen.kunert@ipht-jena.de).

they realize electrical connections and galvanic coupling between circuit parts and define the functionality of circuit sections (storing or propagating flux quanta). Due to long or sometimes very short distances between circuit nodes, inductances in many cases have no regular layout geometries and need to be designed carefully to implement the desired storing behavior of a loop. Therefore inductance calculation is important for the design of RSFQ circuits.

Calculation accuracy, calculation time and the integration of a tool into the design flow are important aspects for efficient circuit design. For two-dimensional (2D) inductance extraction, Lmeter [2] is fast and sufficiently accurate, and is mostly used. However, in cases where three-dimensional (3D) inductance extraction is required, an adequate tool (especially in terms of design flow integration) was not available. To address this, InductEx [3] was developed to provide a user-friendly interface to FastHenry [4] (itself modified to handle multi-terminal superconductive structures [5]). Firstly we analyzed the accuracy of InductEx for extraction of 2D circuit inductances [3]. Next the applicability of InductEx to simple 3D problems was analyzed through the investigation of lines crossing ground plane holes [6], and its accuracy was again confirmed.

In this work we take the next step and demonstrate the applicability of InductEx to the design of RSFQ basic cells with advanced 3D inductance layouts. When RSFQ circuits contain magnetically coupled components (through mutual inductance), a ground plane is necessary to realize low self inductances. However, a ground plane severely limits the coupling factor. If a high coupling factor (k > 0.5) is required, strategically placed ground plane holes can be used to improve mutual inductance, and inductance extraction then requires a 3D tool. Here we demonstrate through two examples – an inductive pulse transfer (TX) cell and a DC-resettable latch (DCRL) – that InductEx has the required abilities to design such circuits successfully. We used LASI [7] and LayoutEditor [8] (with macro support for InductEx) for circuit layouts discussed here. Layouts are sent to InductEx in GDSII format. Detail on InductEx modeling procedures and integration with CAD tools is available in the user’s manual [9].

II. INDUCTIVE COUPLING IN RSFQ CELLS

Power dissipation in single-flux-quantum (SFQ) circuits is an important design issue for large systems, hence the

SFQ Circuits with Ground Plane Hole-Assisted Inductive Coupling Designed with InductEx

Coenrad J. Fourie, Member, IEEE, Olaf Wetzstein, Juergen Kunert, and Hans-Georg Meyer

R

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development of low power SFQ circuits [10] that reduce [11]-[13] or completely eliminate static power dissipation [14], [15]. However, even low power circuits are biased with about 1 mA of current per logic gate. This causes large currents and associated magnetic fields in complex circuits, which degrades performance [16].

One technique with which to lower the total bias current supplied to a circuit is current recycling [17]-[21]. For a recent implementation of current recycling through inductive coupling [22], a thorough analysis of layout for optimal coupling was done. Using InductEx as a more accurate inductance calculation method shown to be accurate for ground plane holes [6], we designed an inductively coupled transmission cell for optimum coupling in the RSFQ niobium process from IPHT Jena [23].

We also designed a DC-resettable latch (DCRL) for the use in reprogrammable circuits [24]. The DCRL functions as a non-destructive readout D Flip-Flop or controlled SFQ stop/pass switch programmed with an SFQ input and reset with an inductively coupled DC current. The DC reset functionality allows all DCRLs in a circuit or block to be erased with on threaded reset current from an off-chip source or an on-chip HUFFLE [25], [26]. To reduce the current driving requirements of the HUFFLE, the DC reset line

coupling to L2b of the DCRL should be as strong as possible. Finally, to verify the accuracy of the calculated inductance

and coupling in these layouts, we manufactured SQUID test structures with which to measure the inductance of similar coupling structures (through SQUID modulation [27]) for comparison to calculations.

III. CIRCUIT DESIGN

A. TX cell

An inductively coupled transmission cell (TX cell) was designed according to that presented by Johnson et al. [17] to inject an incoming single flux quantum (SFQ) pulse into a resistively terminated transformer. The circuit schematic diagram is shown in Fig. 1, with L4 as the primary inductance of the transformer and L5 the secondary inductance. As with other published transmission cells [18], [19], [22], the receiver side of the TX cell is triggered asynchronously by the driver side, and is therefore not clocked.

B. DCRL

The DC-Resettable Latch is a key component of a proposed superconductive programmable gate array [24], and was presented (with simulated response) earlier [28]. The DCRL was redesigned and optimized for the niobium RSFQ process of IPHT, and the schematic circuit diagram is shown in Fig. 2. The dc reset current is 790 A, and simulated bias margins at 10 GHz are listed in Table 1. Coupling between the dc reset line and the storage inductor L2b was strengthened through the use of a ground plane hole, as described below.

IV. INDUCTANCE DESIGN AND LAYOUT

A. TX Cell

Careful design of the coupling between inductors L4 and L5 is necessary to keep self-inductance low for both inductors, while maximizing the mutual inductance.

Johnson et al. [17] used a ground plane tongue, extending over a ground plane moat that isolates the driver and receiver sections, to minimize self-inductance. Mutual inductance was improved with a ground plane hole underneath the transformer. A detailed analysis of different techniques by Igarashi et al. [22] confirmed that the former is by far the most effective.

Due to differences between manufacturing processes, the layout described above is not exactly reproducible in the RSFQ niobium process of IPHT. We designed a layout that preserves low inductance for both L4 and L5, while allowing

Setin

Readout

J1

J2 J3

J8 J9

Ib1

Ib3

L1

L2a L5

k

L10 L11 L12

L3 L4

Readin

J5

L6

J6Ib2

L7 L8 L9

L2b

L13

J4J7

Resetout

Reset+Reset-

Fig. 2. Schematic circuit diagram of DCRL cell. Circuit parameters are:Inductances: L1: 2.2 pH, L2a: 0.64 pH, L2b: 6.2 pH, L3/L4: 2 pH, L5: 1.2 pH, L6: 2.1 pH, L7: 1.6 pH, L8: 1.4 pH, L9: 3.2 pH, L10: 2.5 pH, L11: 1.5 pH, L12: 1.3 pH, L13: 17.5 pH. Coupling: k: 0.43. Critical currents: J1: 175 A, J2/J5/J9: 250 A, J3: 325 A, J4: 125 A, J6: 350 A, J7/J8: 150 A. Bias currents: Ib1: 260 A, Ib2: 375 A, Ib3: 300 A.

TABLE I SIMULATED DC BIAS MARGINS FOR DCRL

DC Bias current Simulated DC bias margins at 10 GHz

Ib1 -28 % to +41 % Ib2 -57 % to +61 % Ib3 -23 % to +21 %

Ireset -24 % to +33 %

TXin

RXout

J1 J2 J3

J4 J5

Ib1 Ib2

Ib3

L1 L2 L3

L4 L5

k

R1

L6 L7 L8Ground plane hole

Separate, isolated ground planesFig. 1. Schematic circuit diagram of inductive pulse transfer cell. Circuitparamaters are: Inductances: L1/L2/L3/L8: 2 pH, L4: 24.5 pH, L5: 15.0 pH, L6: 1.9 pH, L7: 3 pH. Coupling: k: 0.57. Critical currents: J1/J2: 250 A, J3: 175 A, J4: 200 A, J5: 225 A. Bias currents: Ib1: 350 A, Ib2: 152 A, Ib3: 330 A. Resistance: R1: 1 . Junctions J3 and J4 are underdamped.

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strong coupling over a ground plane hole. The layout is shown schematically in Fig. 3(a), with a cross-section detailing the use of a ground plane tongue in the second wiring layer (M2) shown in Fig. 3(b). The ground plane tongue (that brings the driver side ground plane over to the receiver section) is not continuously seamed on the driver side the way that Igarashi et al. do it, but only connected through two vias as shown in Fig. 3(a) to conserve layout space. A microphotograph of the manufactured circuit is shown in Fig. 4.

B. DCRL

Due to differences between the RSFQ niobium processes of IPHT and Hypres, the DCRL layout in [28] cannot be exactly duplicated in the IPHT process. We used a small ground plane hole (see the microphotograph of the manufactured circuit in Fig. 5) to strengthen coupling while keeping the inductance of L2b low. With InductEx [3], the mutual inductance is calculated as 4.5 pH (an improvement over the 3.9 pH in the older layout [28]).

V. RESULTS

A. Inductance tests

The segmented InductEx calculation model for the full TX

cell is shown in Fig. 6. For a detailed explanation of InductEx’s segmentation algorithm, see [3], [29]. We used a maximum segment size of 2.5 m for all calculation models. SQUID test structures were also manufactured to verify the inductance modeling and calculation method. However, the SQUIDs have bias lines, which in the case of the TX cell transformer intrudes over the ground plane hole, and in the case of the small hole of the DCRL’s transformer required us to use two equal ground plane holes on both sides of the bias line for symmetry. The SQUID results therefore do not directly reflect the inductances in the TX cell and DCRL, but are only used to verify the calculation method (InductEx

M2

J2via

via

J3

J4

Ib2

Ground (left)

Ground (left)

Ground (right)

M2M1M0

L5

L4

A A

M1

Groundplane hole

Ground (left)Ground (right)

M0(ground plane removed)

R1

(a) (b)

L5 (in M2)

L4 (in M1)

Fig. 3. (a) Schematic of TX cell coupling layout, with ground plane holeshashed, and (b) cross-section through A-A with ground plane now shown positively.

Ground plane (left)

Ground plane (right)

M0M1 M2

Ground plane slit

Ground plane holeto enhance coupling

J1

J2 J3

J4 J5

Fig. 6. InductEx model of complete TX cell layout, showing isolated ground planes and ground plane hole in M0 and the ground plane tongue in M2. The vertical dimension is enlarged 5 times for clarity. The model has 21,000 filaments and solves in 10 minutes using one core on an Intel Core i5 processor.

Fig. 4. A microphotograph of the TX cell.

Fig. 5. A microphotograph of the DCRL.

Fig. 7. Microphotographs of the SQUID structures for inductance tests. (a) Inductance test structure for the TX cell and (b) symmetrical inductance test structure to measure effect of a small hole as used in the DCRL.

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models were also constructed for the SQUID test structures). Microphotographs of the SQUID test structures are shown in Fig. 7.

In order to compensate for fabrication tolerances, the process parameters used for InductEx calculations were calibrated through measurements and calculations on a set of test structures included on the wafer, as discussed earlier [3], [6], and in far more detail recently [30].

The SQUID calculation and measurement results are shown in Table 2, with the TX cell SQUID measuring the equivalent of L5, and the DCRL SQUID measuring an equivalent of L2b with two ground plane holes for symmetry. The results agree

very well, and we obtain a very good ratio of mutual inductance over self-inductance.

To demonstrate conclusively that the layout with a ground plane tongue and ground plane hole that does not touch the isolation moat is a good solution, we modeled layouts without the ground plane tongue and with holes of varying sizes that touch the isolation moat, as shown in Fig. 8, and analyzed these with InductEx. (These structures were not manufactured). Similar to [22], we found these layouts to be suboptimal when compared to the layout in Fig. 3, as is evident from the results in Table 3.

B. Circuit tests

Only the TX cell has been tested to date. An oscilloscope screenshot showing successful pulse transmission is shown in Fig. 9, and the measured bias current margins are listed in Table 4. The measured bias margins compare very well with the simulated margins, which is significant because the simulated critical margin (Ib2) is very narrow (and corresponds exactly to the critical margin reported by Kang et al. [18]). This demonstrates conclusively that the inductance design and verification process is reliable.

VI. CONCLUSION

We show through measurements of manufactured circuits that inductive pulse transfer circuits with hole-assisted coupling can be modeled and designed reliably with the use of InductEx (inductance, coupling factor and bias current margins of measured circuits correspond very well to the design). However, the pulse transfer circuits still have very narrow margins, so that we will investigate the addition of a double-flux-quantum (DFQ) driver [31] (as implemented by [17]) to widen the bias margins.

We also show that the TX cell coupling layout identified by Igarashi et al. as optimal [22] (and reported earlier by Johnson et al. [17]) is indeed so, and that it is possible to reproduce the coupling in the RSFQ niobium process of IPHT. However, using InductEx, we obtain a better agreement between calculated and measured inductance values (1 % to 5 %, as shown in Table 2) as well as a significantly higher ratio of mutual to self-inductance of the receiver section (0.71 to 0.75, compared to 0.63).

REFERENCES [1] K. K. Likharev and V. K. Semenov, “RSFQ Logic/Memory family: a

new Josephson-junction technology for sub-terahertz-clock-frequency digital systems,” IEEE Trans. Appl. Supercond., vol. 1, pp. 3-28, 1991.

[2] P. I. Bunyk and S. V. Rylov, “Automated calculation of mutual inductance matrices of multilayer superconductor integrated circuits,” in

TABLE IV DC BIAS MARGINS FOR INDUCTIVE PULSE TRANSFER CELL

DC Bias current Simulated DC bias margins at 10 GHz

Measured low-speed DC bias margins

Ib1 -82 % to +42 % 90% Ib2 -9 % to +11 % 5 % Ib3 -25 % to +28 % 30 %

TABLE II INDUCTANCE FOR GROUND PLANE HOLE COUPLING STRUCTURES OBTAINED

FROM MEASUREMENTS AND CALCULATION ON SQUIDS

SQUID structure Self

inductance Mutual

inductance M/L

TX cell Measureda 13.4 pH 10.1 pH 0.75 InductEx 14.0 pH 9.93 pH 0.71

DCRL Measuredb 10.6 pH 8.87 pH 0.84

InductEx 10.5 pH 8.84 pH 0.84

aTX cell measurements averaged from 4 chips over 2 wafers. bDCRL measurements averaged from 2 chips over 2 wafers.

Fig. 9. Oscilloscope screenshot showing operation of the TX cell. Channel 1is the input, channel 2 is the output from a pulse splitter before the TX cell, and channel 3 is the output of the TX cell.

M2

J2via

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J3

J4

Ib2

M2

J2via

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J3

J4

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M2

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L5 (in M2)

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M1M1M1

Ground plane slit(M0) (divides left

from right)

25 µm

30 µm27.5 µm

5 µm

(a) (b) (c)Fig. 8. Schematic of suboptimal TX cell coupling layouts with (a) groundplane hole touching ground plane divide, (b) smaller ground plane holetouching ground plane divide and (c) no ground plane hole.

TABLE III CALCULATED INDUCTANCE OF TX CELL COUPLING WITHOUT GROUND PLANE

TONGUE

Structure L4 (primary)

L5 (secondary)

M M/L5

Fig. 8(a) 45.4 pH 23.5 pH 4.72 pH 0.20 Fig. 8(b) 41.5 pH 14.2 pH 2.22 pH 0.16 Fig. 8(c) 39.9 pH 6.36 pH 0.75 pH 0.12

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