Settling Time Optimization

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 56, NO. 12, DECEMBER 2009 2569

Settling Time Optimization for Three-StageCMOS Amplifier Topologies

Andrea Pugliese, Francesco Antonio Amoroso, Gregorio Cappuccino, Senior Member, IEEE, andGiuseppe Cocorullo, Member, IEEE

Abstract—A new settling-time-oriented design methodologyfor the most common three-stage operational amplifier (op-amp)schemes reported in the literature is presented in this paper. Theproposed approach allows the systematic sizing of the compensa-tion network in order to reach the best closed-loop op-amp settlingbehavior. To demonstrate the effectiveness of the methodologyand the correctness of the analysis, the examined three-stageop-amp topologies are designed in a commercial 0.35- m CMOStechnology. Circuit simulations show that the proposed designapproach, for each investigated topology, guarantees a significantsettling time reduction with respect to the compensation networksizing strategies proposed in the past. An ad-hoc figure of merit,which evaluates the trade-off between the settling time, the loadcapacitance and the total op-amp stage transconductances, is alsodefined in order to estimate the op-amp efficiency in terms oftime-domain performances.

Index Terms—Analog design, frequency compensation, opera-tional amplifiers, transient response.

I. INTRODUCTION

T HE cascade arrangement of three amplifier stages is ex-tensively used in present-day low-voltage CMOS tech-

nologies to develop high-gain large-swing operational ampli-fiers (op-amps) [1]–[6]. To guarantee their closed-loop stability,a proper frequency compensation network is required. The sim-plest one is implemented by using two capacitors, according tothe well-established nested-Miller compensation (NMC) tech-nique. However, NMC amplifiers suffer from a significant band-width limitation [7].

To improve frequency response performances of three-stageop-amps, more complicated NMC-based schemes have beendeveloped. In many of these topologies, gain-bandwidth(GBW) enhancements are obtained by introducing resistors[7]–[11], feedforward transconductance stages [12]–[16],damping-factor control stages [17], active-feedback stages[18]–[21], or AC boosting amplifiers [22] in the compensa-tion network. A coherent comparative analysis of differentconfigurations is useful to decide on the most suitable com-pensation topology for a given application. A figure of meritwhich evaluates the tradeoff between the GBW product, theload capacitance and the total stage transconductances was

Manuscript received July 24, 2008; revised January 02, 2009. First publishedMarch 10, 2009; current version published December 11, 2009. This paper wasrecommended by Associate Editor G. Banerjee.

The authors are with the Department of Electronics, Computer Scienceand Systems, University of Calabria, 87036 Rende (CS), Italy (e-mail:[email protected]; [email protected]; [email protected]; [email protected]).

Digital Object Identifier 10.1109/TCSI.2009.2017133

recently presented in [5] to compare the performance of themost common three-stage op-amp schemes. Design rules toarbitrarily choose the phase margin were also proposed in [5],overcoming the limitation of classic criteria [12], which forcea setting of 60 for the phase margin in order to achieve themaximally flat Butterworth closed-loop frequency response.In a whole class of applications such as switched-capacitorcircuits and analog-to-digital converters (ADCs), the op-ampsettling behavior optimization is needed to reach the desiredamplifier speed performances [23], [24], and limit the powerconsumption. Unfortunately, because of the high-order settlingbehavior of three-stage amplifiers, the relationship betweenthe time response and the op-amp open-loop parameters is notstraightforward [25].

As a consequence, the phase margin which guarantees an op-timal time response cannot be easily deduced. Thus, advancedad-hoc closed-loop time-domain-oriented approaches have tobe developed. A systematic settling time optimization strategybased on a closed-loop analysis was recently presented in [25]for NMC amplifiers. It allows the minimum settling time (MST)response to be obtained for a given power consumption budgetby optimizing the compensation network sizing. Approaches toachieve the MST response for other NMC-based schemes arenot available in existing literature.

Settling-time-oriented design methodologies for the mostused three-stage topologies are proposed in this paper. First,the closed-loop transfer functions of NMC, NMC with feedfor-ward Gm stage (NMCF), nested Gm-C compensation (NGCC),NMC with nulling resistor (NMCNR), NMCF with nullingresistor (NMCFNR), active-feedback frequency compensation(AFFC), multipath NMC (MNMC), AC boosting compensa-tion (ACBC), damping-factor control frequency compensation(DFCFC), dual-loop parallel compensation (DLPC), transcon-ductance with capacitances feedback compensation (TCFC)and double pole–zero cancellation (DPZC) schemes are sum-marized in Section II. A generic strategy to cope with thesettling time minimization for these topologies is developed inSection III. In Section IV, design rules for the compensationnetwork optimization are then defined and a new figure of meritis also introduced to perform a systematic comparison of timeresponse performances of all the schemes under examination.

To prove the effectiveness of the proposed approach, the de-signs of three-stage amplifiers are reported in Section V. Finally,the conclusions are presented in Section VI.

II. TRANSFER FUNCTIONS OF THREE-STAGE TOPOLOGIES

The block diagrams of the three-stage topologies under ex-amination are reported in Fig. 1. The th gain stage is modeled

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2570 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 56, NO. 12, DECEMBER 2009

Fig. 1. Block diagrams of the different three-stage amplifier topologies: (a) Nested Miller compensation (NMC) �� and NMC with nulling resistor(NMCNR). (b) Nested Gm-C compensation (NGCC). (c) NMC with feedforward ��stage (NMCF) �� and NMCF with nulling resistor (NMCFNR). (d)Active-feedback frequency compensation (AFFC). (e) Damping-factor control frequency compensation (DFCFC). (f) dual-loop parallel compensation (DLPC). (g)Multi-path NMC (MNMC). (h) AC boosting compensation (ACBC). (i) Transconductance with capacitances feedback compensation (TCFC). (j) Double pole–zerocancellation (DPZC).

as a transconductance amplifier whose transconductance, outputresistance and output capacitance are and , respec-tively. The load and the compensation capacitances are denotedas and , respectively. and indicate the th“nulling” resistance and feed-forward stage transconductance,respectively, which are used in the compensation network ofsome amplifier schemes. The closed-loop transfer functions ofthe topologies in Fig. 1 are derived by considering a generic al-gebraic feedback factor and the open-loop op-amp transferfunctions originally introduced by the schemes’ authors. Thesetransfer functions were developed under the following assump-tions: 1) the output lumped parasitic capacitances can beneglected with respect to the load and compensation capaci-tances; 2) the dc gain of each stage is much greater than one,i.e., ; 3) the last inverting output stagetransconductance is greater than the sum of andto preserve the negative feedback through the compensation ca-pacitances; 4) the amplifier GBW is well-approximated by theopen-loop unity-gain frequency, i.e., ; 5) theamplifier closed-loop dc gain is well-approximated by .

The transfer functions of the three-stage schemes are summa-rized in Table I.

A. NGCC, NMCF, and NMC

The NMC topology (Fig. 1(a) with ) is character-ized by three poles, one right-half-plane (RHP) and one left-half-plane (LHP) zeros whose effects on the frequency responsecan be neglected if . When this condition is

not satisfied, the RHP zero causes the degradation of the ampli-fier phase margin whereas the LHP zero tends to improve theop-amp stability. In the NGCC scheme [Fig. 1(b)] [14], twofeedforward stages ( and ) are usedto cancel both zeros.

In the NMCF topology (Fig. 1(c) with ) [7], the zeroscancellation is not performed and a single feedforward stage

is used to improve the op-amp phase margin by prop-erly placing the two zeros. As suggested by NMCF authors,

can be fixed equal to in order to obtain a symmetricalpush-pull output stage. The transfer function (1a) describes theclosed-loop behavior of NGCC, NMC ,and NMCF topologies.

B. NMCNR and NMCFNR

In NMCNR [9] and NMCFNR [15], [16] topologies[Fig. 1(a), (c)], a nulling resistance is used to cancel theRHP zero. In NMCFNR scheme a feedforward transconduc-tance is also added to improve the op-ampbandwidth. The closed-loop transfer function of the NMCFNRamplifier is given by (1b). From (1b), the NMCNR transferfunction can be simply obtained by imposing .

C. AFFC

As shown in Fig. 1(d), the AFFC amplifier [18], [19] ex-ploits a feedforward stage and an active-ca-pacitive-feedback network in which a positive gain stageis added in series with the external compensation capacitance


PUGLIESE et al.: TIME OPTIMIZATION FOR THREE-STAGE CMOS AMPLIFIER TOPOLOGIES 2571

TABLE ICLOSED-LOOP TRANSFER FUNCTIONS

. By imposing = and assuming[5], the closed-loop AFFC transfer function is given

by (1c). From (1c), it is evident that the amplifier poles also de-pend on the first-stage output parasitic capacitance .

D. DFCFC

In the DFCFC topology [7], [17] [Fig. 1(e)], a damping-factor-control stage is introduced to avoid the bandwidthlimitation caused by the direct connection of the internalcapacitance to the op-amp output node. is insteadconnected across a further gain stage . A feedforwardtransconductance stage ( [7]) is also used

in the amplifier topology. As suggested by the authors of theDFCFC scheme, can be assumed and zeros can bereasonably neglected for the sake of simplicity [5], [7], [17].The DFCFC op-amp closed-loop transfer function is given by(1d). As is evident from (1d), an explicit dependence of poleson the second-stage output parasitic capacitance exists forthis topology.

E. DLPC

The DLPC topology [21] [see Fig. 1(f)] exploits boththe damping-factor-control stage and the active-capaci-tive-feedback network . A feedforward transconductance



TABLE IICOMPENSATION NETWORK DESIGN RULES

stage ( [21]) is also used in the ampli-fier topology. As suggested by the DLPC scheme’s authors,

can be assumed [21]. The DLPC op-ampclosed-loop transfer function is given by (1e), in which an ex-plicit dependence of the poles on the first-stage output parasiticcapacitance exists.

F. MNMC and ACBC

In the MNMC topology [13] [Fig. 1(g)], a feedforward pathis used to introduce a low-frequency LHP zero in the

amplifier frequency response. By neglecting high-frequencyzeros [5], [13], the MNMC closed-loop transfer function isgiven by (1f). As suggested by MNMC authors,

canbe fixed in order to perform a pole–zero cancellation in (1f) [5],[13]. Pole–zero cancellation also occurs in the ACBC scheme[22] [Fig. 1(h)], in which a further amplifier stage with transcon-ductance and output resistance is connected in parallelwith the second stage to improve the op-amp high-frequencygain. In ACBC amplifiers, a feedforward transconductancestage is also employed. Owing to the pole–zero cancella-tion, the two-pole transfer function (1g) can be used to describethe closed-loop behavior of both MNMC and ACBC op-amps.In (1g), for MNMC,and forACBC.



TABLE III� AND FOM EXPRESSIONS

G. TCFC

As shown in Fig. 1(i), the TCFC amplifier [20] exploits afeedforward stage and an active-capacitive-feedback network in which a positive gain stage is addedin series with the external compensation capacitance . Theclosed-loop TCFC transfer function is given by (1h).

H. DPZC

In the DPZC topology [10], [11] [Fig. 1(j)], two resistors (and ) are introduced in the compensation network to per-form a double pole–zero cancellation. The closed-loop DPZCtransfer function is given by (1i). As suggested by DPZC au-thors, can be reasonably chosen in (1i)[5]. By imposing and

, the single-pole transfer function(1j) arises for the DPZC op-amp.

III. SETTLING TIME MINIMIZATION AND FIGURE OF MERIT

The speed of three-stage amplifiers is determined by the slewrate and the linear settling characteristics. Although slewing re-quires the analysis of nonlinear response, simple expressionscan be used in the early-design phase to analyze the large-signalresponse of amplifiers [5], [17], [22]. Early-design rules to eval-uate linear settling characteristics of three-stage op-amps are in-stead not simple to obtain.

The settling time is the time period required by the op-ampoutput to enter and remain within a specified error band centeredon the output steady-state value, starting from the time instantin which an input step is applied to the amplifier. According tothe above definition, can be formalized for a given responseaccuracy level as follows [26]:

(2)

where is the dynamic settlingerror (DSE), and being the instantaneous and steady-



state values of the time response, respectively. For an inputstep of amplitude is evaluated from the closed-loopop-amp transfer function by means of the inverse Laplacetransformation

(3)

The settling time (2) can be reduced (and theoretically ze-roed) by appropriately choosing the three stage transconduc-tances in order to place the amplifier poles at more and morehigh (infinite) frequencies. However, the settling time reduc-tion is not the only criterion for choosing the stage transcon-ductances, because these latter also affect other important pa-rameters such as the dc gain, the power dissipation, the outputswing and the noise immunity. Therefore, the development ofa systematic design approach to minimize the settling time ata parity of transconductance values is badly needed to improvethe amplifier speed performances, avoiding power wasting andineffective trial-and-error design procedures [25]. To this aim,a systematic strategy to optimize the compensation network forgiven transconductances is introduced in this section. The crite-rion is based on a time-domain normalization which also allowsthe definition of a new figure of merit for a coherent comparisonof settling performances of the different NMC-based schemescharacterized by third-, second-, and first-order closed-loop dy-namic behavior.

A. Third-Order Settling Behavior

The following generic third-order transfer function with dcgain , one real pole , two complex-poles with natural fre-quency and damping factor , and two zeros and

(4)

can be used to analyze the closed-loop dynamic behavior ofNMC, NMCF, NMCNR, NMCFNR, and AFFC (when

), NGCC, DFCFC, and DLPC (when ). Someuseful suggestions to improve the settling time of (4) can befound in [27], although they cannot be directly exploited to de-velop a methodical settling time minimization approach. To deal

with the minimization problem systematically, it is instead con-venient to consider the following normalized system:

(5)

where andare the relative real pole and zero locations, respectively, withrespect to the real part of complex poles . This latter is thenormalization factor. The transfer function (5) arises from (4)according to the time-scaling property of the Laplace transform[28], when the time variable is substituted with the followingnormalized variable:

(6)

According to (2) and (6), the normalized settling time of (5)for the accuracy level (namely ) is given by (7) at thebottom of the page.

The best op-amp dynamics for a given is the one whichallows the minimum value of , namely , to beachieved. From (7), is then obtained by optimizing therelative pole/zero placements of (4) (regardless of their absolutepositions which are also determined by ), i.e.,

(8)

It is worth pointing out that and in (8) can be ac-tually expressed as functions of and once the three stagetransconductances (and, consequently, the feedforward stagetransconductances) have been fixed. In fact, by comparing (4)with (1a)–(1c), it is evident that the amplifier zeros cannot beindependently placed from the poles in this case, i.e., andare the only parameters which are actually free in (7)–(8).

Thus, the minimization problem to find for the de-sired accuracy level reduces to find the optimal values ofand (namely and ). From a practical point ofview, owing to the complexity of the problem (7)–(8),and are achieved by means of numerical simulationsin which is calculated for all possible values of and

. Clearly, only admissible solutions for andleading to physically realizable amplifier pole/zero placementsshould be considered, thus rejecting solutions which refer todegenerate one-pole systems (i.e., systems with

(7)



and ). The MST op-amp response for given stagetransconductances is then obtained by optimizing the compen-sation network on the basis of and values.Interestingly, numerical simulations show that the third-orderop-amp MST response for the desired accuracy level is alwayscharacterized by optimally damped oscillations whose first twopeaks equal the upper and the lower borders of the error band,respectively [25], [26]. The absolute (i.e., de-normalized) MST,namely , can be then derived from (6) as the following:

(9)

B. Second-Order Settling Behavior

Some three-stage op-amp topologies, such as the previouslymentioned TCFC, MNMC, and ACBC and schemes, actuallybehave as second-order systems with two complex-poles andone zero :

(10)

For MNMC and ACBC topologies, . The settlingtime minimization for (10) can be performed by considering thefollowing transfer function:

(11)

which arises from the time normalization (6). The normalizedsettling time of (11) for the accuracy level (namely )is defined as

(12)

The best op-amp dynamics for a given is the one forwhich is minimized. The minimum value of , namely

, is then obtained by optimizing the relative pole/zeroplacements of (10) (regardless of their absolute positions whichare also determined by ), i.e.,

(13)

By comparing (10) with (1h), it appears that the amplifier zerocannot be independently placed from the poles once the stagetransconductances have been fixed. This means that in (13)can be actually expressed as function of , which is the only freeparameter in the minimization problem. Thus, for thedesired accuracy level is obtained by finding the optimal valueof , namely . From a practical point of view, owing tothe complexity of the problem (12)–(13), is achieved bymeans of numerical simulations in which is calculated for

all possible values of . Numerical simulations show that theMST response for second-order systems is achieved when themaximum overshoot of the response equals the upper border ofthe error band identified by the accuracy level [23], [26]. TheMST response is obtained by sizing the compensation networkon the basis of . From (6), the absolute MST for second-order systems is given by

(14)

It is worth pointing out that although (14) has a similar for-mulation with respect to (9), the absolute MST of third- andsecond- order systems are clearly different because the optimalparameters for a given accuracy level are in general different forthe two cases.

C. First-Order Settling Behavior

Finally, in a few cases, such as the DPZC scheme, three-stage topologies may be characterized by the following one-poleclosed-loop transfer function:

(15)

where is the GBW product. By considering the time normal-ization , the following system arises:

(16)

whose normalized settling time for the accuracy level (namely) is given by

(17)

It is evident that (16) does not present free parameters to beoptimized. For this reason, the normalized MST is given by (17)which can be rewritten in closed-form as follows:

(18)

Since dB, a positive value for results fromthe above expression. The de-normalized MST for first-ordersystems is then given by

(19)

D. Figure of Merit

To evaluate the small-signal settling characteristics of three-stage amplifiers, a novel time-domain-based figure of merit isintroduced. It allows the amplifier speed efficiency to be esti-mated by taking into account the op-amp MST for a given timeresponse accuracy level, the stage transconductances and theoutput capacitive load. The figure of merit is defined as follows:

(20)



where and is the total transcon-ductance of potential gain stages used for the compensation net-work that actually imply additional bias currents and siliconarea. It is worth noting that both the power consumption and thesilicon area occupation are taken into account by consideringthe transistor transconductances in (20). In fact, transconduc-tances are directly related to the transistor area and bias current[5]. The proposed FOM allows a well-founded evaluation of thesettling performances to be carried out whatever the op-amp dy-namic behavior is. Evidently, (20) is straightforwardly related tothe op-amp GBW product only in the presence of a first-ordersettling behavior. In this case, in fact, it comes from (18)–(20)that , which coincides with thefrequency-domain-based figure of merit defined in [5]. Instead,for high-order dynamics, the proposed FOM does not coincidein general with the one in [5]. In the next section, FOM willbe specified for all the three-stage amplifier topologies underexamination.

IV. COMPENSATION NETWORK OPTIMIZATION

AND FIGURE OF MERIT

In order to fix the compensation network parameters whichallow the best settling performances preserving the closed-loopop-amp stability, appropriate design rules have to be formulated.To this aim, the relationship between the relative closed-looppole/zero locations and the compensation network parameters isderived for each amplifier topology. The compensation networkrules for each investigated topology are derived and summarizedin Table II. The MST and the figure of merit (20) are reportedin Table III.

A. NMC and NMCF

By comparing the denominators of (1a) (with ) and(4) and taking the time normalization (6) into account, expres-sions (21a) and (21b) for and can be derived. Theoptimal values of and for NMC andNMCF are obtained from (21a)–(21b) with and

. These latter arise from the minimization problem(7)–(8) by considering (21c) and the following expression forthe normalized zeros

(22)

which comes from the comparison of the numerators of (1a) and(4). Similarly, from (1a) and (4), the expression to be usedin order to calculate the de-normalized MST (9) is given by

(23)

B. NGCC

In the case of NGCC and in (1a) equal and, respectively. Thus, comparing (1a) and (4), expressions

(21d) and (21e) for and can be written. The MSTresponse is reached in correspondence to and

, resulting from the minimization problem (7)–(8) (with). The following expression for to be used in (9)

arises from (1a) and (4)

(24)

C. NMCNR

For NMCNR topology, expressions (21f) and (21g) forand , respectively, are derived by comparing the denomi-nators of (1b) (with ) and (4). The MST response isobtained in correspondence to the optimal valuesand which result from (7)–(8) by considering thenormalized zero

(25)

which is derived by comparing the numerators of (1b) and (4)(with ). The expression to be used in (9) is givenby (24).

D. NMCFNR

For NMCFNR amplifier, by comparing the denominators of(1b) and (4), expressions (21h) and (21i) follow. The MST re-sponse for NMCFNR scheme is obtained in correspondence tothe optimal values and . These latterresult from (7)–(8), (21j) and the normalized zero expression asshown by (26) at the bottom of the page, which is derived bycomparing the numerators of (1b) and (4) with . From(1b) and (4), expression to be used in order to calculate thede-normalized MST (9) can be also derived

(27)

E. AFFC

The MST response for the AFFC scheme is obtained by op-timizing the compensation capacitance and the transcon-ductance of the additional gain stage . By comparing thedenominators of (1c) and (4), expressions (21k) and (21l) for

and can be obtained. To identify the optimal andvalues, (21k)–(21j) have to be evaluated in correspondence

to the optimal values and . Theselatter can be obtained from (7)–(8) by considering the normal-ized zero , which is derived by comparing the numer-

(26)



Fig. 2. Typical implementations of compensation networks of the different three-stage op-amps. (a) NMC �� and NMCNR. (b) NMCF �� andNMCFNR. (c) DPZC. (d) MNMC. (e) NGCC. (f) DFCFC. (g) AFFC. (h) ACBC. (i) TCFC. (j) DLPC.

Fig. 3. Basic three-stage op-amp scheme.

ators of (1c) and (4) when . The value to be used in(9) becomes, from (1c) and (4)

(28)

F. DFCFC

By comparing the denominators of (1d) and (4) expressions(21m) and (21n) for and can be carried out. Thus, forDFCFC amplifiers, the MST response can be obtained by op-timizing and in correspondence to the optimal values

and resulting from (7)–(8) when. Similarly, from (1d) and (4), the expression

needed in (9) for the de-normalized MST becomes

(29)

G. DLPC

The MST response for the DLPC amplifier is achieved byoptimizing the compensation capacitance and the transcon-ductance of the active-capacitive-feedback network . Bycomparing the denominators of (1e) and (4), expressions (21o)and (21p) for and can be obtained. To identify theoptimal and values, (21o)–(21p) have to be evaluatedin correspondence to the optimal values and



which are obtained from (7)–(8) when .From (1e) and (4), the value to be used in (9) is

(30)

H. MNMC and ACBC

The MST response for MNMC and ACBC topologies is ob-tained by optimizing . By comparing the denominators of(1g) and (10), expression (21q) for arises. The optimalvalue of results from (21q) for , the latter arisingfrom the minimization problem (12)–(13) when . From(1g) and (10), the expression to be used in (14) is

(31)

I. TCFC

The MST response for TCFC scheme is achieved by opti-mizing , whose expression (21r) can be obtained by com-paring the denominators of (1h) and (10). The optimal value of

results from (21r) for , the latter arising fromthe minimization problem (12)–(13) by considering the expres-sion for the normalized zero shown in (32) at the bottom of thepage. From (1h) and (10), the expression to be used in (14)is shown in (33) at the bottom of the page.

J. DPZC

Finally, in the DPZC scheme, the compensation network pa-rameters are set to realize a double pole–zero cancellation, thusdesigners have no further leeway in fixing them. From (15) and(1j), the expression for to be used in (19) is given by

(34)

V. DESIGN EXAMPLE AND PERFORMANCES COMPARISON

The proposed settling-time optimization approach was ap-plied to design voltage buffers employing the various previouslydiscussed compensation topologies. A commercial 0.35- mCMOS technology was used. The settling performances ofthe amplifiers were evaluated by means of the figure of merit

introduced in Section III. The compensation networks depictedin Fig. 2 were used to compensate the basic op-amp shownin Fig. 3. In it, M1-M5, M6-M9 and M10-M11 constitutethe first, the second, and the third amplifier stages, respec-tively. are the transconductances of MOSFETsM1-M2, M6 and M11, respectively. In NMCF, NMCFNR,DFCFC, AFFC, ACBC, TCFC and DLPC schemes, the feed-forward transconductance is implemented by connectingthe gate of M10 to the first-stage output voltage . Inthe MNMC topology [Fig. 2(d)], M11-M13 implement thefeedforward transconductance . In the NGCC amplifier[Fig. 2(e)], the transconductance of M13 is , whereasM14-M17 are used to implement . The stage representedby the transconductance in the DFCFC amplifier is real-ized by the common-source M12-M13 [Fig. 2(f)]. in theAFFC and ACBC amplifiers is the transconductance of M13[Fig. 2(g)] and M12 [Fig. 2(h)], respectively. In the TCFCamplifier [Fig. 2(i)], is the transconductance of M13. ForDLPC, and are the transconductance of M12 andM15 [Fig. 2(j)], respectively. The designs achieved a minimumopen-loop dc gain of 100 dB and the best settling performancesfor a 1% output response accuracy level. A/V,

A/V and A/V were chosen, and aload capacitance of 100 pF was assumed. For the AFFC,ACBC and DPZC schemes, , and

, respectively, were assumed [5]. The optimalnormalized parameters resulting from numerical simulations,the compensation network elements obtained according tothe proposed design rules, and the predicted and FOMare summarized in Table IV. In the table, the compensationnetwork parameters arising from the rules presented originallyby the schemes’ authors are also listed. Moreover, the tablesummarizes the parameters obtained from the design rulesproposed in [5] in correspondence to a phase margin of 70 ,as suggested in [5] for 1% accuracy level in the response. ForTCFC and DLPC, no rules are available in [5].

Table V reports the HSPICE simulation results related to thepositive/negative settling times and FOM values foreach topology compensated according to the proposed rules.

The positive/negative step responses of the designed voltagebuffers are depicted in Fig. 4. Table V also summarizes theop-amp settling times obtained when the design rules presented

(32)

(33)



Fig. 4. HSPICE simulation results for the 10-mV positive/negative step responses of the different three-stage amplifiers in voltage buffer configuration com-pensated according to the proposed strategy: DPZC, NMC, NGCC, NMCF, NMCNR, NMCFNR, AFFC, TCFC, DFCFC, ACBC, and DLPC (� � � ��A/V,� � � ��A/V, � � � ��A/V, � � �� pF); MNMC (� � � ��A/V, � � � ��A/V, and � � � �� mA/V, � � �� pF).

by the schemes’ authors and those proposed in [5] are used tosize the compensation networks. The GBW, the phase margin(PM) and the power consumption of the different op-amps arereported in Table VI. The results highlight that, with respectto the other considered approaches, the proposed systematicoptimization strategy generally leads to a significant settlingtime reduction at parity of power consumption. It is also worthpointing out that the and FOM values arising fromcircuit simulations are generally in good agreement with the pre-dicted ones for all the considered schemes, with the exceptionof the MNMC configuration. For this latter, the discrepancy isactually due to the stage transconductance values used in the de-

sign example. Although the chosen values satisfy the condition, higher , and ratios should

be indeed considered for MNMC in order to avoid the phasemargin degradation caused by the introduction of an RHP zeronot considered in the original model [13]. In fact, (1f) well-de-scribes the MNMC op-amp behavior only if[5]. This was evidenced by considering A/V,

A/V, and A/V in a further design ofthe MNMC amplifier, carried out for the sake of completeness.In this case, andpF, leading to ns and , in ac-cord with the proposed analysis. From HSPICE simulations,



TABLE IVOPTIMAL VALUES CALCULATED FOR THE NORMALIZED AND

COMPENSATION NETWORK PARAMETERS, � AND FOM(� � � ��A/V, � � � ��A/V, � � � �� A/V, � � �� pF;� � � �� pF FOR DFCFC; � � ��A/V AND � � � � pF

OR TCFC; � � � �� pF AND � � ��A/V FOR DLPC)

ns and result. Finally,important results come out by comparing the FOM valuesreported in Table V. In fact, for the used technology, the stagetransconductances and the load capacitance considered inabove design examples, the DLPC, DFCFC, ACBC, TCFC,and AFFC topologies prove to be the most efficient solutionsto achieve fast-settling three-stage op-amps. It also appears thatthe optimization of the third-order dynamic behavior of thebasic NMC configuration results in better settling performancesthan the single-pole DPZC op-amp. Moreover, comparedwith the NMC scheme, the NGCC, NMCNR and MNMCtopologies (provided that the conditionis satisfied for the latter) guarantee a slight improvement ofthe settling performances, whereas a significant efficiencyincreasing is obtained by resorting to NMCF and NMCFNRop-amps. At system design level, the proposed FOM can beinterpreted as an indication of overall performance of circuitsusing high-speed op-amps, such as ADCs. For example, theincrement of the ADC effective number of bits which can beobtained by means of typical oversampling and noise shaping

TABLE VHSPICE RESULTS FOR THE SETTLING TIME PERFORMANCES OF AMPLIFIERS

TABLE VIHSPICE RESULTS FOR THE GBW, PM AND POWER DISSIPATION

VALUES (@ �� V) OF AMPLIFIERS

techniques, is estimated asand , respectively [29].



In these equations, and are the ADC input signal band-width and sampling frequency, respectively. The maximumachievable is basically determined by the op-amp settlingtime. As a consequence, on the basis of the above relationshipsfor and , the difference in the settling times of themost and the less efficient op-amp schemes considered (i.e., theDLPC and DPZC topology, according to the proposed FOM),translates into a difference of about 4 or 10 bits in the maximumresolution achievable by oversampling or noise shaping ADCs,respectively.

VI. CONCLUSION

A settling-time-oriented design approach for the systematicoptimization of compensation networks for the most used three-stage amplifier schemes has been presented. A new figure ofmerit to evaluate the op-amp efficiency in terms of settling timeperformance has been defined. Different voltage buffers em-ploying the three-stage amplifier schemes under considerationwere designed in a commercial 0.35- m CMOS technology.The circuit simulation results demonstrate that the proposedmethod guarantees a significant reduction in the op-amp settlingtime with respect to other existing strategies. It is also shown thatthe proposed FOM can be successfully utilized to identify thebest compensation network, when time-domain performance iscritical.

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Andrea Pugliese was born in 1969. He received theM.S.degree in computer science engineering and thePh.D. degree in electronics engineering from the Uni-versity of Calabria, Cosenza, Italy.

He was with STMicroelectronics, Catania, Italy, assustain engineering for memory device designers. In2002, he joined the Department of Electronics, Com-puter Sciences, and Systems, University of Calabria,Cosenza, where is currently an Assistant Researcherof Electronics. His main research interests are in fre-quency compensation op-amp technique, delta-sigma

ADC modulation, and low-voltage low-power CMOS analog design.



Francesco Antonio Amoroso was born in 1983. Hereceived the M.S. degree in electronics engineeringfrom the University of Calabria, Cosenza, Italy, in2006.

Currently, he is with the Department of Elec-tronics, Computer Sciences, and Systems, Universityof Calabria. His current research interests in-clude the design of high-speed low-power analogand mixed-signal CMOS circuits, sigma-deltaanalog-to-digital converters, and operational ampli-fiers for switched-capacitor applications.

Gregorio Cappuccino (M’00–SM’08) receivedthe Laurea degree (magna cum laude) in computerscience engineering from the University of Calabria,Cosenza, Italy, in 1992 and the Ph.D. degree inelectronics from Politecnico of Turin, Turin, Italy, in1998.

In 1993, he joined the Electronic Components andElectromagnetism Institute of National Council ofResearch, where he was involved in the design ofa Synthetic Aperture Radar Data Processor. Since1994, he has been with the Department of Computer

Science, Electronics, and Systems, University of Calabria, where he is currentlyan Associate Professor. His current research and teaching interests includedigital and analog electronics, mixed-signal silicon circuit and system design,and high-speed interconnects. He is an Associate Editor of the Journal ofCircuits, Systems and Computers.

Dr. Cappuccino has been selected as the recipient of the University of Cal-abria Young Researchers Award for 1999 and University of Calabria LearningEnhancement Project Award in 1999.

Giuseppe Cocorullo was born in 1952. He receivedthe Dr.Eng. degree in electronics from the Universityof Naples, Naples, Italy, in 1978.

From 1983 to 1992, he was with National Councilof Research, IRECE Institute, Naples, where he wasin charge of the Microelectronic Department. Since1992, he has been an Associate Professor of Elec-tronics at the University of Calabria, Cosenza, Italy.Since 2000, he has been a Full Professor of Elec-tronics at the University of Calabria. His main re-search interest are in the fields of silicon optoelec-

tronics and application specific IC design.


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