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0-7803-9077-6/05/$20.00 © 2005 IEEE October 19 – 22, 2005, Indianapolis, IN 35th ASEE/IEEE Frontiers in Education Conference

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Work in Progress - Use of CPU Prototyping and Logic Analyzers to Cultivate Troubleshooting Skills

Mark C. Johnson

Purdue University, School of Electrical and Computer Engineering West Lafayette, IN 47907 mcjohnso@purdue.edu

Abstract - One skill that is particularly difficult to teach and difficult to master, is the integration of complex systems. Students reach the 90% completion point of a project naively confident that components that work together in simulation will work in hardware. Students in the computer architecture prototyping laboratory often discover this optimism to be unfounded. In the laboratory, students design, build, and test a multicycle CPU (central processing unit), pipelined CPU, and cache memory. Starting Fall 2004, logic analyzers were incorporated to allow for more complete observation of hardware behavior. Previously, all hardware troubleshooting was accomplished through switches, light-emitting diodes, and memory dumps. Student opinions regarding the value of the logic analyzers varied widely, but over 50% of students reported that the logic analyzers helped them to isolate hardware problems, and 65% of students used them to verify correct operation of their designs. Index Terms - Computer Architecture, Digital Logic, Logic Analyzer, Instrumentation, Prototyping.

INTRODUCTION

The Acreditation Board for Engineering and Technology (ABET) criteria for engineering programs [1] has identified “an ability to design a system, component, or process to meet desired needs with realistic constraints…” and “an ability to use the techniques, skills, and modern engineering tools necessary for engineering practice” as critical skills to be attained by all engineering students. The ECE437L Computer Architecture Prototyping Laboratory at Purdue University addresses these particular criteria by requiring students to design, build, test, and demonstrate (in hardware) a functional CPU and cache. Students in ECE437L repeatedly commented on course evaluations about the need for more and better troublshooting techniques. Through the incorporation of logic analyzers, we address this need and the call for “techniques, skills, and modern engineering tools” found in the ABET critera.

In the remainder of this paper, we present an overview of the the ECE437L laboratory, modifications to exploit logic analyzers, preliminary results from student surveys, tentative conclusions regarding the utility of logic analyzers in a computer architecture laboratory, and plans for ongoing work.

COMPUTER ARCHITECTURE PROTOTYPING LABORATORY

The ECE437L Computer Architecture Prototyping Laboratory is the laboratory component for ECE437 Computer Design and Prototyping, a required course in Computer Engineering. Theoretical content includes arithmetic algorithms, multi-cycle processors, pipelined processors, cache hierarchy with virtual memory, input/output, and memory hierarchy performance. The laboratory complements this material by requiring students to build and test a multi-cycle processor, pipelined processor, and cache, first by means of VHDL (VHSIC Hardware Description Language) simulation, and then by mapping the VHDL code to hardware on an FPGA (Field Programmable Gate Array). An FPGA prototyping system, pictured below, is used. CPU test inputs and outputs are limited to dip switches, button switches, light emitting diodes (LEDS), an on board clock that can be single stepped, on board SRAM, and a serial interface to initialize and view the contents of SRAM. It is not difficult to verify a correctly operating CPU this way, but subtle errors can be difficult to observe or isolate.

FIGURE 1 FPGA PROTOTYPING SYSTEM

INCORPORATION OF LOGIC ANALYZERS

Prior to the Fall 2004 semester, Tektronix 716 logic analyzer mainframes with 64 channel logic analyzer modules were installed in the laboratory at half of the prototyping stations. Student lab staff (see acknowledgements) prepared tutorial materials on the use of the logic analyzer, documented a standard probe configuration, created corresponding

switches

LEDs

serial interface

Altera 10K70 FPGA (Hidden)

Session F3J

0-7803-9077-6/05/$20.00 © 2005 IEEE October 19 – 22, 2005, Indianapolis, IN 35th ASEE/IEEE Frontiers in Education Conference

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configuration files for the logic analyzers, and prepared a laboratory exercise requiring students to diagnose errors in deliberately defective designs. For the Spring 2005 semester, the laboratory exercise was eliminated, and use of the logic analyzers was made mandatory when students demonstrate designs to their teaching assistant (TA).

STUDENT AND TEACHING ASSISTANT ASSESSMENT

At the end of the Spring 2005 semester, a comprehensive survey of ECE437 was taken to evaluate all aspects of the laboratory, including the logic analyzers. Out of 42 students in ECE437, 30 responded. Table 1 summarizes the results of the student survey.

TABLE I

STUDENT SURVEY RESULTS Question (over entire semester)

Measure

Result

How many times did the logic analyzer help identify a problem? How many times did the logic analyzer help verify correct operation? Would you care if the logic analyzers were removed?

Number of Responses At least once Total, Average per person Number of Responses At least once Total, Average per person Number of Responses Yes No

29 16 22, 0.76 29 19 79, 2.72 30 11 19

In addition to numeric and yes/no answers, students were asked to comment on their answer to the third question. Of those who answered yes, the only recurring answer was that the logic analyzers did help in identifying problems. Of those who answered no, most explanations fell into one of three categories: “too hard to use”, “nobody is using them”, or “not needed – memory dump is sufficient”.

While the response was not as enthusiastic as anticipated, part of the negative response came from students who simply did not need the logic analyzers as a result of good design practices and thorough verification of the design during simulation. The greatest opportunity for improvement is with those students who found the logic analyzers too difficult to use.

From the point of view of TAs, the major benefit of the logic analyzers consisted in being able to prove to some students that malfunctions were in fact a result of student design errors, not failure of the prototyping system or test equipment. In addition, TAs have observed an increase in the success rate of students in terms of obtaining working designs

since the logic analyzers were introduced, but there are several other factors that could account for some or all of the improvement.

CONCLUSIONS AND FUTURE WORK

While not revolutionary, logic analyzers into ECE437 have been useful to both TAs and a large fraction of students. Interestingly, the logic analyzers were useful more often in verifying and demonstrating correct operation of a CPU design than in isolating failures.

This work will be continued in a variety of ways including: • Continued assessment of student utilization of logic

analyzers. • More detailed assessment to determine the contribution of

logic analyzers to student success in the laboratory. • Finding ways to make the logic analyzers more useful to

students who found them to be too difficult or time consuming.

A closely related project involves automation of grading

student hardware. Two logic analyzer mainframes in the laboratory are also equipped with pattern generator modules. The combined logic analyzer/pattern generator can be programmed to generate input vectors and monitor for correct outputs. This would be especially useful in the verification of cache and major CPU components such as the arithmetic logic unit. We already take an approach similar to this for verification of student source code and circuit netlists, but pre-integration hardware testing of major blocks has been limited to what students can demonstrate using switches and LEDs.

ACKNOWLEDGMENTS

The logic analyzers in ECE437 were heavily subsidized by Tektronix, Inc. Numerous individuals contributed to the creation of laboratory materials, installation and configuration of the logic analyzers, modification of the prototyping boards to accommodate more logic probes, and providing support to students using the equipment. These individuals include: laboratory engineer Charles Barnett; student volunteers Evie Salim and Scott Zadigan; graduate teaching assistants Michael Maletich, William Nagel, and Ethan Schuchman, undergraduate teaching assistant Jacob Schroeder, and GAANN (Graduate Assistant in Areas of National Need) fellow Nathaniel Edward Pettis.

REFERENCES

[1] Accredidtation Board for Engineering and Technology, Criteria for

Accrediting Engineering Programs, November 1, 2004.