Session 25 Overview: GaN Drivers and Galvanic Isolators

426 • 2017 IEEE International Solid-State Circuits Conference 978-1-5090-3758-2/17/$31.00 ©2017 IEEE

ISSCC 2017 / SESSION 25 / GAN DRIVERS AND GALVANIC ISOLATORS / OVERVIEW

Session 25 Overview: GaN Drivers and Galvanic IsolatorsTECHNOLOGY DIRECTIONS SUBCOMMITTEE

Subcommittee Chair: Eugenio Cantatore, Eindhoven University of Technology, Eindhoven, The Netherlands

Gallium-Nitride (GaN) power devices have garnered a lot of attention for their reduced switching losses leading to small-form-factorhigh-frequency switching converters. However, issues related to reliable GaN gate driving, signal and power isolation with highcommon-mode immunity, and reduced electromagnetic interference (EMI) need special attention. This session presents recentadvances in EMI-aware gate drivers for GaN devices and galvanic isolators for both signal and power transfer.

Session Chair: Shuichi Nagai, Panasonic, Osaka, Japan

Session Co-Chair: Yogesh Ramadass, Texas Instruments, Santa Clara, CA

427DIGEST OF TECHNICAL PAPERS •

ISSCC 2017 / February 8, 2017 / 1:30 PM

1:30 PM25.1 A 50.7% Peak Efficiency Subharmonic Resonant Isolated Capacitive Power Transfer System with

62mW Output Power for Low-Power Industrial Sensor InterfacesL. Chen, University of Texas at Dallas, Richardson, TX

In Paper 25.1, the University of Texas at Dallas describes a subharmonic resonant isolated capacitive powertransfer (ICPT) system that supplies power wirelessly to sensor interfaces across on-chip capacitive galvanicisolation barrier. The design achieves 4× higher efficiency and 3× higher power delivery compared to the priorart.

2:00 PM25.2 A 10MHz 3-to-40V VIN Tri-Slope Gate Driving GaN DC-DC Converter with 40.5dBμV Spurious Noise

Compression and 79.3% Ringing Suppression for Automotive ApplicationsX. Ke, University of Texas at Dallas, Richardson, TX

In Paper 25.2, the University of Texas at Dallas describes a GaN DC-DC converter for automotive applicationsthat employs spurious noise compression and adaptive tri-slope gate driving schemes. Using these techniquesthe design is able to reduce the peak spurious noise from 84.73 to 44.23dBµV.

2:30 PM25.3 A 1.3A Gate Driver for GaN with Fully Integrated Gate Charge Buffer Capacitor Delivering 11nC Enabled

by High-Voltage Energy StoringA. Seidel, Reutlingen University, Reutlingen, Germany

In Paper 25.3, Reutlingen University presents a GaN gate driver with a fully integrated gate charge buffercapacitor. This gate driver supplies 11nC gate charge without any external buffer capacitor, which is more than45× improvement as compared to previous designs.

2:45 PM25.4 A 500Mb/s 200pJ/b Die-to-Die Bidirectional Link with 24kV Surge Isolation and 50kV/μs CMR using

Resonant Inductive Coupling in 0.18μm CMOSS. Mukherjee, Texas Instruments, Bangalore, India

In Paper 25.4, Texas Instruments demonstrates a 500Mb/s bidirectional, isolated, inductively coupled die-to-die link at 200pJ/b in 0.18μm CMOS. This isolation technique achieves 24kV surge isolation and 50kV/µscommon-mode transient noise rejection (CMR) that is 2× higher surge isolation and 2× higher data rate at 33%of the power level of previous designs.

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428 • 2017 IEEE International Solid-State Circuits Conference

ISSCC 2017 / SESSION 25 / GAN DRIVERS AND GALVANIC ISOLATORS / 25.1

25.1 A 50.7% Peak Efficiency Subharmonic Resonant Isolated Capacitive Power Transfer System with 62mW Output Power for Low-Power Industrial Sensor Interfaces

Lei Chen1, Joseph Sankman1,2, Rajarshi Mukhopadhyay2, Mark Morgan2, D. Brian Ma1

1University of Texas at Dallas, Richardson, TX2Texas Instruments, Dallas, TX

Low-power sensor interfaces play a key role in monitoring industrial systemreliability in hostile environments. They are exposed to destructive surge voltages,which are caused by ground current spikes from operation transitions ofmachinery and motor drives, endangering circuit functionality. Employing galvanicisolation is thus imperative to protect the sensor analog front end (AFE) fromsevere damage. However, the use of an isolation barrier presents severalchallenges. Without a wired connection to the sensor AFE, power/data must betransferred through the barrier via magnetic or capacitive coupling. Moreover,size and cost are constrained in such applications. In [1], an isolated DC/DCconverter is used, which delivers up to 2W with 80% efficiency, but at the cost ofbulky external micro-henry transformers. To avoid a large form-factor solution,the transformers can be integrated, but efficiency is sacrificed and cost is added.In [2-3], the operating frequency of the integrated transformers is ~300MHz forsize reduction. However, at such a high frequency, the switching power loss (PSW)is greater than 10s of mW, reducing efficiency below 30%. On the other hand,capacitive isolation, usually used in digital links [4], replaces polyimide-basedtransformers with integrated thick dielectric capacitors. It represents a majorimprovement due to size and cost savings as a result of integration on silicon.

A typical implementation of on-chip isolated capacitive power transfer (ICPT) isshown in Fig. 25.1.1, which consists of a power transmitter (TX), a power receiver(RX), and an integrated, thick dielectric capacitive galvanic isolator (CISO).However, thick dielectric causes CISO to suffer from low density. It results in eithera high input impedance path that restricts power delivery capability or huge siliconarea. Compounding this issue, the bottom-plate parasitic capacitance (CPAR) toCISO ratio is large. For 1kV isolation rating, this ratio can be over 1:1. Large peakinput current (IIN) is incurred by CPAR during switching transitions, whichdramatically increases PSW and degrades efficiency. Moreover, without acommunication link between TX and RX, power transfer cannot be optimized toload. For example, at light load, open-loop operation allows VDD2 to rise, causinga large dropout voltage in the regulator and thus increases power loss. To addressthese challenges, this paper introduces an integrated subharmonic resonant ICPTsystem for improving power delivery across galvanic isolation. The resonantapproach enables efficient power transfer by minimizing CISO impedance andmitigating PSW from CPAR. A programmable subharmonic resonant scheme isproposed to improve efficiency by scaling PSW with load. A compact isolatedcapacitive feedback link between TX and RX is seamlessly integrated with theICPT system to achieve real-time optimal power transfer.

Figure 25.1.2 illustrates the system block diagram of the resonant ICPT scheme.The system consists of resonant capacitive isolator, TX, RX, subharmonicresonant tuner and isolated feedback link. In the resonant capacitive isolator, aresonant inductor, LR, is connected to CISO bottom plate. Compared to capacitiveisolator, the resonant approach has two advantages. First of all, it significantlyincreases power delivery capability since LR cancels out CISO at the resonantfrequency (fRES). In other words, operating at fRES creates an AC short path thatallows power to flow uninhibited. Secondly, it reduces PSW caused by CPAR. Currentto charge/discharge CPAR is recycled through LR, so both IIN peak current and PSW

are dramatically decreased. The resonant ICPT system employs a dual-phase TX,which are implemented with all-NMOS stacked topology and bootstrapped driversfor compactness and low cost. In the RX, a full-bridge self-powered active rectifieris used for efficient AC-DC conversion. Two NMOSs, MN1,2, driven by VDD2-powered common-gate comparators, comprise the low side of the rectifier andcross-coupled PMOSs, MP1,2, comprise the high side to alleviate the need forprecise switch timing control.

Figure 25.1.3 shows the TX circuit implementation and subharmonic resonantoperation principle. The TX power stage consists of all N-type power switches forlow PSW. It employs an interleaved 2-phase topology to double transferred power.In each phase, stacked switch structure is employed to extend the input voltagerange and thus further increases power delivery. Bootstrapped driving of high-side stacked switch (by M1 and M1’) is achieved with level shifters and integratedbootstrapped capacitor, CBST. The system modulates switching frequency (fSW)from a VCO to adjust transferred power. Constrained by area and cost, CISO andLR are on the order of 10pF and 100nH, respectively. fRES is thus high, which incurssignificant PSW for driving TX power stages if fSW = fRES. At low power level, largePSW degrades power efficiency. Therefore, a subharmonic resonant power transferscheme is employed in this work. Instead of using resonant operation at fRES, fSW

is set to be the 3rd, 5th or 7th subharmonic of fRES, controlled by the selectordepending on the load condition. For instance, in the 5th subharmonic mode,fSW = fRES/5 and PSW is 5× less than resonant operation, enabling high efficiencyacross a wide load range.

Figure 25.1.4 shows the circuit implementation of the isolated capacitive feedbacklink. The capacitive link is much smaller to integrate compared to magneticcounterparts and inherently compatible with the ICPT standards. It enables signaltransfer despite no common ground. VDD2 and VREF are time-multiplexed by anS/H circuit and an analog DE-MUX, and transmitted from RX to TX by CFB. Theerror signal, VREF−VDD2, is used to control fSW to regulate VDD2 = VREF in RX. Theisolated signal transfer is performed in 4 phases (φ1- φ4). In φ1/φ3, S3 and S4 areon, and CFB is reset. In φ2/φ4, S1 and S2 are on, so VREF or VDD2 is transferreddepending on the selection signal, EN1,2. Switching synchronization is achievedthrough CSYNC, which carries the VCO output, CLK, back to the RX to generate asynchronized clock, CLK’. Two clock synchronizers on each side convert CLK’and CLK into CLK1-CLK4 for 4-phase operation control.

The resonant ICPT system is fabricated with a 0.35μm BCD process. Withnumerous capacitive galvanic isolation data transfer solutions reported, to ourbest knowledge, this is the first successfully implemented ICPT solution. Toachieve isolation, two 20pF high-voltage (<1kV) capacitors are integrated on chipfor each phase. LR is implemented with 110nH off-chip air-core inductor (Q ≈ 150at 40MHz). fRES is measured as 40MHz. CFB and CSYNC in the feedback link are both50fF high-voltage capacitors and placed on RX chip. Figure 25.1.5 shows themeasured TX switching node VSW, input current IIN and RX output VDD2 in the 7th,5th and 3rd order subharmonic modes, respectively, with a power supply of 3.3Vfrom TX chip. The measured efficiency is provided in Fig. 25.1.6. Thanks to thesubharmonic resonant ICPT scheme, power efficiency is improved by more than2.5× at low power levels compared to [2]. Also, with the capacitive feedback link,20% higher power efficiency is achieved compared with LDO-only regulation.With a peak efficiency of 50.7% and maximum POUT of 62mW, this design achieves4× efficiency improvement and 3× power delivery than [3] with the same solutionsize. The chip micrographs are shown in Fig. 25.1.7, with a total die area of4.76mm2.

Acknowledgements:This work is in part supported by SRC under research contract SRC GRC1836.146. The authors would like to thank Jeffrey Morroni and Yogesh Ramadassof Texas Instruments for valuable inputs.

References:[1] Texas Instruments, TPS55010, “6V Input, 2W, Isolated DC/DC Converter withIntegrated FET,” Oct. 2014. Available at: <http:www.ti.com/lit/ds/>.[2] Analog Devices, ADuM5010, “Integrated Isolated DC-to-DC Converter,” Mar.2013. Available at: <http://www.analog.com/en/products/interface-isolation/isolation/isopower/adum5010.html>[3] P. Lombardo, et al., “A fully-integrated half-duplex data/power transfer systemwith up to 40Mb/s data rate, 23mW output power and on-chip 5kV galvanicisolation,” ISSCC Dig. Tech. Papers, pp. 300-301, Feb. 2016.[4] Texas Instruments, ISO7220A, “Dual Channel, 2/0, 1Mbps Digital Isolator,”Sept. 2015. Available at: <http:www.ti.com/lit/ds/>.

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Figure 25.1.1: Capacitive galvanic isolated power transfer system: architectureand challenges. Figure 25.1.2: Block diagram of the proposed subharmonic ICPT system.

Figure 25.1.3: TX block diagram with the subharmonic resonant operationprinciple.

Figure 25.1.5: Measured waveforms at VSW with fsw=fRES/7, fRES/5, and fRES/3,and VDD2 adaptively controlled by TX through feedback link. Figure 25.1.6: Efficiency measurement and performance comparison.

Figure 25.1.4: Schematic of the proposed isolated capacitive feedback link.

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• 2017 IEEE International Solid-State Circuits Conference 978-1-5090-3758-2/17/$31.00 ©2017 IEEE

ISSCC 2017 PAPER CONTINUATIONS

Figure 25.1.7: Chip micrographs with TX chip on the left and RX and capacitiveisolator chip on the right.



25.2 A 10MHz 3-to-40V VIN Tri-Slope Gate Driving GaN DC-DC Converter with 40.5dBμV Spurious Noise Compression and 79.3% Ringing Suppression for Automotive Applications

Xugang Ke1, Joseph Sankman1,2, Yingping Chen1, Lenian He3, D. Brian Ma1

1University of Texas at Dallas, Richardson, TX2Texas Instruments, Dallas, TX3Zhejiang University, Hangzhou, China

As power efficiency becomes essential in automotive applications, DC-DCconverters are widely employed [1]. However, size and thermal limits have madeit challenging to continue using standard CMOS-based converters. Gallium Nitride(GaN) FETs, on the other hand, have a much higher conductivity with smallsize/capacitance in comparison to silicon FETs, enabling a highly efficient powerconversion at high switching frequency (fSW). However, there are several issuesthat must be resolved before using GaN in automotive. High fSW incurs larger di/dtand dv/dt transitions which injects high frequency electromagnetic interference(EMI) noise into the input bus. This creates unwanted noise or even a malfunctionin a safety-critical system. A bulky input filter can reduce EMI, but it greatlyincreases size and cost. Several techniques [2-5] are reported to mitigate EMI.Frequency hopping using discrete frequencies is proposed in [2], but cannotspread the frequency evenly to lower the peak noise effectively. Alternatively, aseries resistor is typically added at the gate of the GaN FET to slow down thetransition [3-4]. However, the switching loss is dramatically increased. To mitigatethis, adjustable driving strength is proposed in [5]. Unfortunately, the sensingand driver delays confine its use in low fSW applications, where the switch noderising time is several tens or hundreds of ns. Another issue of high fSW operationis that it causes significant current and voltage spikes due to the parasitics at thedrain/source of the high side GaN FET (M H), which could lead to GaN VDS

breakdown or damage on logic-level FETs. Thus, EMI noise suppression andreliable operation of GaN FETs remain as major challenges in realizing high fSW

power converters for automotive-use.

Figure 25.2.1 shows the system architecture of the proposed high voltage (HV),high fSW, GaN-based buck converter for automotive applications. Rather thanemploying a fixed fSW, the converter uses a spurious noise compression (SNC)technique to generate randomly distributed frequencies within a sideband of Δfm

centered at f0. The energy at f0 and its harmonics (Nf0) are thus evenly spread,and the peak EMI noise is greatly compressed compared to the fixed fSW operationor frequency hopping techniques. With the SNC technique, the spurious noisefloor is greatly reduced over a wide frequency range, eliminating the need of thebulky input filter. Moreover, instead of solely using a fixed current (IGH) for gatedriving, an adaptive tri-slope gate driver charges VGH with a variable current (IM),which has three predefined current levels. An initial low charge current that isinversely proportional to load current (IO) pre-charges VGH, realizing a controlledIDH rising slope and a reduced current spike. In the second phase when VGH entersthe Miller plateau region, a current that is inversely proportional to input voltage(VIN) continues to charge VGH, achieving a controlled VSW rising slope and areduced voltage spike. After VSW approaches VIN closely, a large charge current isactivated to quickly pull up VGH to reduce the conduction loss in MH. This drivingscheme realizes the controlled rising slopes of IDH and VSW especially in high IO

and VIN scenarios, mitigating the huge spikes, which are unavoidable inconventional fixed driving scheme.

The SNC scheme is depicted in Fig. 25.2.2. With the random noise generated inan envelope generator, the main frequency of the clock (Vclk) in the SNC clockgenerator is modulated to create randomly distributed switching frequencies witha sideband of Δfm. Thus the noise spectrum generated at the main frequency andits harmonics are evenly distributed over the sidebands to achieve a compressedEMI noise floor. Figure 25.2.2 also shows the circuit implementation. A constantcurrent (Ib) charges Cfm, until VTR hits the high reference level VH. Then thecomparator CMP2 triggers high and starts to discharge Cfm. When VTR rampsdown and hits the low reference level VL, CMP2 resets to start the next cycle. Inthis way, a triangular envelope with a time period of Tmod is generated at VTR. Arandom noise signal that is acquired from the avalanche noise in Zener diode isamplified and further coupled to VTR. The common mode level of VTR is level-

shifted by If×Rref to achieve a modulated reference Vref (contains noise), which iscompared with a saw-tooth ramp Vramp. Vramp hits Vref in a randomized way, togenerate a Vclk with the frequencies randomly distributed with a sideband of Δfm.The rising edge of Vclk triggers the turn-on of high-side switch MH, and the fSW ismodulated similarly to compress the spurious noise and reduce the peak EMInoise effectively.

To mitigate the large IDH and VSW spikes during MH turn-on transition, an adaptivetri-slope gate driver (TSGD) is presented in Fig. 25.2.3. With lO and VIN detectedby an internal sensor, three different driving currents IM1, IM2 and IM3 are predefinedto provide a tri-slope charging profile of VGH. When VPWM goes down, VDH triggershigh and is level-shifted to the BST rail by a zero-IQ dynamic up level shifter. AfterVGL goes low, VGH starts to get charged initially with a current of IM1 that inverselyproportional to IO. After VGH reaches the threshold voltage Vth, MH starts conductingand IDH rises. At high IO with a low IM1, VGH charges from Vth to Vmp within a timeperiod of tp1 until MH enters the Miller plateau region. During tp1, the drain currentof MH is sensed by MT2 and is further compared with reference current of IB2.When IMT2 is larger than IB2, M2 turns on to increase the driving current by IM2

which is inversely proportional to VIN. At low IO with a high IM1, a less chargingtime of tp1’ (<tp1) is modulated before VGH reaches Vmp. In the second phase, VSW

rises with a gate charge current of IM2 (inversely proportional to VIN) until VSW

approaches VIN closely, and a time of tp2 results from high VIN. For low VIN, VSW ischarged up to VIN earlier resulting in a shorter tp2’ (<tp2). In this way, the risingslopes of IDH and VSW are adaptively adjusted, reducing the current/voltage spikesand suppressing EMI noise that injected to VIN. As VGH goes slightly higher than2Vth (predefined in this design), VP3 is pulled down by MT3 to enable a large chargecurrent IM3. With a much faster charging in tp3 period, VGH reaches to the final valuequickly to ensure a lower conduction loss.

A 0.86mm2 test chip is fabricated using a 0.35μm HV BCD process. Twoenhancement mode GaN FET switches are employed as power switches. At10MHz, the converter achieves a maximum IO of 1.2A over a wide VIN from 3V to40V. Figure 25.2.4 shows the measured VSW and EMI noise spectrum with SNCscheme. With the SNC, the peak EMI noise is reduced from 84.84dBμV to64.48dBμV with a 5% modulation range Δδ (=Δfm/f0). For Δδ=12%, the peak noiseis further reduced to 33.03dBμV. Figure 25.2.5 shows the measured rising edgesof VSW and VGH. With the TSGD, the maximum spike at VSW is reduced from 8.7Vto 1.8V at IO=1A, achieving a 79.3% ringing suppression. In VGH waveforms, tp1 ismodulated from 0.9ns to 2.5ns as IO increases. As VIN increases, tp2 varies from0.6ns to 2ns. The measured conductive EMI noise in a frequency range of 2MHzto 100MHz is shown in Fig. 25.2.6. Compared to a conventional converter, thepeak EMI noise at 10MHz is reduced from 84.73dBμV to 51.33dBμV with the SNCand further reduced to 44.23dBμV with TSGD. The overall noise reduction is40.5dBμV at 10MHz, 22.5dBμV at 90MHz, and 8.7dBμV at mid-frequency rangeof 15MHz to 70MHz. The gate driver consumes a power of 39.5mW at 10MHz.Figure 25.2.6 shows the comparison with the prior arts. It achieves 9× wider VIN,1.5× higher fSW and 1.5× reduction in peak spurious noise in comparison with [2].Compared to [3-4], the EMI noise is greatly reduced. The peak efficiency is 85.5%for 12V-to-5V conversion. The die micrograph is shown in Fig. 25.2.7.

Acknowledgements:The authors would like to thank Texas Instruments for IC fabrication support.

References:[1] Texas Instruments Application Notes: “Automotive Infotainment Guide”, 2016,<http://www.ti.com/lit/sl/ssay002d/ssay002d.pdf>.[2] C. Tao, et al., “Spurious-noise-free buck regulator for direct powering ofanalog/RF loads using PWM control with random frequency hopping and randomphase chopping,” ISSCC Dig. Tech. Papers, pp. 396-398, Feb. 2011. [3] M. K. Song, et al., “A 20V 8.4W 20MHz four-phase GaN DC-DC converter withfully on-chip dual-SR bootstrapped GaN FET driver achieving 4ns constantpropagation delay and 1ns switching rise time,” ISSCC Dig. Tech. Papers, pp.302-303, Feb. 2015. [4] X. Ke, et al., “A 3-to-40V 10-to-30MHz automotive-use GaN driver with activeBST balancing and VSW dual-edge dead-time modulation achieving 8.3% efficiencyimprovement and 3.4ns constant propagation delay,” ISSCC Dig. Tech. Papers,pp. 302-303, Feb. 2016. [5] M. Rose, et al., “Adaptive dv/dt and di/dt control for isolated gate powerdevices”, Energy Conversion Congress and Exposition, pp. 927-934, Sept. 2010.

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Figure 25.2.1: Proposed spurious noise compression and ringing suppressiontechniques in HV, high fSW GaN DC-DC converters.

Figure 25.2.2: Spurious noise compression (SNC) scheme with key operationwaveforms.

Figure 25.2.3: Implementation of adaptive tri-slope gate driving (TSGD) duringMH turn-on transition.

Figure 25.2.5: Measurement of VSW ringing suppression, and VGH with TSGD indifferent IO and VIN conditions.

Figure 25.2.6: Conductive EMI noise measurement and performancecomparison.

Figure 25.2.4: Measured key transient points of VSW and noise spectrum withSNC scheme.

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Figure 25.2.7: Chip micrograph.



25.3 A 1.3A Gate Driver for GaN with Fully Integrated Gate Charge Buffer Capacitor Delivering 11nC Enabled by High-Voltage Energy Storing

Achim Seidel, Bernhard Wicht

Reutlingen University, Reutlingen, Germany

More and more power electronics applications utilize GaN transistors as theyenable higher switching frequencies in comparison to conventional Si devices.Faster switching shrinks down the size of passives and enables compact solutionsin applications like renewable energy, electrical cars and home appliances. GaNtransistors benefit from ~10× smaller gate charge QG and gate drive voltages inthe range of typically 5V vs. ~15V for Si.

Highly integrated gate drivers still require an external buffer capacitor Cext in therange of 100nF to buffer the drive voltage at turn-on, Fig. 25.3.1. In case of fastswitching, the effectiveness of Cext is severely reduced, as there is always someparasitic inductance in series. The driver presented in [1] uses transmitted RFenergy to directly drive the gate without any buffer capacitor, but the drivingcapability is limited by the transmitted energy. The GaN driver in [2] utilizes a fullyintegrated buffer capacitor, but it supports only small gate charge in the range of100pC. This work presents a fully integrated GaN gate driver that utilizes high-voltage energy storing (HVES) in a resonant tank in order to support gate charges>10nC.

The proposed gate driver (Fig. 25.3.1 bottom), comprises a fully integrated high-voltage energy charge storing (HVES) circuit, consisting of an LC-tank (LHV,CHV), connected to a high-voltage supply VHV, sub-regulated from VIN. VHV canbe adjusted externally by the signal VRef. VIN is usually generated by externalbootstrapping or via a transformer. LHV = 14nH in thick copper is stacked ontoCHV = 600pF without layout area penalty, covering an area of 1.44mm2 (Fig. 25.3.1top right). If the gate control signal IN is activated (timing diagram in Fig. 25.3.1),MN1 turns on and CHV discharges over LHV and the active rectifier and deliversa current pulse Idrv with the required charge QG onto gate G. A gate resistor Rgonis not required anymore. [3] proposes the concept of high-voltage charge storing(HVCS) in order to integrate the buffer capacitor. However, as there is no resonantoperation, relatively high energy losses occur in the resistive charging path. HVESinstead utilizes a resonant concept to fully transfer the stored CHV energy to nodeG, assuming ideal components. Since the energy in CHV is proportional to VHV2,the proposed HVES concept is suitable for a broad range of high-voltage as wellas low-voltage / high-current GaN types. Unlike conventional resonant gate driveconcepts, VHV can be chosen significantly higher than the actual gate drivevoltage, resulting in much higher QG.

A parallel low voltage buffer, comprising P1, N1, keeps the GaN switch safelyturned on at the end of the transition. The low-voltage capacitor CLV = 1.7nF isplaced below CHV (see Fig. 25.3.1 top right). The GaN transistor is turned off bythe low voltage buffer via N1 with Idrv, adjustable by Rgoff.

Figure 25.3.2 (top right) shows the VHV recharge control circuit. The capacitorCHV is charged from VIN via 30V DMOS transistors N1, N2. The back-to-backconfiguration of N1, N2 prevents discharge of CHV into VIN via N1’s body diodein case VIN drops below VHV. At low switching frequencies and at startup, CHVis charged directly via a bypass resistor R1=10kΩ. CHV is disconnected from VINif IN = 1, i.e., at turn-on of the GaN switch. Recharge mode (Charge_EN=1) isentered after G rises with a delay. In this case N3 is turned-off and P1 connectsG12 to VIN via a bootstrap diode D3, controlled over C1. D3 prevents a chargeback-flow to VIN, if G12 exceeds VIN. The proposed recharge control circuitenables CHV recharge over most of the switching period, even while the driver isturned on (Charge_EN in the timing diagram of Fig. 25.3.1) to support short off-times (<30ns) of the GaN transistor. If VHV reaches the target voltage, thecharging stops. A feedback divider and COMP1 form a hysteretic control loop,that keeps VHV within a target window of 2% of VHV. Since the recharge of CHVis very fast, the comparator current is increased in recharge mode, to achieve asmall comparator response time.

The MN1 control and supply circuit (Fig. 25.3.2 bottom) turns on MN1 via MN2,controlled by level shifter LS. D2 prevents discharging of the MN2 gatecapacitance, when node GMN1 rises. D3 ensures 5V-over-voltage protection forN4. As MN2 turns off, the Charge Completion block pulls GMN1 to its final level,V5f (5V). The floating supply V5f is generated by two cascaded shunt regulators.The small Shunt Regulator 1 rapidly resets capacitor CS of the larger ShuntRegulator 2 to its target value at CB1 recharge. CB1 and CB2 are stacked devices.

The low-voltage transistor NAR acts as an active rectifier (Fig. 25.3.2 bottom right)that turns off via N6 and R1 once VHV falls below the GaN gate voltage G at eachturn-on transition. R1 causes a short delay, to keep NAR ideally active until itsdrain current reaches zero. The gate of the cascode N6 is protected by P7. WhenVHV rises, the cascode N7 turns off and GN6 is pulled to V5f via R2. At the endof the switching cycle, MN1 gets turned off (LSout = ’low’). P8 shorts R2 for afaster activation of N6 and N7 pulls the gate of NAR fully to V5f.

The driver has been implemented in a 180nm BCD technology. The transientcurves in Fig. 25.3.3 show that VHV drops from VHVinit below the 5V gate drivevoltage to VHVmin as expected. VHV recharges in about 130ns, ready to start thenext switching cycle. At a target peak current of 1.3A the gate is charged very fastwithin ~7ns. The tight gate voltage maximum ratings for GaN usually requireparticular precautions in the design [2]. The bottom right diagram shows that thegate voltage of the proposed concept is not very sensitive on VHV variations. Thestandby power consumption of the IC is ~300μA.

Figure 25.3.4 (top) shows the gate charge allocation QG. The graph includes thecalculated data for a conventional gate driver and for high-voltage charge storing(HVCS) [3]. HVES achieves a gate charge of up to 11nC, which is 13× more thana conventional 5V capacitor with the same layout size (1.7nF) could provide. Thebottom left diagram indicates a QG gain of more than 40% in comparison to HVCSover the whole range of VHV with a peak value of 47%. The efficiency of the HVESconcept (bottom right) is 1.3× superior to HVCS. The efficiency is calculated asthe ratio of the energy in the charged node G (Eout) to the incoming energy fromCHV (Ein), during a driver turn-on event. The overall efficiency is mainlydetermined by the parasitic resistances in the charging path, associated with LHV(1.35Ω), MN1 (0.8Ω), NAR (0.35Ω).

The transients in Fig. 25.3.5 show a steep rising transition and confirm the HVESoperation. The falling edge is determined by the resistive load, discharging VSWmore slowly. Very short on-/off-times are achieved at a maximum switchingfrequency of 3MHz (Fig. 25.3.6 top). The comparison with prior art in Fig. 25.3.6indicates that the proposed driver is able to deliver nearly 83× more gate chargethan [2][4] and 45× more gate charge than [3]. This results in a superior value of7.6nC/mm² buffer cap area, which is approximately two times larger than achievedin [3].

References:[1] S. Nagai, et al., "A DC-isolated gate drive IC with drive-by-microwavetechnology for power switching devices," ISSCC Dig. Tech. Papers, pp. 404-406,Feb. 2012.[2] X. Ke, et al., "16.8 A 3-to-40V 10-to-30MHz automotive-use GaN driver withactive BST balancing and VSW dual-edge dead-time modulation achieving 8.3%efficiency improvement and 3.4ns constant propagation delay," ISSCC Dig. Tech.Papers, pp. 302-304, Feb. 2016.[3] A. Seidel, et al., "Area efficient integrated gate drivers based on high-voltagecharge storing," IEEE J. Solid-State Circuits, vol. 50, no. 7, pp. 1550-1559, July2015.[4] M. K. Song, et al., “A 20V 8.4W 20MHz four-phase GaN DC-DC converter withfully on-chip dual-SR bootstrapped GaN FET driver achieving 4ns constantpropagation delay and 1ns switching rise time,” ISSCC Dig. Tech. Papers, pp.302-303, Feb. 2015.

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Figure 25.3.1: Conventional gate driver (top left), proposed gate driver (bottom)and inductor / capacitor placement (top right). Figure 25.3.2: Gate driver circuits.

Figure 25.3.3: Measured gate driver switching waveforms and VG vs. VHVdiagram for a 60A GaN FET including test setup.

Figure 25.3.5: Measured transient operation of the proposed gate driver.Figure 25.3.6: Minimum and maximum gate drive pulse width measurement(top) and comparison table to prior work (bottom).

Figure 25.3.4: Gate charge allocation and efficiency of the proposed HVESdriver in comparison to state-of-the art concepts.

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Figure 25.3.7: Die micrograph with an active area of 2.4mm × 1.0mm.



25.4 A 500Mb/s 200pJ/b Die-to-Die Bidirectional Link with 24kV Surge Isolation and 50kV/μs CMR using Resonant Inductive Coupling in 0.18μm CMOS

Subhashish Mukherjee1, Anoop Narayan Bhat1, Kumar Anurag Shrivastava1, Madhulatha Bonu1, Benjamin Sutton2, Venugopal Gopinathan1, Ganesan Thiagarajan1, Abhijit Patki1, Jhankar Malakar1, Nagendra Krishnapura3

1Texas Instruments, Bangalore, India2Texas Instruments, Dallas, TX3IIT Madras, Chennai, India

Chip based digital isolators are being developed for higher speed and higherisolation capabilities [1, 2]. These make use of various coupling mechanisms suchas capacitive coupling [3] and transformer coupling [4]. A limitation of thesetechnologies is that they need to maintain a low separation (distance throughinsulation DTI<30μm) through high quality insulators (oxides, polyamides) inorder to achieve data rate and isolation performance [2]. These require expensivespecial process development and special packaging techniques to meet reinforcedisolation recommended by IEC 60747-5-5 and VDE 0884-10. Other high-speeddie-to-die communication techniques implemented using millimeter-wave andoptical solutions are expensive and not designed for isolation. In this work, anisolation technique is proposed where two standard 180nm CMOS dies placedside by side with DTI of more than 500μm, and co-packaged using regular planarMCM flow with package mold compound being the isolation material, achieveasynchronous bidirectional link with >24kV surge isolation capability and greaterthan 500Mb/s at 175pJ/b. Channel gain is maximized using resonance. Gain isdecoupled from channel bandwidth by resetting the channel state variables. Thishelps in enhancing data rate well beyond what is implied by the bandwidth.

As shown in Fig. 25.4.1, dies 1 and 2 placed side by side on the package substrate,separated by 0.5mm, communicate through weak magnetic coupling (coefficientk~1%) between on-die coils. To overcome the low coupling coefficient, coils onboth the dies are tuned to the same resonance frequency and passive gainprovided by Q of the tanks is utilized to boost the signal. A carrier applied to theprimary at the resonance frequency gets picked up by the secondary tank with asteady state gain of kQ2 when both primary and secondary have the same qualityfactor Q. A Q between 6 and 10 is targeted in our application.

The high Q used to maximize gain has a negative effect in lowering bandwidthand hence the data rate through the channel. With a resonance frequency f0, thebandwidth is (f0/Q)×(20.5−1)0.5. The data rate of traditional on-off keying throughthis channel is about the same, i.e. ~ f0/16 for Q=10. In this paper, a technique isproposed to increase the data rate to about f0/4 b/s for the same gain.

Figure 25.4.2 shows the block diagram of full duplex communication systemthrough the isolation barrier. Coils in the two channels are tuned to two differentresonance frequencies, 2GHz and 1.3GHz, in order to avoid cross talk. A datatransition edge (1→0 or 0→1) triggers the transmit driver to generate a set ofpre-determined carrier pulses (3 carrier pulses in our implementation) whichcauses the primary tank to ring. Subsequently S1 is opened to rapidly clear theTX tank memory by decreasing its Q and widening its bandwidth. In response,the RX coil oscillates and the system amplifies the signal until the detector circuitsdetect change of state. At this point, memory of all RX circuits including RX tankcoil is rapidly cleared by closing S2 and widening its bandwidth. Pulse VRXrst iskept sufficiently wide such that VRX discharges completely and the same bit is notreceived twice, and is sufficiently narrow to avoid interference with the next bit.

Figure 25.4.3 shows different blocks used in the transmitter. Ring oscillatorstuned to 2GHz and 1.3GHz are used to drive the two transmitters. A state machinestarts the oscillator at the data edge and runs through 3 cycles (2 cycles for the1.3GHz case) before resetting the transmitter. The received signal is amplified bya 2-stage PGA (Fig. 25.4.2). Each stage of the PGA is implemented as a broadband

fully differential gmR stage with programmable gain. The amplified signal is fedto a full-wave rectifier and peak detector. As shown in Fig. 25.4.3, NMOS/PMOSpairs detect positive/negative peak of the input signal. Biasing circuit to obtain aprocess and temperature independent no-signal (DC) bias voltage (Vop−Vom)DC isalso shown. The pseudo-differential outputs Vop and Vom are fed to a comparatorwith hysteresis (Fig. 25.4.2). The comparator drives the delay block, whichgenerates the reset signal for the receive channel. A following decoder convertsthe transition coded signals into data levels.

A thick copper layer, typically used for power routing, is used to form the coils.The coil dimensions are calculated such that a decent (1%) coupling is establishedbetween the dies. The dimensions depend on die-to-die spacing. Self-resonancefrequencies of the coils need to be greater than carrier frequencies. The activecircuits are located within the coils (Fig. 25.4.7).

Eddy current flowing in the solid package leadframe severely limits the couplingbetween dies. A grooved leadframe is designed with grooves perpendicular to thecoil windings (Fig. 25.4.4). This virtually eliminates package related coupling loss.Scribe seal around the die creates an induced current, which again reducescoupling. The scribe wall is cut (10μm slit) at strategic locations to significantlyreduce the eddy current without compromising ion ingress. Since the scribe walltouches the substrate, it was put in PSD and NWELL to remove low resistanceDC ground paths.

Frequency separation alone is not enough to suppress crosstalk between TX andRX on the same die to a level required for full duplex communication. The transmitcoils are given a twist as shown in Fig. 25.4.7 so that the transmit signal (flux)cancels itself for the adjacent same-die coil, without significantly altering theforward coupling to the other die. A wideband cancellation is achieved since itonly depends on coil geometry.

A full-duplex test chip was implemented in a 180nm digital CMOS process andpackaged as an MCM in a 24-pin SOIC package. Measured isolation performancewas surge rating of more than 24kV and CMR of 50kV/μs (compared to 10kVneeded for reinforced isolation). An eye opening of more than 75% can be seenin Fig. 24.4.5 at 500Mb/s data rate for 2GHz channel. The chip was able to toleratean external EM field of 5V/m (level 2 of IEC-61000-4-3). The emission from thechip was measured to be below the permissible level recommended by FCC forclass B digital devices at all frequencies. Fig. 25.4.6 summarizes the performanceand compares it to other devices in the literature. The proposed device achieveshigher isolation and higher data rate with better energy efficiency.

A digital isolation technology using standard CMOS process, standard MCM flow,and package mold compound as isolation demonstrates a bidirectional link withstate-of-the-art isolation performance at 500Mb/s. A technique to increase datarate beyond traditional limits through narrow band channels has beenimplemented achieving an efficiency of 175pJ/b at a die-to-die distance of 500μm.

Acknowledgements:The authors thank Mahesh Mehendale, Sreenivasan Koduri, Shankar RamNarayana Moorthy, E Anjan Prasad, Sarangan Valavan, Raja Selvaraj and TomBonifield for their help on this project.

References:[1] P. Lombardo, et al., “A Fully-Integrated Half-Duplex Data/Power TransferSystem with up to 40Mbp/s Data Rate, 23mW Output Power and On-Chip 5kVGalvanic Isolation,” ISSCC Dig. Tech. Papers, pp. 300-301, Feb. 2016.[2] S. Kaeriyamaet, et al., “A 2.5kV Isolation, 35kV/μs CMR, 250Mbps,0.13mA/Mbps Digital Isolator in Standard CMOS with an On-Chip SmallTransformer,” IEEE Symp. VLSI Circuits, pp. 197-198, 2010.[3] P. Mahalingam, et al., “Manufacturing Challenges and Method of Fabricationof On-Chip Capacitive Digital Isolators,” IEEE Int. Symp. On SemiconductorManufacturing, ISSM Paper: PO-P-020, pp. 1-4, Oct. 2007.[4] R. Kliger, “Integrated Transformer-Coupled Isolation,” IEEE Instrumentation& Measurement Magazine, pp. 16-19, 2003.

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Figure 25.4.1: Loosely inductive-coupled coplanar dies and coils tuned at sameresonance frequency to enhance signal strength. A unidirectional link is shown.

Figure 25.4.2: Communication protocol and data rate enhancement techniquealong with full duplex system architecture.

Figure 25.4.3: Transmitter modulator and Receiver full-wave rectifier andpseudo differential peak detector circuit with reset.

Figure 25.4.5: Measured Eye diagrams. Figure 25.4.6: Performance summary and comparison.

Figure 25.4.4: 3-D Model of Grooved Leadframe with dies and X-ray of thepackaged dies.

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Figure 25.4.7: Micrograph of the two dies in the MCM showing duplex channelsand coil structures.

Session 25 Overview: GaN Drivers and Galvanic Isolators

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