Session 08 v.3

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Session Eight

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Cairo-Egypt

Version 03 – June 20121


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about Start Group

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Mahmoud AbdellatifAlaa Salah Shehata Mohamed SalahMohamed Talaat

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+ 02 0122-4504158 M.A www.youtube.com/StartGroup2011+ 02 0128-0090250 A.S

Session Eight



Outline

Session Eight 3

Evaluation Test

Arithmetic circuits Projects Discussion

8



Outline

Session Eight 4

Evaluation Test




Evaluation Test

Session Eight 5

Answer all questions in the following paperQuestions : 50 Question Time : 30 minuteFull Mark : 100 degree



Outline

Session Eight 6

Evaluation Test




Unsigned and Signed Types

Session Eight 7

Behave exactly like STD_LOGIC_VECTORThey determine whether a given vector should be treated as a signed or unsigned number.

Definition

Package ieee.numeric_std.all

0 to 2N - 1Unsigned

- 2(N-1) to 2(N-1) – 1 2's Complement numberSigned

signal A : unsigned(3 downto 0) ;signal B : signed(3 downto 0) ;

A <= "1111" ; -- 15B <= "1111" ; -- -1

Example



Unsigned and Signed Types

Session Eight 8

Z_signed <= A_signed + "1010"; Error -6 or 10

Ambiguous Expressions

Ambiguous

Solution Z_signed <= A_signed + signed("1010“);



Adders with Carry In

Session Eight 9

A(3:0) + B(3:0) + Carry-InResult

Algorithm A(3:0) , ‘1’ B(3:0) , Carry-In--------------------Result(4:1)

CodeSignal A,B,Y : unsigned (3 downto 0);Signal Z : unsigned (4 downto 0);Signal cin : std_logic;.....Z <= (A & ’1’) + (B & cin);Y <= Z(4 downto 1 );

011 1001 1------- cin =1101 0

011 1001 0------- cin =0100 0



Adders with Carry Out

Session Eight 10

Result + Carry-OutResult

Algorithm ‘0’ A(3:0) ‘0’ B(3:0) ---------------------Cout Result(3:0)

Code Signal A,B,Y : unsigned (3 downto 0);Signal Z : unsigned (4 downto 0);Signal co : std_logic;…..Z <= (’0’ & A) + (’0’ & B);Y <= Z(3 downto 0 );Co <= Y(4);

0 1110 100-------1 011



Type Conversions

Session Eight 11

Signed & Unsigned (elements) Std_LogicSigned & Unsigned Std_Logic_VectorSigned & Unsigned IntegerStd_Logic_vector Integer

Conversion functions located in Numeric_Std

Conversion



Unsigned.Signed Std_Logic

Session Eight 12

Conversions Converted automatically.

ExampleA_std <= J_unsigned(0);B_std <= K_signed(7); --not preferred

L_unsigned(0) <= C_std;M_signed(2) <= N_std(2);



Unsigned.Signed Std_Logic_vector

Session Eight 13

Conversions Use type casting to convert equal sized arrays

ExampleA_std <= std_logic_vector( B_unsigned ) ;C_std <= std_logic_vector( D_signed ) ;

G_unsigned <= unsigned( H_std ) ;J_signed <= signed( K_std ) ;



Unsigned.Signed Integer

Session Eight 14

Conversions Use conversion functions

ExampleSignal A,B : integer;Signal A_unsigned : unsigned(7 downto 0);Signal B_signed : signed(7 downto 0);…A <= TO_INTEGER ( A_unsigned ) ;B <= TO_INTEGER ( B_signed ) ;

A_unsigned <= TO_UNSIGNED ( A, 8) ;B_signed <= TO_SIGNED ( B, 8) ;

Data <= ROM(( TO_INTEGER( Addr_uv));



Std_logic_vector Integer

Session Eight 15

Conversions Use conversion functions + type casting i.e. Needs 2 steps.

Example Signal A,B : integer;Signal A_std : std_logic_vector (7 downto 0);Signal B_std : std_logic_vector (7 downto 0);….A <= to_integer( unsigned( A_std ));B <= to_integer( signed( B_std ));

A_std <= std_logic_vector( to_unsigned( A, 8 ));B_std <= std_logic_vector( to_signed( B, 8 ));



Session Eight 16

VHDL is Strongly typed <= Less Errors ;

Strong Typing Strong Error Checking Built into the Compiler Less debugging.

Without VHDL, you must have a good Testbench+ lots of time to catch your errors.

You may notice that Verilog is much more easier than VHDL.



Multiplication and Division

Session Eight 17

/ mod rem **Operators

Signal * Constant Z_unsigned <= A_unsigned * 2 ;

Size of result = 2 * size of input signal

Signal* Signal Signal A_unsigned : unsigned (7 downto 0);Signal B_unsigned : unsigned (7 downto 0);Signal Z_unsigned : unsigned (15 downto 0);Z_unsigned <= A_unsigned * B_unsigned ;

Size of result = size of 1st signal + size of 2nd signal

/ mod rem are not synthesisSynthesis



Example 31

Session Eight 18

Signed Adder

LIBRARY ieee ; USE ieee.std_logic_1164.all ; USE ieee.numeric_std.all ; --------------------------------------- ENTITY adder IS PORT (

Cin : IN STD_LOGIC ; X,Y : IN STD_LOGIC_VECTOR(15 DOWNTO 0); S : OUT STD_LOGIC_VECTOR(15 DOWNTO 0));

END adder ; --------------------------------------- ARCHITECTURE Behavior OF adder IS

SIGNAL Xs,Ys : SIGNED(15 DOWNTO 0); SIGNAL Sum : SIGNED(15 DOWNTO 0);

BEGIN Xs <= signed(X); Ys <= signed(Y); Sum <= Xs + Ys + Cin ; S <= std_logic_vector(Sum);

END Behavior ;



Not Recommended

Session Eight 19

Signed Adder

LIBRARY ieee ;USE ieee.std_logic_1164.all ;USE ieee.std_logic_signed.all ;---------------------------------------ENTITY adder ISPORT ( Cin : IN STD_LOGIC ;

X, Y : IN STD_LOGIC_VECTOR(15 DOWNTO 0) ;S : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)) ;

END adder ;---------------------------------------ARCHITECTURE Behavior OF adder IS BEGIN

S <= X + Y + Cin ;END Behavior ;



Not Recommended

Session Eight 20

Signed Adder

ENTITY adder16 ISPORT (X,Y: IN INTEGER RANGE -32768 TO 32767 ; S : OUT INTEGER RANGE -32768 TO 32767 ) ;END adder16 ;---------------------------------------ARCHITECTURE Behavior OF adder16 IS BEGIN

S <= X + Y ;END Behavior ;



Example 32

Session Eight 21

UnSigned Adder

LIBRARY ieee ; USE ieee.std_logic_1164.all ; USE ieee.numeric_std.all ; --------------------------------------- ENTITY adder IS PORT (

Cin : IN STD_LOGIC ; X,Y : IN STD_LOGIC_VECTOR(15 DOWNTO 0); S : OUT STD_LOGIC_VECTOR(15 DOWNTO 0));

END adder ; --------------------------------------- ARCHITECTURE Behavior OF adder IS

SIGNAL Xus,Yus : UnsIGNED(15 DOWNTO 0); SIGNAL Sum : UnSIGNED(15 DOWNTO 0);

BEGIN Xus <= Unsigned(X); Yus <= Unsigned(Y); Sum <= Xus + Yus + Cin ; S <= std_logic_vector(Sum);

END Behavior ;



Example 33

Session Eight 22

Multiplier

LIBRARY ieee;USE ieee.std_logic_1164.all; USE ieee.numeric_std.all ;---------------------------------------entity multiply isport( a : in STD_LOGIC_VECTOR(7 downto 0); b : in STD_LOGIC_VECTOR(7 downto 0); cu : out STD_LOGIC_VECTOR(15 downto 0); cs : out STD_LOGIC_VECTOR(15 downto 0));end multiply;---------------------------------------architecture rtl of multiply is

SIGNAL sa: SIGNED(7 downto 0);SIGNAL sb: SIGNED(7 downto 0);SIGNAL sc: SIGNED(15 downto 0);

SIGNAL ua: UNSIGNED(7 downto 0);SIGNAL ub: UNSIGNED(7 downto 0); SIGNAL uc: UNSIGNED(15 downto 0);

begin

-- signed multiplicationsa <= SIGNED(a);sb <= SIGNED(b);sc <= sa * sb;cs <=

STD_LOGIC_VECTOR(sc);

-- unsigned multiplicationua <= UNSIGNED(a);ub <= UNSIGNED(b); uc <= ua * ub;cu <=

STD_LOGIC_VECTOR(uc);

end rtl;



Example 34

Session Eight 23

Half Adder

LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;---------------------------------------ENTITY HALF_ADDER ISGeneric (WIDTH : INTEGER := 8 );PORT( A : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0 );

B : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0 );P : OUT STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0 );G : OUT STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0 ));

END HALF_ADDER;---------------------------------------ARCHITECTURE RTL OF HALF_ADDER ISBEGIN

P <= A XOR B;G <= A AND B;

END;



Example 35

Session Eight 24

Full Adder

LIBRARY ieee; USE ieee.std_logic_1164.all;---------------------------------------ENTITY fullAdder IS PORT( In1, In2, CarryIn : IN std_logic;

Sum : OUT std_logic; CarryOut : OUT std_logic);

END fullAdder; ---------------------------------------ARCHITECTURE expr OF fullAdder IS

signal temp : std_logic; BEGIN

temp <= In1 XOR In2; Sum <= temp XOR CarryIn;

CarryOut <= (In1 AND In2) OR (CarryIn AND temp);END expr;



Lab 10

Session Eight 25

Title:Using Arithmetic operators

Goal: Multipliers Adders



Lab 10

Session Eight 26

Describe code performing this function

C = A + B*2A,B and C are of width = 16 signed bits

C = B*AA,B and C are of width = 16 signed bits



Outline

Session Eight 27

Evaluation Test




Time for Your Questions

Session Eight 28

Examples Exercises Labs31-35 - 10



Take Your NotesPrint the slides and take your notes here

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Session Eight 29



See You Next Session .. Don’t miss

Thank

YouSession Eight 30

Session 08 v.3

Technology

Transcript of Session 08 v.3