Serializer ASIC design at SMU

Andy Liu on behalf of the SMU group

December 6, 2011LAr Week, CERN

Optical link Overview

ADC Data

Multiplexers Serializers

Laser drivers

VCSELs

Optical fibers

TIAPIN

diodeLD

deserializer

Optical Links

Trans-impedance amplifiers FPGA

Off-detector, COTS

Optical transmitters

Optical receivers

On-detector, rad tol

LOCs1 Review

T. Liu- Southern Methodist UniversityTIPP 2011 – 11 June 2011 – Chicago, Illinois

5 Gbps

• Process: fabricated in a commercial 0.25 μm Silicon-on-sapphire (SoS) CMOS technology

• Input: 16 bit parallel data and 1 clock, LVDS• Output: 1 bit serial, CML• Operation range: 4.0 – 5.7 Gbps • Power dissipation: 463 mW • Radiation tolerant

3 mm

3 m

m

4

LOCs2 block diagram + Status• In design:

– 2-ch serializers, 8 Gbps/ch

– 4-ch VCSEL driver array, 8 bps/ch

• Status:– All fast blocks in CML

logic done (dark green)

– Other parts in light green have been verified in LOCs1, under fine tuning.

– Single channel VCSEL driver done, moving to an (open drain) driver array

– The LVDS receiver will need to be checked

6 Dec 2011, LAr Week, CERNLiu@SMU

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CML circuits in LOCs2• The CML Driver has been changed to 5 stages and 3.3V power supply to

improve performance in jitter and amplitude. • Designed low speed CML divider and CML multiplexer circuits to replace

CMOS circuits in Stages 2 and 3 multiplexers to reduce noise and power consumption.

6 Dec 2011, LAr Week, CERN

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Test the CML circuits

• Tested all high speed CML circuits in a test bench shown below. The overall DJ is about 14 ps (p-p) at typical corner 27 C.

Test schematic of all high speed CML circuits

6 Dec 2011, LAr Week, CERN

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The VCSEL driver• A single channel VCSEL driver operating at 8 Gbps has been designed. • A 4-channel VCSEL driver matching a VCSEL array is under development.

Will expand to 12 channel once proved successful. Limited by MPW.

an eye diagram at 8 Gbps (post layout simulation, DJ < 6 ps)

the schematic of a VCSEL driver (only the last two stages shown)

Vctrl

Vi_p

Vi_n

Bias

Vo_pVo_n

VDD

M1 M2

M3 M4

M5 M6

M7 M8

R2R1

6 Dec 2011, LAr Week, CERN

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Adjustable Active Peaking • Proposed using an external voltage to adjust the peaking strength. The

control will be moved inside the chip in the final version (using DAC).

1.7 1.75 1.8 1.85 1.9 1.95 2 2.05 2.10

2

4

6

8

10

12

14 Inductance effect on jitter, 3.3V postlayout

L=1nHL=2nHL=3nHL=4nH

Control voltage (V)

Jitter

(ps)

6 Dec 2011, LAr Week, CERN

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Plan

• Initially planned to submit (MPW run) in March 1, 2012, now the designers would like to move that to May 1, 2012.

• The designers would like to request a review organized by LAr sometime in Jan./Feb. time frame.

• We have started looking into the packaging issue, together with the array optical transmitter development. Will report next time.

6 Dec 2011, LAr Week, CERN