Serial Peripheral Interface Module MTT48 8-1 M SERIAL PERIPHERAL INTERFACE (SPI)
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Transcript of Serial Peripheral Interface Module MTT48 8-1 M SERIAL PERIPHERAL INTERFACE (SPI)
Serial Peripheral Interface Module MTT48 8-1M
SERIALPERIPHERALINTERFACE
(SPI)
Serial Peripheral Interface Module MTT48 8-2M
Module Objective
Understand SPI format and data transfersgure the control registers
Transmit and receive data
Module exercise:
Configure the SPI to transmit and receive characters to/from another
device in Master mode at a 1 MHz rate
Serial Peripheral Interface Module MTT48 8-3M
SERIAL PERIPHERAL INTERFACE MODULE68HC08
CPU
SystemIntegration
Module(SIM)
ClockGeneration
Module(CGM)
TimerInterfaceModule(TIM)
DirectMemoryAccessModule(DMA)
SerialCommunications
Interface(SCI)
Internal Bus (IBUS)
SerialPeripheralInterface
(SPI)
RandomAccess
Memory(RAM)
ElectronicallyProgrammable
ROM
LVI
COP
Monitor ROM
IRQ
BREAK
RESET
• Features of the SPI module include the following:
• Full-Duplex Operation
• Master and Slave Modes
• Separate Transmit and Receive Registers
• Four Master Mode Frequencies (Maximum = Bus Frequency 2)
• Maximum Slave Mode Frequency = Bus Frequency
• Separate Clock Ground for Reduced Radio Frequency (RF) Interference
• Serial Clock with Programmable Polarity and Phase
• Bus Contention Error Flag
• Overrun Error Flag
• Two Separately Enabled Interrupts with DMA or CPU Service:SPRF (SPI Receiver Full)SPTE (SPI Transmitter Empty)
• Programmable Wired-OR Mode
• I2C (Inter-Integrated Circuit) Compatibility
Serial Peripheral Interface Module MTT48 8-4M
SPI I/O Registers
Three registers control and monitor SPI operations:
• SPI Control Register (SPCR)
• SPI Status and Control Register (SPSCR)
• SPI Data Register (SPDR)
Serial Peripheral Interface Module MTT48 8-5M
SPI Modes
Master mode
• Only a master SPI initiates a transmission
• Data is shifted out via Master Out Slave In (MOSI) line
• Data is shifted in via Master In Slave Out (MISO) line
• Transmission ends after 8 cycles of serial clock (SPSCK)
Slave Mode
• Transfer synchronized to serial clock (SPSCK) from Master
• Data is shifted in via the Master Out Slave In (MOSI) line
• Data is shifted out via the Master In Slave Out (MISO) line
Serial Peripheral Interface Module MTT48 8-6M
Slave Select Pin
SS
Shift Register Shift Register
MOSI
MISO
+5vSS
MASTER SLAVE
Baud Rate Gen.
SPSCK
Slave Select (SS)
• Master mode– SS held high during transmission– Acts as error detection input– Can be general purpose output
• Slave mode– SS must remain low until transmission completes
0 = Enables slave1 = Disables slave
Serial Peripheral Interface Module MTT48 8-7M
SPI Control Register
SPI Control Register (SPCR)
• SPI Master (SPMSTR)– Selects master mode or slave mode operation
1 = Master mode
0 = Slave mode
• SPI Master and Slave need identical clock polarity and
phase settings
• Clock Polarity (CPOL)– Determines clock state when idle
• Clock Phase (CPHA)
1 = Begin capturing data on second clock cycle edge
0 = Begin capturing data on first clock cycle edge*– When CPHA = 0, the SS must be deasserted and reasserted
between each transmitted byte
RESET: 0 0 0 0 1 0 0 0
WRITE:
READ: SPRIE DMAS SPMSTR CPOL CPHA SPWOM SPE SPTIESPCR
• SPI Enable (SPE)
1 = SPI module enabled
0 = SPI module disabled
Recommend disabling SPI before initializing or
changing clock phase, clock polarity, or baud
rate
Serial Peripheral Interface Module MTT48 8-8M
Clock Polarity and Phase
SPI Control Register (SPCR)
• SPI modules need identical Clock polarity and phase
CPHA
1
0
1
CPOL
0 0
0
1
1
MSB Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 LSBMOSI/MISO
Capture Strobe
SPSCK
SPSCK
SPSCK
SPSCK
SS
Serial Peripheral Interface Module MTT48 8-9M
SPI Baud Rate
SPI Status and Control Register (SPSCR)
• SPI rate select bits (SPR1, SPR0)– Sets the Master SPSCK clock frequency– No effect in the Slave devices– Baud Rate = CGMOUT / Baud Rate Divisor
SPR1:SPR0Divided By
System Clock(System Clock Freq. = 8 MHz)
Baud Rate
00
01
10
11
2
8
32
128
4 MHz
1 MHz
250 KHz
62.5 KHz
RESET: 0 0 0 0 1 0 0 0
WRITE:
READ: SPRF 0 OVRF MODF SPTE SPR1 SPR0
SPSCR
0
Serial Peripheral Interface Module MTT48 8-10M
SPI Data Register
SPI Data Register (SPDR)
• Read/Write buffer for SPI data
• Write operation– Writes data to transmit data register
• Read operation– Reads data in receive data register
RESET: UNAFFECTED BY RESET
WRITE:
READ: Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0SPDR
Serial Peripheral Interface Module MTT48 8-11M
SPI Status Flags
SPI Status and Control Register (SPSCR)
• SPI Receiver Receiver Full (SPRF)– Set when a byte is shifted from shift register to the receive data register– Cleared by reading SPSCR then reading SPDR
1 = Receive data register full
0 = Receive data register not full
• SPI Transmitter Empty (SPTE)– Set when a byte is transferred from SPDR to the shift register– Cleared by reading SPDR register
1 = Transmit data register empty
0 = Transmit data register not empty
RESET: 0 0 0 0 1 0 0 0
WRITE:
READ: SPRF 0 OVRF MODF SPTE SPR1 SPR0
SPSCR
0
Serial Peripheral Interface Module MTT48 8-12M
SPI Interrupts
SPI Control Register (SPCR)
• SPI Receiver Interrupt Enable Bit (SPRIE)– Interrupt generated when SPRF flag set
• SPI Transmit Interrupt Enable (SPTIE))– Interrupt generated when SPTE flag set
1 = Interrupt enabled
0 = Interrupt disabled
• Direct Memory Access Select (DMAS)– Selects either DMA or CPU interrupt request– SPRIE/SPTIE bits still enable or disable interrupts
RESET: 0 0 0 0 1 0 0 0
WRITE:
READ: SPRIE DMAS SPMSTR CPOL CPHA SPWOM SPE SPTIESPCR
Serial Peripheral Interface Module MTT48 8-13M
Initialization
SPI Initialization sequence
1) Initialize SPI clock frequency ( SPR1 and SPR0 in SPSCR )
2) Set clock configuration ( CPOL and CPHA bits in SPSCR )
3) Select Master/Slave operation ( SPMSTR in SPCR )
4) Enable interrupts if desired ( SPTIE, SPRIE in SPCR )
5) Enable the SPI system ( SPE in SPCR )
• Should enable Master before Slaves
Serial Peripheral Interface Module MTT48 8-14M
Master to Slave Transfer
Simple Polled operation
1) Initialize the SPI
2) Select SS to Slave device (hardware dependent
3) Write byte to SPDR
4) Wait for SPI Transmitter Empty Flag (SPTE)
5) Read the SPDR
6) Release SS to Slave (hardware dependent)
Serial Peripheral Interface Module MTT48 8-15M
SPI Exercise
Part 1:
Initialize a SPI to the following:
Master mode
1 MHz baud rate ( 8 MHz system clock )
Clock phase = 1 and clock polarity = 0
Polled operation
Part 2:
Write a procedure to transmit the character in the
Accumulator to the Slave device. Then wait for the
received character and place it into the Accumulator.
(The Master SS is tied to VDD and the Slave SS is tied to
ground)
Serial Peripheral Interface Module MTT48 8-16M
SPI C
onfig & T
ransmit E
xercise
Write a routine that configures the S
PI as a m
aster, non-interrupt driven and then transmits the
value $55. The S
PI is connected to a serial-in/parallel out 8-bit shift register. T
he shift register is chip-selected w
ith the PB
3 line at low voltage level. B
etween transfers, the P
B3 line m
ust be high. It requires the clock to idle low
and takes data on rising clock edges. The serial clock
cannot exceed 300 KH
z. Assum
e System
Clock F
requency = 8 M
Hz.
Su
ggested p
rogram step
s: A
ddresses for: Port B
Data register
Port F
Data register
Port B
Data D
irection register P
ort F D
ata Direction register
SP
I Control register
SP
I Status and C
ontrol register S
PI D
ata (Read=
rcv, Write=
xmt)
Write you
r program
here:
PTB EQU $01
PTF EQU $09
DDRB EQU $05
DDRF EQU $0D
SPCR EQU $10
SPSCR EQU $11
SPDR EQU $12
HC
08-SP
IExer
CO
NF
IGU
RA
TIO
N:
Select P
ort F inputs/outputs &
levels :
1. Make P
B3 output value high.
2. Make P
B3 an output.
3. Load accum
ulator with
" MO
SI &
SP
SC
K =
outputs" value. " M
ISO
& S
S* =
inputs" value. 4. S
tore accumulator to D
DR
F register.
Select m
aster mode, clock operation, &
enable SP
I: 5. L
oad AC
C. w
ith value that selects freq Š 300 K
Hz.
6. S
tore accumulator to S
PS
CR
register. 7. L
oad accumulator w
ith value that selects master
mode, clock phase =
rising edge, polarity = idle
low, active pullup outputs, interrupts disabled,
SP
I enabled. 8. S
tore accumulator to S
PC
R register.
Send $55 to shift register:
9. Make P
B3 output low
(chip-select shift register). 10. L
oad accumulator w
ith $55. 11. S
tore accumulator to S
PD
R register.
12. Stay here until transm
ission is complete.
13. Make P
B3 output high (deselect shift register).
14. Done, stay here.
Serial Peripheral Interface Module MTT48 8-17M
Additional InformationWired-Or Mode
SPI Control Register (SPCR)
• SPI Wired OR Mode (SPWOM)– Configures MISO, MOSI, and SPSCK outputs to be open-drain drivers– Allows multiple-master systems– Provides some protection against CMOS latchup
RESET: 0 0 0 0 1 0 0 0
WRITE:
READ: SPRIE DMAS SPMSTR CPOL CPHA SPWOM SPE SPTIESPCR
Serial Peripheral Interface Module MTT48 8-18M
Additional InformationOverflow and Mode Fault Status Flags
SPI Status and Control Register (SPSCR)
• Overflow flag (OVRF)– Failure to read data register before it is over written– Incoming data bytes are lost
• Data register contents unaffected– Cleared by reading the data register
• Mode Fault flag (MODF)– Master mode only– Indicates another master tried to access this device– Set when another device pulls SS pin low– Cleared by a write to the SPSCR
RESET: 0 0 0 0 1 0 0 0
WRITE:
READ: SPRF 0 OVRF MODF SPTE SPR1 SPR0
SPSCR
0
Serial Peripheral Interface Module MTT48 8-19M
Additional InformationLow Power Modes
Low Power Modes
• WAIT– SPI mode remains active– SPI registers are not accessible
• Except by DMA– Enabled SPI interrupts will exit wait mode
• STOP– SPI module becomes inactive– No affect on register conditions– Operation continues after an external interrupt
Serial Peripheral Interface Module MTT48 8-20M
SPSCR
WRITE:
READ: Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0SPDR
SPRIESPCRWRITE:
READ:DMAS SPMSTR CPOL CPHA SPWOM SPE SPTIE
Register Summary
SPR1 SPR0WRITE:
READ: SPRF 0 OVRF MODF SPTE 0
Serial Peripheral Interface Module MTT48 8-21M
SPI C
onfig & T
ransmit Solution
Write a routine that configures the S
PI as a m
aster, non-interrupt driven and then transmits the
value $55. The S
PI is connected to a serial-in/parallel out 8-bit shift register. T
he shift register is chip-selected w
ith the PB
3 line at low voltage level. B
etween transfers, the P
B3 line m
ust be high. It requires the clock to idle low
and takes data on rising clock edges. The serial clock
cannot exceed 300 KH
z. Assum
e System
Clock F
requency = 8 M
Hz.
Su
ggested p
rogram step
s: A
ddresses for: Port B
Data register
Port F
Data register
Port B
Data D
irection register P
ort F D
ata Direction register
SP
I Control register
SP
I Status and C
ontrol register S
PI D
ata (Read=
rcv, Write=
xmt)
Write you
r program
here:
PTB EQU $01
PTF EQU $09
DDRB EQU $05
DDRF EQU $0D
SPCR EQU $10
SPSCR EQU $11
SPDR EQU $12
HC
08-SP
ISol
BSET #3,PTB
BSET #3,DDRB
LDA #$06
STA DDRF
LDA #$02
STA SPSCR
LDA #$22
STA SPCR
BCLR #3,PORTB
LDA #$55
STA SPDR
WAIT BRCLR #7,SPSCR,WAIT
BSET #3,PORTB
DONE BRA DONE
Send $55 to shift register:
9. Make P
B3 output low
(chip-select shift register). 10. L
oad accumulator w
ith $55. 11. S
tore accumulator to S
PD
R register.
12. Stay here until transm
ission is complete.
13. Make P
B3 output high (deselect shift register).
14. Done, stay here.
Select m
aster mode, clock operation, &
enable SP
I: 5. L
oad AC
C. w
ith value that selects freq Š 300 K
Hz.
6. S
tore accumulator to S
PS
CR
register. 7. L
oad accumulator w
ith value that selects master
mode, clock phase =
rising edge, polarity = idle
low, active pullup outputs, interrupts disabled,
SP
I enabled. 8. S
tore accumulator to S
PC
R register.
CO
NF
IGU
RA
TIO
N:
Select P
ort F inputs/outputs &
levels :
1. Make P
B3 output value high.
2. Make P
B3 an output.
3. Load accum
ulator with
" MO
SI &
SP
SC
K =
outputs" value. " M
ISO
& S
S* =
inputs" value. 4. S
tore accumulator to D
DR
F register.