Serial Comm - UTEP · Block Diagram . USCI Programming Model . USACTL0 . USACTL1 . USA0BR0 and...
Transcript of Serial Comm - UTEP · Block Diagram . USCI Programming Model . USACTL0 . USACTL1 . USA0BR0 and...
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Serial Comm
EE3376
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Serial Communication Interface l Referred to as UART in most companies (N16550 compatible) l Serial communication where no clock is shared (thus asynch) l Both receiver / transmitter share only a nominal baud rate l 1 stop bit and start bit per 8 bits of data (20% overhead) l optional parity bit for error checking l Rule of Thumb is that baud error should be less than 1%.
rx
tx tx
rx
system a system b
baud clock = 19.1k baud clock = 18.9k
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USCI Details in Hardware Manual
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Serial Communication Interface l TX signal stays high while idle l When beginning a transaction, start bit always goes low for 1 bit l Next 8 baud periods, data is sampled. l 10th bit should be stop bit and is always high. l Internally, data is sampled at a higher rate (16x) and averaged
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Asynch – How does it work?
TX Data 7 6 5 4 3 2 1 0
TX Clock 9589 Hz
RX Clock 9645 Hz
• Baud rates are both nominally (in name only) 9600. • Actual bauds are not exactly the same but are close enough that the first
10/11 bits are received correctly. • Receiver is aware of incoming frame upon sampling a low (start bit). • Receiver is aware of successful completion if the parity matches
(optional) and the last bit is high (stop bit). • In reality, receiver samples at a higher rate of 9600 x 16 and gets average
of 16 values it reads in each bit. This helps noise and mismatch.
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Asynch – example wrong baud
TX Data 7 6 5 4 3 2 1 0
TX Clock 9589 Hz
RX Clock 13000 Hz
• Case of frequency mismatch too great to receive value correctly. • Bit 1 of transmitted word is received as stop bit – if low, (stop bit always
high) than the receiver will be aware of the corruption. • Otherwise, corruption would go undetected unless parity used. • In this case,
R7=T7, R6=T6, R5=T5, R4=T5, R3=T4, R2=T3, R1=T2, R0=T2.
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USCI Hardware Overview
not drawn to scale
cpu
bus
ram
USCI0 shift register
config / status
shift register
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Block Diagram
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USCI Programming Model
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USACTL0
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USACTL1
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USA0BR0 and USA0BR1
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USACTL0
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USCI - Interrupts
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USCI Data Registers
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USCI for IrDA – remote controls…
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USCI Baud Rate Selection
The USA0BR0 and USA0BR1 represent a value – BR – between 1 and 64K Baud Rate = CLK / (BR) where ACLK = LVO at 1MHz Example: ACLK =1MHz, BR=104 Baud Rate = 1MHz / (104) = 9615 Baud Error = 9615 – 9600 / 9600 = .15% = good enough!
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USCI Initialization
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USCI Functions
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USCI Functions
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USCI Functions
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USCI Functions
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USCI Functions
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USCI Functions
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USCI Functions
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Serial Peripheral Interface l Synchronous Serial Interface – clock sent with data l Duplex with data simultaneously in both directions l No start/stop overhead on bandwidth, but requires 4 signals l Data sampled on edge of clock when frame asserted
– alternatively, clock can be controlled and gated by master l Useful for short, high speed (faster than UART) interface l Commonly used for DAC or RTCs or HCS12 to HCS12 comm.
rx
tx tx
rx
master slave
frame frame
clk clk
clock
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Serial Peripheral Interface
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SPI
Think of an SPI connection as a rolling shift register that resides (is shared) on two chips.
enable
clock
so
si
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IIC – 2 Wire Interface l Very inexpensive Interface
– Only two wires – SCL and SDA – SCL is gated – Synchronous – no baud generation necessary for slaves – Multiple slaves allowed – up to 32 – Wired OR configuration – pull up resistor on both lines – slow speed – 100KHz original, 400KHz fast, new 1MHz high speed – commonly used for EEPROMs
master slave0 slave1 slave31
IIC_CLK
IIC_SDA