Sequential logic - University of Washington · 2006-10-24 · Sequential logic Sequential circuits...

28
Autumn 2006 CSE370 - IV - Sequential Logic 1 Sequential logic Sequential circuits simple circuits with feedback latches edge-triggered flip-flops Timing methodologies cascading flip-flops for proper operation clock skew Basic registers shift registers simple counters Hardware description languages and sequential logic Autumn 2006 CSE370 - IV - Sequential Logic 2 X1 X2 Xn switching network Z1 Z2 Zn Circuits with feedback How to control feedback? what stops values from cycling around endlessly

Transcript of Sequential logic - University of Washington · 2006-10-24 · Sequential logic Sequential circuits...

Page 1: Sequential logic - University of Washington · 2006-10-24 · Sequential logic Sequential circuits simple circuits with feedback latches edge-triggered flip-flops Timing methodologies

Autumn 2006 CSE370 - IV - Sequential Logic 1

Sequential logic

Sequential circuitssimple circuits with feedbacklatchesedge-triggered flip-flops

Timing methodologiescascading flip-flops for proper operationclock skew

Basic registersshift registerssimple counters

Hardware description languages and sequential logic

Autumn 2006 CSE370 - IV - Sequential Logic 2

X1X2•••

Xn

switchingnetwork

Z1Z2•••

Zn

Circuits with feedback

How to control feedback?what stops values from cycling around endlessly

Page 2: Sequential logic - University of Washington · 2006-10-24 · Sequential logic Sequential circuits simple circuits with feedback latches edge-triggered flip-flops Timing methodologies

Autumn 2006 CSE370 - IV - Sequential Logic 3

"remember"

"load""data" "stored value"

"0"

"1"

"stored value"

Simplest circuits with feedback

Two inverters form a static memory cellwill hold value as long as it has power applied

How to get a new value into the memory cell?selectively break feedback pathload new value into cell

Autumn 2006 CSE370 - IV - Sequential Logic 4

R

S

Q

Q'

RS

Q

R'S'

QQ

Q'

S'

R'

Memory with cross-coupled gates

Cross-coupled NOR gatessimilar to inverter pair, with capability to force output to 0 (reset=1) or 1 (set=1)

Cross-coupled NAND gatessimilar to inverter pair, with capability to force output to 0 (reset=0) or 1 (set=0)

Page 3: Sequential logic - University of Washington · 2006-10-24 · Sequential logic Sequential circuits simple circuits with feedback latches edge-triggered flip-flops Timing methodologies

Autumn 2006 CSE370 - IV - Sequential Logic 5

Reset Hold Set SetReset Race

R

S

Q

\Q

100

Timing behavior

R

S

Q

Q'

Autumn 2006 CSE370 - IV - Sequential Logic 6

S R Q0 0 hold0 1 01 0 11 1 unstable

State behavior or R-S latch

Truth table of R-S latch behavior

Q Q'0 1

Q Q'1 0

Q Q'0 0

Q Q'1 1

R

S

Q

Q'

Page 4: Sequential logic - University of Washington · 2006-10-24 · Sequential logic Sequential circuits simple circuits with feedback latches edge-triggered flip-flops Timing methodologies

Autumn 2006 CSE370 - IV - Sequential Logic 7

Theoretical R-S latch behavior

State diagramstates: possible valuestransitions: changesbased on inputs

Q Q'0 1

Q Q'1 0

Q Q'0 0

Q Q'1 1

SR=10SR=00SR=01

SR=11

R

S

Q

Q'

Autumn 2006 CSE370 - IV - Sequential Logic 8

Theoretical R-S latch behavior

State diagramstates: possible valuestransitions: changesbased on inputs

Q Q'0 1

Q Q'1 0

Q Q'0 0

Q Q'1 1

SR=10

SR=01SR=00SR=10

SR=00SR=01

SR=11 SR=11

R

S

Q

Q'

Page 5: Sequential logic - University of Washington · 2006-10-24 · Sequential logic Sequential circuits simple circuits with feedback latches edge-triggered flip-flops Timing methodologies

Autumn 2006 CSE370 - IV - Sequential Logic 9

Theoretical R-S latch behavior

State diagramstates: possible valuestransitions: changesbased on inputs

Q Q'0 1

Q Q'1 0

Q Q'0 0

Q Q'1 1

SR=00

SR=10

SR=01SR=00SR=10

SR=00SR=01

SR=11 SR=11

SR=01 SR=10

SR=11

R

S

Q

Q'

Autumn 2006 CSE370 - IV - Sequential Logic 10

Theoretical R-S latch behavior

State diagramstates: possible valuestransitions: changesbased on inputs

Q Q'0 1

Q Q'1 0

Q Q'0 0

Q Q'1 1

SR=00SR=11SR=00

SR=10

SR=01SR=00SR=10

SR=00SR=01

SR=11 SR=11

SR=10SR=01

SR=01 SR=10

SR=11

possible oscillationbetween states 00 and 11

R

S

Q

Q'

Page 6: Sequential logic - University of Washington · 2006-10-24 · Sequential logic Sequential circuits simple circuits with feedback latches edge-triggered flip-flops Timing methodologies

Autumn 2006 CSE370 - IV - Sequential Logic 11

Observed R-S latch behavior

Very difficult to observe R-S latch in the 1-1 stateone of R or S usually changes first

Ambiguously returns to state 0-1 or 1-0a so-called "race condition"or non-deterministic transition

SR=00SR=00

Q Q'0 1

Q Q'1 0

Q Q'0 0

SR=10

SR=01SR=00SR=10

SR=00SR=01

SR=11 SR=11

SR=01 SR=10

SR=11

R

S

Q

Q'

Autumn 2006 CSE370 - IV - Sequential Logic 12

Q(t+∆)

RS

Q(t)

S R Q(t) Q(t+∆)0 0 0 00 0 1 10 1 0 00 1 1 01 0 0 11 0 1 11 1 0 X1 1 1 X

hold

reset

set

not allowed characteristic equationQ(t+∆) = S + R’ Q(t)

R-S latch analysis

Break feedback path

R

S

Q

Q'

0 0

1 0

X 1

X 1Q(t)

R

S

Page 7: Sequential logic - University of Washington · 2006-10-24 · Sequential logic Sequential circuits simple circuits with feedback latches edge-triggered flip-flops Timing methodologies

Autumn 2006 CSE370 - IV - Sequential Logic 13

R’

S’ Q

Q'

Activity: R-S latch using NAND gates

characteristic equationQ(t+∆) =

Q(t)

R

S

S R S’ R’ Q(t) Q(t+∆)0 0 1 1 00 0 1 1 10 1 1 0 00 1 1 0 11 0 0 1 01 0 0 1 11 1 0 0 01 1 0 0 1

Autumn 2006 CSE370 - IV - Sequential Logic 14

R’

S’ Q

Q'

Activity: R-S latch using NAND gates

characteristic equationQ(t+∆) = S + R’ Q(t)

R’S’

Q(t)

0 0

1 0

X 1

X 1Q(t)

R

S

S R S’ R’ Q(t) Q(t+∆)0 0 1 1 0 00 0 1 1 1 10 1 1 0 0 00 1 1 0 1 01 0 0 1 0 11 0 0 1 1 11 1 0 0 0 X1 1 0 0 1 X

hold

reset

set

not allowed

Page 8: Sequential logic - University of Washington · 2006-10-24 · Sequential logic Sequential circuits simple circuits with feedback latches edge-triggered flip-flops Timing methodologies

Autumn 2006 CSE370 - IV - Sequential Logic 15

enable'

S'Q'

QR' R

S

Gated R-S latch

Control when R and S inputs matter

otherwise, the slightest glitch on R or S while enable is low could cause change in value stored

Set Reset

S'

R'

enable'

Q

Q'

100

Autumn 2006 CSE370 - IV - Sequential Logic 16

period

duty cycle (in this case, 50%)

Clocks

Used to keep timewait long enough for inputs (R' and S') to settlethen allow to have effect on value stored

Clocks are regular periodic signalsperiod (time between ticks)duty-cycle (time clock is high between ticks - expressed as % of period)

Page 9: Sequential logic - University of Washington · 2006-10-24 · Sequential logic Sequential circuits simple circuits with feedback latches edge-triggered flip-flops Timing methodologies

Autumn 2006 CSE370 - IV - Sequential Logic 17

clock’

R’ and S’

changing stable changing stablestable

Clocks (cont’d)

Controlling an R-S latch with a clockcan't let R and S change while clock is active (allowing R and S to pass)only have half of clock period for signal changes to propagatesignals must be stable for the other half of clock period

clock’

S’Q’

QR’ R

S

Autumn 2006 CSE370 - IV - Sequential Logic 18

clock

R

S Q

Q’ R

S Q

Q’R

S

Cascading latches

Connect output of one latch to input of anotherHow to stop changes from racing through chain?

need to be able to control flow of data from one latch to the nextmove one latch per clock periodhave to worry about logic between latches (arrows) that is too fast

Page 10: Sequential logic - University of Washington · 2006-10-24 · Sequential logic Sequential circuits simple circuits with feedback latches edge-triggered flip-flops Timing methodologies

Autumn 2006 CSE370 - IV - Sequential Logic 19

Master-slave structure

Break flow by alternating clocks (like an air-lock)use positive clock to latch inputs into one R-S latchuse negative clock to change outputs with another R-S latch

View pair as one basic unitmaster-slave flip-floptwice as much logicoutput changes a few gate delays after the falling edge of clockbut does not affect any cascaded flip-flops

master stage slave stage

P

P’

CLK

R

S Q

Q’ R

S Q

Q’R

S

Autumn 2006 CSE370 - IV - Sequential Logic 20

10 gates

D flip-flop

Make S and R complements of each othereliminates 1s catching problemcan't just hold previous value(must have new value ready every clock period)value of D just before clock goes low is what is stored in flip-flopcan make R-S flip-flop by adding logic to make D = S + R’ Q

D Q

Q’

master stage slave stage

P

P’

CLK

R

S Q

Q’ R

S Q

Q’

Page 11: Sequential logic - University of Washington · 2006-10-24 · Sequential logic Sequential circuits simple circuits with feedback latches edge-triggered flip-flops Timing methodologies

Autumn 2006 CSE370 - IV - Sequential Logic 21

Q

D

Clk=1

R

S

0

D’

0

D’ D

Q’

negative edge-triggered D flip-flop (D-FF)

4-5 gate delays

must respect setup and hold time constraints to successfully

capture input

characteristic equationQ(t+1) = D

holds D’ whenclock goes low

holds D whenclock goes low

Edge-triggered flip-flops using gates

Only 6 gatessensitive to inputs only near edge of clock signal (not while high)

D Q

Autumn 2006 CSE370 - IV - Sequential Logic 22

Edge-triggered flip-flops using transistors

Only 8 transistors

D Q

D Q

D

clk

Q

clk’

clk’ clk

D

clk’

Q

clk

clk clk’

Page 12: Sequential logic - University of Washington · 2006-10-24 · Sequential logic Sequential circuits simple circuits with feedback latches edge-triggered flip-flops Timing methodologies

Autumn 2006 CSE370 - IV - Sequential Logic 23

positive edge-triggered FF

negative edge-triggered FF

DCLK

QposQpos’QnegQneg’

100

Edge-triggered flip-flops (cont’d)

Positive edge-triggeredinputs sampled on rising edge; outputs change after rising edge

Negative edge-triggered flip-flopsinputs sampled on falling edge; outputs change after falling edge

Autumn 2006 CSE370 - IV - Sequential Logic 24

Timing methodologies

Rules for interconnecting components and clocksguarantee proper operation of system when strictly followed

Approach depends on building blocks used for memory elements

we'll focus on systems with edge-triggered flip-flopsfound in programmable logic devices

many custom integrated circuits focus on level-sensitive latchesBasic rules for correct timing:

(1) correct inputs, with respect to time, are provided to the flip-flops(2) no flip-flop changes state more than once per clocking event

Page 13: Sequential logic - University of Washington · 2006-10-24 · Sequential logic Sequential circuits simple circuits with feedback latches edge-triggered flip-flops Timing methodologies

Autumn 2006 CSE370 - IV - Sequential Logic 25

there is a timing "window" around the clocking event during which the input must remain stable and unchanged in order to be recognized

clock

datachangingstable

input

clock

Tsu Th

clock

dataD Q D Q

Timing methodologies (cont’d)

Definition of termsclock: periodic event, causes state of memory element to change

can be rising edge or falling edge or high level or low levelsetup time: minimum time before the clocking event by which the

input must be stable (Tsu)hold time: minimum time after the clocking event until which the

input must remain stable (Th)

Autumn 2006 CSE370 - IV - Sequential Logic 26

behavior is the same unless input changeswhile the clock is high

D Q

CLK

positiveedge-triggered

flip-flop

D QG

CLK

transparent(level-sensitive)

latch

D

CLK

Qedge

Qlatch

Comparison of latches and flip-flops

Page 14: Sequential logic - University of Washington · 2006-10-24 · Sequential logic Sequential circuits simple circuits with feedback latches edge-triggered flip-flops Timing methodologies

Autumn 2006 CSE370 - IV - Sequential Logic 27

Type When inputs are sampled When output is valid

unclocked always propagation delay from input changelatch

level-sensitive clock high propagation delay from input changelatch (Tsu/Th around falling or clock edge (whichever is later)

edge of clock)

master-slave clock hi-to-lo transition propagation delay from falling edgeflip-flop (Tsu/Th around falling of clock

edge of clock)

negative clock hi-to-lo transition propagation delay from falling edgeedge-triggered (Tsu/Th around falling of clockflip-flop edge of clock)

Comparison of latches and flip-flops (cont’d)

Autumn 2006 CSE370 - IV - Sequential Logic 28all measurements are made from the clocking event (the rising edge of the clock)

Typical timing specifications

Positive edge-triggered D flip-flopsetup and hold timesminimum clock widthpropagation delays (low to high, high to low, max and typical)

D

Clk

Q

T su1.8ns

T h 0.5ns

T w 3.3 ns

T pd3.6 ns 1.1 ns

T su1.8ns

T h 0.5 ns

T pd3.6 ns 1.1 ns

T w 3.3 ns

Page 15: Sequential logic - University of Washington · 2006-10-24 · Sequential logic Sequential circuits simple circuits with feedback latches edge-triggered flip-flops Timing methodologies

Autumn 2006 CSE370 - IV - Sequential Logic 29

IN

Q0

Q1

CLK

100

Cascading edge-triggered flip-flops

Shift registernew value goes into first stagewhile previous value of first stage goes into second stageconsider setup/hold/propagation delays (prop must be > hold)

CLK

INQ0 Q1

D Q D Q OUT

Autumn 2006 CSE370 - IV - Sequential Logic 30

timing constraintsguarantee proper

operation ofcascaded components

assumes infinitely fast distribution of the clock

Cascading edge-triggered flip-flops (cont’d)

Why this workspropagation delays exceed hold timesclock width constraint exceeds setup timethis guarantees following stage will latch current value before it changes to new value

Tsu1.8ns

Tp1.1-3.6ns

Th0.5ns

In

Q0

Q1

CLK

Tsu1.8ns

Tp1.1-3.6ns

Th0.5ns

Page 16: Sequential logic - University of Washington · 2006-10-24 · Sequential logic Sequential circuits simple circuits with feedback latches edge-triggered flip-flops Timing methodologies

Autumn 2006 CSE370 - IV - Sequential Logic 31

original state: IN = 0, Q0 = 1, Q1 = 1due to skew, next state becomes: Q0 = 0, Q1 = 0, and not Q0 = 0, Q1 = 1

CLK1 is a delayedversion of CLK0

InQ0Q1

CLK0CLK1

100

Clock skew

The problemcorrect behavior assumes next state of all storage elementsdetermined by all storage elements at the same timethis is difficult in high-performance systems because time for clockto arrive at flip-flop is comparable to delays through logiceffect of skew on cascaded flip-flops:

Autumn 2006 CSE370 - IV - Sequential Logic 32

Summary of latches and flip-flops

Development of D-FFlevel-sensitive used in custom integrated circuits

can be made with 8 switchesedge-triggered used in modern programmable logic devicesgood choice for data storage register

Historically J-K FF was popular but now never usedsimilar to R-S but with 1-1 being used to toggle output (complement state)good in days of TTL/SSI (more complex input function: D = J Q’ + K’ Qcan always be implemented using D-FF

Preset and clear inputs are highly desirable on flip-flopsused at start-up or to reset system to a known state

Page 17: Sequential logic - University of Washington · 2006-10-24 · Sequential logic Sequential circuits simple circuits with feedback latches edge-triggered flip-flops Timing methodologies

Autumn 2006 CSE370 - IV - Sequential Logic 33

Flip-flop features

Reset (set state to 0) – Rsynchronous: Dnew = R' • Dold (when next clock edge arrives)asynchronous: doesn't wait for clock, quick but dangerous

Preset or set (set state to 1) – S (or sometimes P)synchronous: Dnew = Dold + S (when next clock edge arrives)asynchronous: doesn't wait for clock, quick but dangerous

Both reset and presetDnew = R' • Dold + S (set-dominant)Dnew = R' • Dold + R'S (reset-dominant)

Selective input capability (input enable or load) – LD or ENmultiplexor at input: Dnew = LD' • Q + LD • Doldload may or may not override reset/set (usually R/S have priority)

Complementary outputs – Q and Q'

Autumn 2006 CSE370 - IV - Sequential Logic 34

R S R S R SD Q D Q D Q D Q

OUT1 OUT2 OUT3 OUT4

CLK

IN1 IN2 IN3 IN4

R S

"0"

Registers

Collections of flip-flops with similar controls and logicstored values somehow related (for example, form binary value)share clock, reset, and set linessimilar logic at each stage

Examplesshift registerscounters

Page 18: Sequential logic - University of Washington · 2006-10-24 · Sequential logic Sequential circuits simple circuits with feedback latches edge-triggered flip-flops Timing methodologies

Autumn 2006 CSE370 - IV - Sequential Logic 35

D Q D Q D Q D QIN

OUT1 OUT2 OUT3 OUT4

CLK

Shift register

Holds samples of inputstore last 4 input values in sequence4-bit shift register:

Autumn 2006 CSE370 - IV - Sequential Logic 36

clear sets the register contentsand output to 0

s1 and s0 determine the shift function

s0 s1 function0 0 hold state0 1 shift right1 0 shift left1 1 load new input

left_inleft_out

right_out

clearright_in

output

input

s0s1

clock

Universal shift register

Holds 4 valuesserial or parallel inputsserial or parallel outputspermits shift left or rightshift in new values from left or right

Page 19: Sequential logic - University of Washington · 2006-10-24 · Sequential logic Sequential circuits simple circuits with feedback latches edge-triggered flip-flops Timing methodologies

Autumn 2006 CSE370 - IV - Sequential Logic 37

Nth cell

DQ

CLK

Q[N-1](left)

Q[N+1](right)

Input[N]

to N-1th cell

to N+1th cell

clear s0 s1 new value1 – – 00 0 0 output0 0 1 output value of FF to left (shift right)0 1 0 output value of FF to right (shift left)0 1 1 input

Design of universal shift register

Consider one of the four flip-flopsnew value at next clock cycle:

s0 and s1control mux0 1 2 3

CLEAR

Autumn 2006 CSE370 - IV - Sequential Logic 38

parallel inputs

parallel outputs

serial transmission

Shift register application

Parallel-to-serial conversion for serial transmission

Page 20: Sequential logic - University of Washington · 2006-10-24 · Sequential logic Sequential circuits simple circuits with feedback latches edge-triggered flip-flops Timing methodologies

Autumn 2006 CSE370 - IV - Sequential Logic 39

D Q D Q D Q D QIN

OUT1 OUT2 OUT3 OUT4

CLK

OUT

Pattern recognizer

Combinational function of input samplesin this case, recognizing the pattern 1001 on the single input signal

Autumn 2006 CSE370 - IV - Sequential Logic 40

D Q D Q D Q D QIN

OUT1 OUT2 OUT3 OUT4

CLK

Counters

Sequences through a fixed set of patternsin this case, 1000, 0100, 0010, 0001if one of the patterns is its initial state (by loading or set/reset)

Page 21: Sequential logic - University of Washington · 2006-10-24 · Sequential logic Sequential circuits simple circuits with feedback latches edge-triggered flip-flops Timing methodologies

Autumn 2006 CSE370 - IV - Sequential Logic 41

Activity

How does this counter work?

D Q D Q D Q D QIN

OUT1 OUT2 OUT3 OUT4

CLK

Autumn 2006 CSE370 - IV - Sequential Logic 42

Activity

How does this counter work?

D Q D Q D Q D QIN

OUT1 OUT2 OUT3 OUT4

CLK

Counts through the sequence: 1000, 1100, 1110, 1111, 0111, 0011, 0001, 0000

Known as Mobius (or Johnson) counter

Page 22: Sequential logic - University of Washington · 2006-10-24 · Sequential logic Sequential circuits simple circuits with feedback latches edge-triggered flip-flops Timing methodologies

Autumn 2006 CSE370 - IV - Sequential Logic 43

D Q D Q D Q D Q

OUT1 OUT2 OUT3 OUT4

CLK

"1"

Binary counter

Logic between registers (not just multiplexer)XOR decides when bit should be toggledalways for low-order bit,only when first bit is true for second bit,and so on

Autumn 2006 CSE370 - IV - Sequential Logic 44

EN

DCBALOADCLKCLR

RCOQDQCQBQA

(1) Low order 4-bits = 1111

(2) RCO goes high

(3) High order 4-bits are incremented

Four-bit binary synchronous up-counter

Standard component with many applicationspositive edge-triggered FFs w/ synchronous load and clear inputsparallel load data from D, C, B, Aenable inputs: must be asserted to enable countingRCO: ripple-carry out used for cascading counters

high when counter is in its highest state 1111implemented using an AND gate

Page 23: Sequential logic - University of Washington · 2006-10-24 · Sequential logic Sequential circuits simple circuits with feedback latches edge-triggered flip-flops Timing methodologies

Autumn 2006 CSE370 - IV - Sequential Logic 45

EN

DCBALOADCLKCLR

RCOQDQCQBQA

"1"

"0""0""0""0"

"0"

EN

DCBALOADCLKCLR

RCOQDQCQBQA

"1"

"0""1""1""0"

Offset counters

Starting offset counters – use of synchronous loade.g., 0110, 0111, 1000, 1001,1010, 1011, 1100, 1101, 1111, 0110, . . .

Ending offset counter – comparator for ending valuee.g., 0000, 0001, 0010, ..., 1100, 1101, 0000

Combinations of the above (start and stop value)

Autumn 2006 CSE370 - IV - Sequential Logic 46

Hardware Description Languages and Sequential Logic

Flip-flopsrepresentation of clocks - timing of state changesasynchronous vs. synchronous

Shift registersSimple counters

Page 24: Sequential logic - University of Washington · 2006-10-24 · Sequential logic Sequential circuits simple circuits with feedback latches edge-triggered flip-flops Timing methodologies

Autumn 2006 CSE370 - IV - Sequential Logic 47

module dff (clk, d, q);

input clk, d;output q;reg q;

always @(posedge clk)q = d;

endmodule

Flip-flop in Verilog

Use always block's sensitivity list to wait for clock edge

Autumn 2006 CSE370 - IV - Sequential Logic 48

module dff (clk, s, r, d, q);input clk, s, r, d;output q;reg q;

always @(posedge clk)if (r) q = 1'b0;else if (s) q = 1'b1;else q = d;

endmodule

module dff (clk, s, r, d, q);input clk, s, r, d;output q;reg q;

always @(posedge r)q = 1'b0;

always @(posedge s)q = 1'b1;

always @(posedge clk)q = d;

endmodule

More Flip-flops

Synchronous/asynchronous reset/setsingle thread that waits for the clockthree parallel threads – only one of which waits for the clock

Synchronous Asynchronous

Page 25: Sequential logic - University of Washington · 2006-10-24 · Sequential logic Sequential circuits simple circuits with feedback latches edge-triggered flip-flops Timing methodologies

Autumn 2006 CSE370 - IV - Sequential Logic 49

module dff (clk, d, q);

input clk, d;output q;reg q;

always @(clk)q = d;

endmodule

Incorrect Flip-flop in Verilog

Use always block's sensitivity list to wait for clock to change

Not correct! Q willchange whenever theclock changes, notjust on an edge.

Autumn 2006 CSE370 - IV - Sequential Logic 50

always @(posedge CLK)begin

temp = B;B = A;A = temp;

end

always @(posedge CLK)begin

A <= B;B <= A;

end

Blocking and Non-Blocking Assignments

Blocking assignments (X=A)completes the assignment before continuing on to next statement

Non-blocking assignments (X<=A)completes in zero time and doesn’t change the value of the target until a blocking point (delay/wait) is encountered

Example: swap

Page 26: Sequential logic - University of Washington · 2006-10-24 · Sequential logic Sequential circuits simple circuits with feedback latches edge-triggered flip-flops Timing methodologies

Autumn 2006 CSE370 - IV - Sequential Logic 51

Register-transfer-level (RTL) Assignment

Non-blocking assignment is also known as an RTL assignmentif used in an always block triggered by a clock edgeall flip-flops change together

// B,C,D all get the value of Aalways @(posedge clk)

beginB = A;C = B;D = C;

end// implements a shift register always @(posedge clk)

beginB <= A;C <= B;D <= C;

end

Autumn 2006 CSE370 - IV - Sequential Logic 52

Shift register in Verilog

module shift_register (clk, in, out);

input clk;input in;output [0:3] out;

reg [0:3] out;

initial beginout = 0; // out[0:3] = {0, 0, 0, 0};

end

always @(posedge clk) beginout = {in, out [0:2]};

end

endmodule

Page 27: Sequential logic - University of Washington · 2006-10-24 · Sequential logic Sequential circuits simple circuits with feedback latches edge-triggered flip-flops Timing methodologies

Autumn 2006 CSE370 - IV - Sequential Logic 53

Activity: express in Verilog

always @(posedge clk)begin

end

D Q D Q D Q D QIN

OUT1 OUT2 OUT3 OUT4

CLK

Autumn 2006 CSE370 - IV - Sequential Logic 54

Mobius Counter in Verilog

initialbegin

A = 1’b0;B = 1’b0;C = 1’b0;D = 1’b0;

end

always @(posedge clk)begin

A <= ~D;B <= A;C <= B;D <= C;

end

{A, B, C, D} <= {~D, A, B, C};

D Q D Q D Q D QIN

OUT1 OUT2 OUT3 OUT4

CLK

Page 28: Sequential logic - University of Washington · 2006-10-24 · Sequential logic Sequential circuits simple circuits with feedback latches edge-triggered flip-flops Timing methodologies

Autumn 2006 CSE370 - IV - Sequential Logic 55

Binary Counter in Verilog

module binary_counter (clk, c8, c4, c2, c1);

input clk;output c8, c4, c2, c1;

reg [3:0] count;

initial begincount = 0;

end

always @(posedge clk) begincount = count + 4’b0001;

end

assign c8 = count[3];assign c4 = count[2];assign c2 = count[1];assign c1 = count[0];

endmodule

module binary_counter (clk, c8, c4, c2, c1, rco);

input clk;output c8, c4, c2, c1, rco;

reg [3:0] count;reg rco;

initial begin . . . end

always @(posedge clk) begin . . . end

assign c8 = count[3];assign c4 = count[2];assign c2 = count[1];assign c1 = count[0];assign rco = (count == 4b’1111);

endmodule

Autumn 2006 CSE370 - IV - Sequential Logic 56

Sequential logic summary

Fundamental building block of circuits with statelatch and flip-flopR-S latch, R-S master/slave, D master/slave, edge-triggered D flip-flop

Timing methodologiesuse of clockscascaded FFs work because propagation delays exceed hold timesbeware of clock skew

Basic registersshift registerscounters

Hardware description languages and sequential logic