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EET 3350 Digital Systems Design

John Wakerly Chapter 7: 7.1 – 7.2

Sequential Circuits

Flip-Flops

Types of Sequential Circuits

• Two major types:– Synchronous – changes in the output are only

allowed to occur in synchronization with an external clock signal

– Asynchronous – changes in the output are allowed to occur whenever there is a change in the input signals

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Types of Sequential Circuits

• Synchronous Sequential Circuits (also called Clocked Sequential Circuits) – All signals are synchronized to some “master clock”– The memory devices respond only when activated

by the master clock– The most common memory device is a flip-flop– Circuits can be designed using systematic methods

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Types of Sequential Circuits

• Asynchronous Sequential Circuits – Outputs depend solely on the order in which the

inputs change, so timing is critical– Based on time-delay devices

• The design methods used for synchronous sequential circuits do not apply to asynchronous circuits

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Synchronous vs. Asynchronous

• Synchronous circuits have sequential elements whose outputs change at the same time.

• Asynchronous circuits have sequential elements whose outputs change at different times.

• Disadvantages of Asynchronous Circuits– Difficult to analyze operations– Intermediate states that are not part of the desired

design may be generated

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Memory Elements

• Memory elements can be anything that will make a past value available at some future time– A device that can hold a binary value

• Memory elements are typically flip-flops– flip-flops and latches– Available in several varieties– Designer chooses based on application

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Flip-Flops and Latches

• All digital designers use the name flip-flop for a sequential device that normally samples its inputs and changes its output only when a clocking signal is changing.

• On the other hand, most digital designers use the name latch for a sequential device that watches its inputs continuously and can change its outputs at any time (although in some cases requiring an enable signal to be asserted)

Flip-Flops and Latches

• Flip-flops have a clock input and synchronous outputs

• Latches are asynchronous and their outputs can change at anytime– May have an enable input

• Flip-flops and Latches are both a type of multivibrator circuit

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Multivibrator

• Multivibrators are a group of regenerative circuits that are used extensively in timing applications

• It is a wave shaping circuit which gives symmetric or asymmetric square wave outputs

• It has two states either stable or quasi-stable depending on the type of multivibrator– Astable: not stable, no stable states– Monostable: one stable state– Bistable: two stable states

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Astable Multivibrator

• An astable multivibrator is a free running oscillator having two quasi-stable states.

• Thus, there is oscillation between these two states and no external signal is required to produce the change in state

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Monostable Multivibrator

• A monostable multivibrator is one which generates a single pulse of specified duration in response to each external trigger signal.

• It has only one stable state. • Application of a trigger causes a change to the

quasi-stable state.

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0

1

0

1

Bistable Multivibrator

• A bistable multivibrator is one that maintains a given output voltage level unless an external trigger is applied.

• Application of an external trigger signal causes a change of state, and this output level is maintained indefinitely until an second trigger is applied .

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0

1

0

1

Multivibrator Types

• Mechanical analogy:

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Bistable Multivibrator

Monostable Multivibrator

Astable Multivibrator

flip-flop, Schmitt Trigger

one-shot

oscillator

S

R

T

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Clock Signal Parameters

• Very important with most sequential circuits– State variables change state at clock edge.

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Bistable Elements

• The simplest sequential circuit (note feedback)• Two states

– One state variable, say, Q

HIGH LOW

LOW HIGH

Q Stable at 0

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Bistable Elements

• The simplest sequential circuit (note feedback)• Two states

– One state variable, say, Q

LOW HIGH

HIGH LOW

Q Stable at 1

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Analog Analysis

• Assume pure CMOS thresholds, 5.0 V rail• Theoretical threshold center is 2.5 V

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Metastability

• Metastability is inherent in any bistable circuit

• Two stable points, one metastable point

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Analog Analysis

• Assume pure CMOS thresholds, 5.0 V rail• Theoretical threshold center is 2.5 V

2.5 V 2.5 V

2.5 V 2.5 V

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Analog Analysis

• Assume pure CMOS thresholds, 5.0 V rail• Theoretical threshold center is 2.5 V

2.5 V

2.5 V 2.5 V

2.0 V

2.0 V 4.8 V

2.5 V2.51 V4.8 V 0.0 V

0.0 V 5.0 V

Q Stable at 0

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Another Look at Metastability

• Another mechanical analogy for metastability

A small movement from metastability leads to stability.

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Why Worry About Metastability?

• All real systems are subject to it– Problems are caused by “asynchronous inputs”

that do not meet flip-flop setup and hold times

• Especially severe in high-speed systems– since clock periods are so short, “metastability

resolution time” can be longer than one clock period

• Many digital designers, products, and companies have been burned by this phenomenom

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Back to the Bistable Circuit• How to control it?

– add control inputs

• S-R latch

Function Table

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S-R Latch OperationNormal Inputs

Metastability is possibleif S and R are negatedsimultaneously.

S & R asserted simultaneously

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S-R Latch Timing Parameters

• Propagation delay• Minimum pulse width Metastability may also

occur if a pulse that is too short is applied to S or R.

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S-R Latch Symbols

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S_L-R_L Latch Using NAND Gates

• Active low inputs S_L & R_L

• When S_L = R_L = 1 latch remembers previous state

• When both are asserted outputs go to 1, not 0

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S-R Latch With Enable

• When C = 1, behaves as an S-R latch

• When C = 0, retains its previous state

• If both S & R = 1 when C changes from 1 to 0 it behaves as an S-R latch in which S & R are negated simultaneously- next state is unpredictable

EN

EN

• S-R latches are useful in control applications, where we think in terms of setting a flag in response to some condition and resetting it when conditions change. So, we control the set and reset inputs somewhat independently.

• However, we often need latches simply to store bits of information- each bit is presented on a signal line, and we would like to store it somewhere. A D-latch may be used in such an application.

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D Latch or Data Flip-Flop• Inverter added to

generate S & R inputs from the D input

• Eliminates the situation where S & R may be asserted simultaneously

• The control input is sometimes named ENABLE, CLK or G.

• It may be active low in some designs

• Always has minimum pulse width requirement

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D Latch Operation

• Functional Behaviour

• When C is asserted Q follows D• Latch is open• The path between D & Q is transparent• Transparent latch• When C is negated latch closes, Q retains its last

value and does not change in response to D

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D Latch Timing Parameters

• Propagation delay (from C or D)• Setup time (D before C edge)• Hold time (D after C edge)

Edge-Triggered D Flip-Flop

• Samples D input and changes its Q & QN output only on the rising edge of a controlling clock signal.

• Master is open and follows the input when CLK is 0• When CLK goes to 1 the Master is closed and its

output is transferred to the Slave which is open• The slave is open when CLK is 1, but changes only

at the beginning of the interval, as Master is closed

Functional Behavior of PET D flip flop

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D Flip-Flop Timing Parameters

• Propagation delay (from CLK)• Setup time (D before CLK)• Hold time (D after CLK)

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J-K Flip-FlopsFunctional Equivalent

JK Characteristic Table JK Excitation Table

J

00001111

K

00110011

Q

01010101

Q+

01001110

Q+

0101

Q

0011

J

01XX

K

XX10

JK / Q 0 1

00 0 1

01 0 0

11 1 0

10 1 1

K-Map for Q+

Q+ = J·Q' + K'·Q

JK Characteristic Eqn

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T or Toggle Flip-Flops

• Important for counters

Summary of Flip-Flop Behavior

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Additional Definitions

• Clocked Synchronous Sequential Circuits– A.K.A. “finite state machines” or simply “state

machines” … or even “FSM”– Use edge-triggered flip-flops– All flip-flops are triggered from the same master

clock signal, and therefore all change state together

• Two types of finite state machines– Mealy Machines: output depends on state and

inputs– Moore Machines: output only depends on state

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State-Machine Structure: Mealy

typically edge-triggered D flip-flops

output depends onstate and input

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State-Machine Structure: Moore

output dependson state only

typically edge-triggered D flip-flops

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State-Machine Structure: Pipelined

• Often used in PLD-based state machines– Outputs taken directly from flip-flops, valid sooner

after clock edge– But the “output logic” must determine output value

one clock tick sooner (“pipelined”)

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Notation and Characteristic Equations

• Q+, Q*, Q(t+1) mean “the next value of Q”• “Excitation” is the input applied to a device

that determines the next state.• “Characteristic equation” specifies the next

state of a device as a function of its excitation.• S-R flip-flop : Q(t+1) = S + R · Q(t) • Edge-triggered D flip-flop: Q(t+1) = D • J-K flip-flop: Q(t+1) = J · Q(t) + K · Q(t)• T flip-flip: Q(t+1) = T + Q(t) = T · Q(t) + T · Q(t)

Synchronous Analysis Process

1. Determine next-state function F and output function G

2. Use F and G to construct a state/output table that completely specifies the next state and output for every possible combination of current state and input.

3. (Optional) Draw state diagram that presents the information in graphical form.

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Detailed steps in the Analysis Process1. Determine the excitation equations for the flip flop

inputs

2. Substitute the excitation equations into the flip flop characteristic equations to obtain transition equations.

3. Use transition equations to construct transition table.

4. Determine the output equations.

5. Add output values to the transition table for each state (Moore) or state /input combination (Mealy) to create a transition/output table.

6. Name the states and substitute state names for state – variable combinations in the transition/output table to obtain the state/output table.

7. Draw a state diagram corresponding to the state/output table.