Sept. 7, 2004Silicon VTX Workshop - Brookhaven National Laboratory, Long Island, New York Prototype...

Sept. 7, 2004 Silicon VTX Workshop - Brookhaven National Laboratory, Long Island, New York

Prototype Design of the Front End Module (FEM) for the

Silicon Pixel Vertex Tracker in the PHENIX Experiment

Sanjee Abeytunge

Department of Physics and Astronomy

Stony Brook University

Stony Brook, New York.

September 7, 2004


Topics of Discussion

• ALICE1LHCB readout chip and its format

• Data Simulator

• Drift Chamber FEM and the Interface board

• Test Setup

• Results

• Outlook

• Conclusions and Issues


ALICE1LHCB readout chip• Each chip reads 32 x 256 pixels

• Registers “hit” pixels; each pixel is a bit.

• Readout 32 x 256 bits at 10 MHz

• 8 chips (½ ladder ) are controlled and read out by the Pilot MCM

• Upon trigger Pilot MCM initiates readout of 8 chips sequentially on a 32-bit bus

• GOL allows transmission of 16-bit data @ 40 MHz

• GOL transmits via G-Link


ALICE1LHCB Format – according to the document available

• 100 ns long frames

• Each frame – 2 control words, 2 data words (16-bit wide)

• When there is no data – Idle frames ( 2 control words, 2 no data words)

• Bit specification identifies the event #, chip, first_word, last_word, fast_or etc.


ALICE Data Transmission Principle


Bit Configuration for Cycles & Framescav dav dav

In every frame Only Event Word frame “hit” Word frame


Synchronizing Pilot MCM to the Link Receiver

• Pilot MCM near the detector; Link receiver in the control room; needs synchronization

• Link receiver must identify the different cycles

• Two step process to synchronize:

1) Synch Pilot MCM to the Link Receiver

2) Synch Link receiver to the proper data block


Synch Pilot MCM to the Link Receiver

• Pilot near the detector; Receiver near the control room

• Identify slots with two control bits available in the G-Link protocol

• These two bits provide following signals:cav – Active when a control word available

Active during slot 0

dav – Active when a data word available

Active during slot 1a and slot 1b


Synch Link receiver to the proper data block

• Identify the first_word signal : Activate bit 28 & 29 during slot0-cycle0

• Identify the last_word signal : Activate bit 26 & 27 during slot0-cycle0

• fast_or signal: Activated if at least one pixel has

been “hit”


Data Simulator (DS)• Use National Instrument’s NI-

5411 pattern generator modules

• Use two modules: – One to simulate the “hit” data

– One to simulate the cav & dav signals

• Use LabVIEW to talk to the generators

• Provide clock and trigger from the interface board FEM-DS

• Use “stepped trigger” mode

ExternalTrigger

ExternalClock

Digital Data OutSHC50-68 cable


Data Simulator and FEM-DS flow diagram

16 bits

16 bits

FEM-DS Board

LabVIEW

PXI 8175Controller

NI 5411Pattern Gen 1

NI 5411Pattern Gen 1

Clock / Trigger Clock / Trigger


32-bit word

16

b

itsOur Input File in Frame format

3 Idle Frames

In stepped trigger mode 1st 8 16-bit words are repeated until

another trigger is received

EVENT

DATA

DATA

1

CONTROL

WORD

DATA

2

DATA

3

DATA

4

Event WordFrame

First “hit” WordFrame

Includes real data from the first two

data words

CONTROL

WORD

CONTROL

WORD

NO

DATA

NO

DATA

CONTROL

WORD

CONTROL

WORD

NO

DATA

NO

DATA

CONTROL

WORD

CONTROL

WORD

NO

DATA

NO

DATA

CONTROL

FIRSTWORD

CONTROL

WORD

EVENT

DATA

CONTROL

WORD

CONTROL

WORD

CONTROL

WORD

CONTROL

LASTWORD

DATA

511

DATA

512

Last WordFrame

Includes real data from the last two data

words

CONTROL

WORD

256 32-bit words


Bits and Data Input File

• It’s a 16-bit word

• Use the bit specs used by ALICE1LHCB

• A bit ‘on’ is 1, and a bit ‘off’ is 0

• Convert the binary number to decimal number

• Program it into the input file


Input Data File and the Input cav/dav File

• Remember we use the 2nd pattern generator for cav/dav – 16 bits available

• Only two bits are needed – one for cav and another for dav

• Use bit 1 (10) for dav and bit 2 (100)for cav

• This means, program 2 for dav and 4 for cav for every Data Word & Control Word


Drift Chamber FEM and the Interface board

• Use DC FEM to connect to the PHENIX DAQ

• Use an interface board to translate data from the data simulator into a format the DC FEM expects


Block Diagram of the DC FEM


FEM-DS Interface Board• Purpose:

– Separate Control Words and “hit” Data Words.– Buffer data coming in at 20 MHZ and send out at 40 MHz.

• Receives timing, control and reset signals from the FEM

• Transmits trigger and clock to the DS

• Receives input data ( “hit” Data and cav/dav) from the DS

• Transmits “hit” Data to the FEM


FEM-DS Board FuturebusConnectors

JTAG Conector

EE-Prom

Power In+5V

Power-OnReset

Fuse

+3.3V VolRegulator

Low ProfileConnectors

+2.5V VolRegulator

FPGA

Jumper

LVPECLto LVTTLconverter

FEM or GTMClk & TrigSelector

LimoConectors 50

Line Driver

Trigger OutBNCConnectors

Clock OutBNCConnectors

General I/OConnector


Control Signals

• Signals to the FEM_DS:

– 40 MHz clock (from FEM).

– Collect_Data signal (from FEM) tells the FEM-DS to tell the generator to initiate pattern generation.

– Read_Data signal (from FEM) tells the FEM-DS to start sending the data.

• Signals from the FEM-DS:

– Trigger (Collect_Data) (to DS)

– 40MHz clock (to DS)


Test Setup

• Includes key components of the PHENIX readout system – FEM, DCM & GTM

• FEM-DS interface board

• Data simulator


Clock/Trig,Readout Control, Mode-bits etc.

Data_Trigger ( Collect_Data)

40 MHz Clock

16 bit Data Words

2 bits for cav / dav

Data Simulator (DS)

256 16-bit Data Frames +3 16-bit Idle Frames +1 16-bit Event Frame = 1040 Words NI5411 Module 2

520 16-bit cav Words +520 16-bit dav Words = 1040 Words

NI5411 Module 1

PCLabVIEWInterface

PXI 8175Controller

16 bit Data Words + 2 bits for first / last words

40 MHz Clock

Read_Data

Collect_Data

FEM-DS Board

514Data

Words

1040 cav/davWords

+ 526 control Words

header +

514 Data Words

+ trailer

G-LinkReceiver

Initialization/Status

GTM PCG-LinkTranmitt

er

FEM

G-LinkTranmitter

G-LinkReceive

r

ARCNetFIFO

Data-flow

FPGA

LOGIC ANALYZER

514 word data stream

cav, dav and fastor can be

used for timing analysis of Data

Words

FEM


Test Setup

ENDAT / Clock

Data_Trig / Clock

ReadData

Collect_Data / Clock

Data

cav/dav

Data

“hit” Data

“hit” Data

GTM Simulator

Board

DCM Simulator

Board

FEMFEM-DS Board

Data Simulator

Logic Analyzer


Measurement for full readout cycle

30.06 µs

Fill frames for synch

CollectData

Data at DCM

Read_Data

Time needed to read 514 words


First “hit” Data Words

Data 4Data 3Data 2

Event Numbersand 1st word indication

Beam ClkCounter Data 1


End of the transmission

Data 512 andLast wordindication

Data 511 andLast wordindication

ParityWord

User Word

all zerosStatusUser Word

User Word


Outlook

• Bring chip test board and readout cards to SB

• Learn to operate the system

• Develop the FEM prototype


Issues• Optical Rx/Tx from/to detector needs clarification

due to lack of documentation. Should be resolved when chip & readout system available.

• G-Link replacement must have higher bandwidth– 2 chips: 2 x (2 x 256) = 1024 16-bit words– ½ ladder: 2chips x 4 = 4096 16-bit words– @ 40 MHz approximate readout time 120 µs– Need to transfer at a higher rate to avoid bottle neck– Full ladder readout time ~ 240 µs– Approximately factor of 5 increase in transmission

bandwidth

• ArcNet – PHENIX decision


Conclusions

• 256 pairs of 16-bit data words were read out in ~ 30 µs

• Equivalent to reading out 256 32-bit data words from one ALICE1LHCB chip

• Next phase of the prototype design of the FEM would be to readout 8 ALICE1LHCB chips, or ½ ladder within the time restrictions set by PHENIX


Acknowledgements

• Many thanks to – Axel Drees– Chuck Pancake

Sept. 7, 2004Silicon VTX Workshop - Brookhaven National Laboratory, Long Island, New York Prototype...

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Transcript of Sept. 7, 2004Silicon VTX Workshop - Brookhaven National Laboratory, Long Island, New York Prototype...