Sept. 2005EE37E Adv. Digital Electronics Lesson 1 CPLDs and FPGAs: Technology and Design Features.

Sept. 2005 EE37E Adv. Digital Electronics

Lesson 1

CPLDs and FPGAs: Technology and Design Features


Topics

• Fundamental Concepts• CPLDs vs FPGAs• CPLD Architectures• FPGA Architectures• Design Methods for FPGA-based Systems• Intellectual Property• System-on-chip• Reconfigurable Computing• Future FPGA Developments


1. Fundamental Concepts

• What are CPLDs and FPGAs?

– Complex Programmable Logic Devices (CPLDs) and Field Gate Arrays (FPGAs) are digital integrated circuits (ICs) that contain configurable (programmable) blocks of logic along with configurable interconnects between these blocks.

– Design engineers can configure (program) such devices to perform a tremendous variety of tasks


Classification of Digital ICs


They thing about CPLDs and FPGAs:

The thing that really distinguish an FPGA or a CPLD from an ASIC is the programmable feature.

a

Logic 1

y = 1 (N/A)&

b

Pull-up resistors

Potential links

NOT

NOT

AND

Let us consider a simple programmable function:

In order to make our function more interesting, we need some mechanism that allows us to establish one or more of the potential links.


a

Fat

Logic 1

y = 0 (N/A)&

Faf

b

Fbt

Fbf

Pull-up resistors

NOT

NOT

AND

Fuses

Fusible link technology

These fuses are similar in to household fuses.


a

Fat

Logic 1

y = a & !b&

b

Fbf

Pull-up resistors

NOT

NOT

AND

Programmed fusible links

Devices based on fusible-link technologies are said to be one-time programmable, or OTP. FPGAs don’t use them.


Antifuse Technologies

• Antifuse links are an alternative to fuse links.• An antifuse link is programmable by applying a

voltage across it.• An antifuse is given as follows:

(a) Before programming

Substrate

Metal

Oxide

Metal

Amorphous silicon column

(b) After programming

Polysilicon via


Other Technologies

• EPROM• EEPROM• FLASH• SRAM


2. CPLDs vs. FPGAs• CPLD

architecture

• Small number of PLDs on a single chip• Programmable interconnect between PLDs

PLDs = PALs, PLAs,or GALs


• FPGA architecture

• Much larger number of smaller programmable logic blocks.

• Embedded in a sea of lots and lots of programmable interconnect.


3. CPLD Architectures

• Identical individual PLD blocks (Xilinx “FBs”) replicated in different family members.– Different number of PLD blocks– Different number of I/O pins

• Many CPLDs have fewer I/O pins than macrocells– “Buried” Macrocells -- provide needed logic terms

internally but these outputs are not connected externally.– IC package size dictates # of I/O pins but not the total # of

macrocells.– Typical CPLD families have devices with differing resources

in the same IC package.


Xilinx CPLDs

• Notice overlap in resource availability in a particular package.


Xilinx 9500-family CPLD architecture

72 ==>XC9572


9500-family function blocks (FBs)

• 18 macrocells per FB• 36 inputs per FB (partitioning challenge, but also reason for

relatively compact size of FBs)• Macrocell outputs can go to I/O cells or back into switch matrix to

be routed to this or other FBs.


9500-series macrocell (18 per FB)

Up to 5 product terms

Programmableinversion or XORproduct term

Global clock or product-term clock

Set control

Reset control

OE control


9500-series product-term allocator

Share terms from above and below

programmablesteeringelements


9500-series I/O block


• Could be anything from a limited set of multiplexers to a full crossbar.

• Multiplexer -- small, fast, but difficult fitting• Crossbar -- easy fitting but large and slow

Switch matrix for XC95108


XC9500 Product Family

9536

Macrocells

Usable Gates

tPD (ns)

Registers

Max I/O

36 72 108 144 216

800 1600 2400 3200 4800

5 7.5 7.5 7.5 10

36 72 108 144 216

34 72 108 133 166

Packages VQ44PC44 PC44

PC84TQ100PQ100

PC84TQ100PQ100PQ160

PQ100PQ160

288

6400

10

288

192

HQ208BG352

PQ160HQ208BG352

9572 95108 95144 95216 95288


CoolRunner-II

• CoolRunner-II Family– Lowest system cost using advanced

features– Lowest power– High speed – Additional security– Smallest packages

• Including world’s smallest low cost package - QF32

– 1.5V, 1.8V, 2.5V & 3.3V interface– 2 to 4 I/O banks


CoolRunner-II CPLD Architecture

AIM: Advanced Interconnect Matrix

Sept. 2005EE37E Adv. Digital Electronics Lesson 1 CPLDs and FPGAs: Technology and Design Features.

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Transcript of Sept. 2005EE37E Adv. Digital Electronics Lesson 1 CPLDs and FPGAs: Technology and Design Features.