Semiconductor Device Modeling and Characterization – EE5342 Lecture 34 – Spring 2011
Semiconductor Device Modeling and Characterization – EE5342 Lecture 29 – Spring 2011
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Transcript of Semiconductor Device Modeling and Characterization – EE5342 Lecture 29 – Spring 2011
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Semiconductor Device Modeling and
Characterization – EE5342 Lecture 29 – Spring 2011
Professor Ronald L. [email protected]
http://www.uta.edu/ronc/
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Ideal 2-terminalMOS capacitor/diode
x
-xox
0SiO2
silicon substrate
Vgate
Vsub
conducting gate,area = LW
tsub
0
y
L
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Band models (approx. scale)
Eo
Ec
Ev
qox
~ 0.95 eV
metal silicon dioxide p-type s/c
qm= 4.1
eV for Al
Eo
EFmEFp
Eo
Ec
Ev
EFi
qs,p
qSi=
4.05eV
Eg,ox
~ 8 eV
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Flat band condition (approx. scale)
Ec,Ox
Ev
AlSiO2
p-Si
q(m-ox)= 3.15 eV
EFm
EFp
Ec
Ev
EFi
q(ox-Si)=3.1eV
Eg,ox
~8eV
cond band-flat for
VVV8.0
V
eV8.0EE
Then
eV85.0EE
If
sg
MS
fpfmFB
fpfm
fpc
qfp= 3.95e
V
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Equivalent circuitfor Flat-Band• Surface effect analogous to the
extr Debye length = LD,extr = [Vt/(qNa)]1/2
• Debye cap, C’D,extr = Si/LD,extr
• Oxide cap, C’Ox = Ox/xOx
• Net C is the series combOxextr,Dtot 'C1
'C1
'C1
C’Ox
C’D,extr
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Accumulation for
Vgate< VFB
SiO2
p-type Si
Vgate< VFB
Vsub = 0
EOx,x<0
x
-xox
0
tsubx,OxSi
Ox
Si
SiSix,OxOx
Ox
Oxx,Ox
E31
E
39.37.11
EE
0xV
E
holes
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Accumulationp-Si, Vgs < VFBFig 10.4a*
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Equivalent circuitfor accumulation• Accum depth analogous to the
accum Debye length = LD,acc = [Vt/(qps)]1/2
• Accum cap, C’acc = Si/LD,acc
• Oxide cap, C’Ox = Ox/xOx
• Net C is the series combOxacctot 'C1
'C1
'C1
C’Ox
C’acc
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Depletion for
p-Si, Vgate> VFB
SiO2
p-type Si
Vgate> VFB
Vsub = 0
EOx,x> 0
x
-xox
0
tsubx,OxSi
Ox
Si
SiSix,OxOx
Ox
Oxx,Ox
E31
E
39.37.11
EE
0xV
E
Acceptors
Depl Reg
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Depletion for
p-Si, Vgate> VFBFig 10.4b*
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Equivalent circuitfor depletion• Depl depth given by the usual
formula = xdepl = [2Si(Vbb)/(qNa)]1/2
• Depl cap, C’depl = Si/xdepl
• Oxide cap, C’Ox = Ox/xOx
• Net C is the series comb
Oxdepltot 'C1
'C1
'C1
C’Ox
C’depl
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Inversion for p-Si
Vgate>VTh>VFB
Vgate> VFB
Vsub = 0
EOx,x> 0
inversion for
threshold above
E Induced
depletes 0
E Induced
0xV
E
Si
Si
Ox
Oxx,Ox
Acceptors
Depl Reg
e- e- e- e- e-
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Inversion for p-Si
Vgate>VTh>VFBFig 10.5*
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Approximation concept“Onset of Strong Inv”• OSI = Onset of Strong Inversion occurs
when ns = Na = ppo and VG = VTh
• Assume ns = 0 for VG < VTh
• Assume xdepl = xd,max for VG = VTh and it doesn’t increase for VG > VTh
• Cd,min = Si/xd,max for VG > VTh
• Assume ns > 0 for VG > VTh
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MOS Bands at OSIp-substr = n-channelFig 10.9*
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Equivalent circuitabove OSI• Depl depth given by the maximum
depl = xd,max = [2Si|2p|/(qNa)]1/2
• Depl cap, C’d,min = Si/xd,max
• Oxide cap, C’Ox = Ox/xOx
• Net C is the series comb
Ox,mindtot 'C1
'C1
'C1
C’Ox
C’d,min
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MOS surface states**p- substr = n-channel
VGS s Surf chg Carr Den
VGS < VFB < 0 s < 0 Accum. ps > Na
VGS = VFB < 0 s = Neutral ps = Na
VFB < VGS s > 0 Depletion ps < Na
VFB < VGS < VTh s = |p| I ntrinsic ns = ps = ni
VGS < VTh s > |p| Weak inv ni< ns < Na
VGS = VTh s = 2|p| O.S.I . ns = Na
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n-substr accumulation (p-channel)Fig 10.7a*
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n-substrate depletion(p-channel)Fig 10.7b*
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n-substrate inversion(p-channel)Fig 10.7*
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Values for gate workfunction, m
V 17.5q/E :Si-poly p
V 05.4 :Si-poly n
V 55.4 :W ,Tungsten
V 65.5 :Pt ,Platinum
V 6.4 :Mo ,Molybdenum
V 1.5 :Au ,Gold
V 28.4 :Al ,umminAlu
gSim
Sim
m
m
m
m
m
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Values for ms
with metal gate
02586.0V ,12.1E ,19E8.2N
10E45.1n ,05.4 ,28.4
NN
lnV :Si-n to Al
nN
lnVq2
E
n
NNlnV :Note
n
NNlnV :Si-p to Al
tgC
iSiAlm,
d
CtSiAlm,ms
i
at
g2i
aCt
2i
aCtSiAlm,ms
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Values for ms
with silicon gate
i
dt
g
d
Ct
d
CtSi
gSims
i
at
g2i
aCt
2i
aCtSiSims
nN
lnVq2
E
NN
lnV :Note
NN
lnVq
E :Si-n to poly p
nN
lnVq2
E
n
NNlnV :Note
n
NNlnV :Si-p to poly n
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Fig 10.15*
ms(V)
NB (cm-3)
Typical ms values
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Flat band with oxidecharge (approx. scale)
Ev
AlSiO2
p-Si
EFm
Ec,Ox
Eg,ox
~8eV EFp
Ec
Ev
EFi
'Ox
'ss
msOxmsFB
Ox
Oxc
Ox
'ss
x
ssm
ss
CQ
VV
xV
dxdE
q1Q
E
surface gate the on
is Q'Q' charge
a cond FB at then
bound, Ox/Si the at
is Q' charge a If
q(fp-ox)q(Vox
)q(m-
ox)
q(VFB
) VFB= VG-VB, when Si bands
are flat
Ex
+<--Vox-->-
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Flat-band parametersfor n-channel (p-subst)
0nN
lnVq2
E
n
NNlnV
gate, Si-poly n a For
den chg Ox/Si the is 'Q ,x
'C
'C'Q
V :substratep
i
at
g2i
actms
sms
ssOx
OxOx
Ox
ssmsFB
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Flat-band parametersfor p-channel (n-subst)
0nN
lnVq2
E
n
NNlnV
q
E gate, Si-poly p a For
den chg Ox/Si the is 'Q ,x
'C
change) (no 'C'Q
V :substraten
i
dt
g2i
dvtms
gsms
ssOx
OxOx
Ox
ssmsFB
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Inversion for p-Si
Vgate>VTh>VFB
Vgate> VFB
Vsub = 0
EOx,x> 0
inversion for
threshold above
E Induced
depletes 0
E Induced
0xV
E
Si
Si
Ox
Oxx,Ox
Acceptors
Depl Reg
e- e- e- e- e-
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Approximation concept“Onset of Strong Inv”• OSI = Onset of Strong Inversion occurs
when ns = Na = ppo and VG = VTh
• Assume ns = 0 for VG < VTh
• Assume xdepl = xd,max for VG = VTh and it doesn’t increase for VG > VTh
• Cd,min = Si/xd,max for VG > VTh
• Assume ns > 0 for VG > VTh
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MOS Bands at OSIp-substr = n-channel
Fig 10.9*
2q|p|
qp
xd,max
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Computing the D.R. W and Q at O.S.I.
Ex
Emax
x
aSi
x Nq
dxdE
a
pSid qN
x
22
,max
parea 2
,max,max' dad xqNQ
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Calculation of thethreshold cond, VT
Ox the across Q' induce to added
voltage the isV where V,VV
sub)-p sub,-(n xNqQ' is
charge extra the and x of value
the reached has region depletion
The inverted. is surface the when
reached is condition threshold The
d,max
FBT
d,maxBd,max
d,max
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Equations forVT calculation
substr-n for 0 substr,- p for 0V
qN
22x ,xNqQ'
0nN
V 0Nn
V
C
Q2VV substrnp
da
npd,maxd,maxa,dd,max
i
dtn
a
itp
Ox
dnpFBT
,
,
',max
,
,ln,ln
':,
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Fully biased n-MOScapacitor
0
y
L
VG
Vsub=VB
EOx,x> 0
Acceptors
Depl Reg
e- e- e- e- e- e- n+ n+
VS VD
p-substrate
Channel if VG > VT
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MOS energy bands atSi surface for n-channel
Fig 8.10**
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Computing the D.R. W and Q at O.S.I.
Ex
Emax
x
aSi
x Nq
dxdE
a
SBpSid qN
VVx
)(22,max
)(2 SBp VVarea
,maxda,maxd xqNQ
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Q’d,max and xd,max forbiased MOS capacitor
Fig 8.11**
xd,max
(m) )2-
d,max
(cm
q
Q'
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Fully biased n-channel VT calc
0V ,
qN
VV22x
,xNqQ' ,0Nn
lnV
VV'C
'Q2VVV
VV :substratep
a
CBpd,max
d,maxad,maxa
itp
FBOx
,maxdpFBCT
Tthreshold at ,G
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n-channel VT forVC = VB = 0
Fig 10.20*
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References
* Semiconductor Physics & Devices, by Donald A. Neamen, Irwin, Chicago, 1997.
**Device Electronics for Integrated Circuits, 2nd ed., by Richard S. Muller and Theodore I. Kamins, John Wiley and Sons, New York, 1986