sem_avi_kaj
7
1 DIGITAL ELECTRONICS, M.TECH (PART TIME) INPUT CIRCUITS A simple input circuit consisting of a transmission gate activated by an enable (E) signal and its complement is shown in Fig1 FIG1: (a) Input series transmission gate circuit and (b) its symbolic representation. The incoming signal A is fed into the transmission gate through the protection network (PN) from the bonding pad Of the chip. The enable signal is generated on-chip and controls the gating of the input signal as * X=A, when E=0 * X = high-impedance state, otherwise Any unused chip input terminals should be tied to V DD or Vss using pull-up or pull-down resistors externally. Some input pad circuit modules have a built-in internal pull-up or pull-down resistor or active load (normally-on transistor) with a resistance of 200 kΩ to 1 MΩ AVINASH. N. J INPUT CIRCUITS
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1DIGITAL ELECTRONICS,M.TECH (PART TIME)INPUT CIRCUITSA simple input circuit consisting of a transmission gate activate !" an ena!le (E) signalan its complement is s#o$n in %ig1%I&1' (a) Input series transmission gate circuit an (!) its s"m!olic representation.T#e incoming signal A is fe into t#e transmission gate t#roug# t#e protection net$or((P))fromt#e!oningpa*ft#ec#ip.T#eena!lesignal isgenerateon+c#ipancontrols t#e gating of t#e input signal as, -.A, $#en E./, - . #ig#+impeance state, ot#er$iseAn" unuse c#ip input terminals s#oul !e tie to 011 or 0ss using pull+up or pull+o$n resistors e2ternall". 3ome input pa circuit moules #ave a !uilt+in internal pull+upor pull+o$n resistor or active loa (normall"+on transistor) $it# a resistance of 4// (5to 1 M5%I&4'. Inverting input circuit $it# (a) protection net$or(, an (!) s"m!olic vie$.A0I)A3H. ). 6I)P7T CIRC7IT34DIGITAL ELECTRONICS,M.TECH (PART TIME)%I&4 s#o$saninverting input circuit consisting of t#e protection net$or( an a CM*3inverter T"pical values for0I8an 0IHare /.9011an /.: 011,respectivel" for a!out9/;noise margins. T#is !asic input circuit can !e esigne to receive TT8 signals forCM*3 logic circuits !" aual to /.= 0 s#oul !e interprete lo$ an inputvoltages greater t#anor e>ual to4./0s#oul!einterprete#ig#. After t#einputprotectioncircuit, t#eincomingsignals #aveto!elevel+s#iftetoaesira!lelevel,epeningon t#eirvoltage levels.%orinstance,if t#e incoming signal isfrom a TT8river, t#en its lo$ voltage can !e as #ig# as /.= 0 an its #ig# output voltage can !e aslo$ as 4./ 0. T#erefore a careful level s#ifting #as to !e one to translate suc#logic levels to corresponingM*3 gate voltage levels as s#o$n in%ig. 9. %I& 9' (a) TT8 to CM*3 level c#aracteristic curve s#ifting an (!) t#e corresponingvoltage transferT#e level s#ifting !et$een a TT8 river an a CM*3 gate can !e ac#ieve !" properl"esigning t#e ratio !et$een pM*3 an nM*3 transistors of t#e receiving CM*3 invertergate. A practical met#o is to auations, $e fin t#at %or e2ample, if @n . 9@p an 0T), . +0TP. 1./ 0 an 011 . A 0, t#en in orer to ac#ievet#e nM*3+to+pMB3 ratio must !e%rom t#e a!ove calculation, $e etermine t#at r . C.A an$#ere 0*7T, satisfies t#e follo$ing current e>uation'Com!ining t#ese t$o e>uations, $e o!tain0out . D.E: 0A0I)A3H. ). 6I)P7T CIRC7IT3DDIGITAL ELECTRONICS,M.TECH (PART TIME)an, #ence8i(e$ise,$#ere 0*ut satisfies t#e follo$ing current e>uationCom!ining t#ese t$o e>uations, $e o!tain3olving for 0*7T an 0IH "iels'0*7T. / 4/C 0 an 0IH . 1.D: 0T#isesignappearstomeet t#eesigno!
