SEMATECH Workshop on 3D Interconnect Metrology - FogaleNanotech...SEMATECH Workshop on 3D...

SEMICONDUCTOR & OPTICAL

METROLOGY SOLUTION

TSV Copper Nails FOGALE & 3D IC Technologies Backside processing Others

SEMATECH Workshop on 3D Interconnect Metrology SEMATECH Workshop on 3D Interconnect Metrology

SEMATECH Workshop on 3D Interconnect Metrology

11 July, 2012

A versatile optical system for metrology and

inspection of 3D IC TSV integration processes

Gilles Fresquet


METROLOGY SOLUTION



confidential

SUMMARY

1. FOGALE 3D IC organization

2. Technologies

3. Application: TSV

4. Application: Back side processing

5. Application: Die stacking

6. Others: Out of the plane registration

.


METROLOGY SOLUTION



FOGALE Nanotech

•Hardware development

•Software development

•Integration

•Tool development (Beta)

•Automation

•New applications/market

analysis & potential solutions

review

R&D

Applications

Technology Beta tools &

upgrades

Applications/technologies

Common lab in Orsay: IEF/FOGALE

Research/application

Staff: 16 engineers & technicians

FOGALE Headquarter

NIMES

Staff: 47

Application Lab

Aix en Provence Manufacturing

Toulouse

ORGANIZATION

3D IC TSV FOGALE

project:

Topics: •3D IC TSV

•WLP

•E-WLB

•Hermiticity

FOGALE Asia:

ITRI Application lab

FRANCE


METROLOGY SOLUTION



Technology:

A versatile optical system for metrology and inspection of 3D IC TSV integration processes

Optical Metrology: Multiple sensors configuration

IR sensor technology (TSV, RST, T, TTV,Bow,warp)

Multi wavelength bandwidth IR interferometer for TSV and Thickness measurement

Chromatic Confocal (Roughness, surface profiling, Edge trim, large trenches, large bow)

WL or IR microscopy for inspection and spot positioning/interface defect inspection and our of the

plane registration

Fiber based technologies

WL & NIR Objectives


METROLOGY SOLUTION



IR interferometer: Example OCT (temporal mode) for thickness measurement


METROLOGY SOLUTION



IR interferometer for High A/R TSV

Absolute height measurements with a single beam larger than pattern:

Single point IR interferometrer: Fiber based interferometer

Core of the system: low coherence interferometer based on optical fibers and using an infrared broadband source:

The light source: Super luminescent diode (SLD)

A spatial filter retains only the information of phase difference between the two groups of waves

The system combines microscopy and metrology for spot positioning and pattern rec.

Internal reference

mirror

Interferometer

R1

R2

Fiber


METROLOGY SOLUTION



3D Surface Profiling: Confocal Chromatic technology

Spectrometer

Light source

Control unit

Probe

Object surface Measurement range

Optical fiber

FPGA Calculator

Single point method: no z-scan required due to multi confocal points

x,y scan only


METROLOGY SOLUTION



3D Die stacking requires new processes and corresponding metrology and control solutions:

FEOL

Transistor manufaturing

TSV formation

Through Silicon Vias

BEOL

Transistors interconnection

Wafer Thinning Backside processing and

Die stacking PROCESS FLOW:

Process control solutions:

Std process New process

TSV depth

measurement

Thickness & Bonding inspection

copper nails dimensional control & die stacking process control


METROLOGY SOLUTION



200mm wafer: TSV

TSV diameter : 5 µm

TSV Depth: 25 to 35 µm

300mm wafer: TSV

TSV diameter : down to 3 µm

TSV Depth: 40 to 50 µm

Used platform: IMEC 65nm node CMOS

TSV: After first metallization

VIA # DEEPROBE SEM (average)

1 33.77 µm 34.35µm

2 34.13µm 34.35µm

3 34.54 µm 34.35µm

4 34.04 µm 34.35µm

5 33.93µm 34.35µm

Mean 34.082 µm 34.35µm

1.Accuracy: Cross referencing, correlating DeeProbe measurements with Via depth measurements resulting from X-SEM, and FIB inspections. spec: < 0.5µm

2. Reproducibility: Reproducibility of the measurements when identical structures are measured multiple times with some intermittent delay Spec: < 0.5 µm and etch uniformity study.

2 3 4 5

6 7 8 9

1

Experiment:

300 mm wafer

9 points per wafer

Repeat: 20 times

s < 0.08 µm

3.Linearity: Measurement of etched wafer with variable depth Measurement across 300 mm wafer diameter

Note: SEM measurement accuracy is estimated in the 0.1 to 0.5 µm range

Via depth

50 µm

45 µm

40 µm

35 µm

30 µm

25µm

20 µm

15 µm

10 µm

Die #

TSV


METROLOGY SOLUTION



Die #

µm

“M” shape of depth across 300 wafer diameter

• Measure every die (37) over the west-east axis

Edge Center Edge

INFLUENCE OF HARD MASK AND TOP LAYER

Mono and stacked layers: SiC, Si3N4, SiO2, STI etc…

No influence of top hard mask layer

SPC control chart exploitation:

SECS GEM communication implemented

Deep RIE Cp/Cpk calculation

Deep RIE process tuning

TSV depth uniformity

Courtesy of IMEC


METROLOGY SOLUTION



15 µm

Chip Thickness Average 3 sigma

a 97.062 0.251

b 95.45 0.191

c 97.925 0.224

d 97.092 0.207

10 µm

7 µm


a 86.736 0.258

b 85.521 0.229

c 85.932 0.26

d 87.67 0.304


a 77.691 0.209

b 77.674 0.177

c 78.962 0.303

d 78.142 0.207

TSV: Depth versus diameter


METROLOGY SOLUTION



Dual sensing technology: Microscopy capability and pattern recognition

Spot positioning

White light microscopy

IR microscopy

Spot positioning

Substrate

Die

Si 1

Glass or Si O2 Die

BACKSIDE Processing: Wafer on temporary carrier wafer thinning


METROLOGY SOLUTION



T,TTV, Bow, Warp after bonding

Layer Bow (um) Warp (um) Average Thickness (um)

TTV (um)

All -328.706 375.119 1709.816 5.865

Si 775.947 <0.5um

Glue 15. 457 2.7

Carrier 776.9 <0.5µm

TTV Glue

Bow/Warp

Interface defect detection


METROLOGY SOLUTION



Layer Average Thickness (um) TTV (um)

All 880.670 5.694

Si 94.715 3.234

T,TTV, Bow, Warp after grinding

Edge trimming dimensional control with confocal chromatic

Applications: L & z dimensions

L

z

Z= 74µm

L= 1246 µm

TTV Backside Roughness


METROLOGY SOLUTION



RST Measurement

Before Back grind

NIR µcroscope

+ Multiple wavelenght IR intefrerometer

After back grind

Min Thickness: 0.44 . (l 2source / Dl)

With l: wavelength And Dl: source bandwidth

Multiple Source bandwidth depending on process step

4.5

4.7

4.9

5.1

5.3

5.5

5.7

5.9

-150 -100 -50 0 50 100 150

RST before TSV reveal across 300mm wafer diameter

RST

µm

Dl = 100 nm

Dl = 0.9µm


METROLOGY SOLUTION



WLI for Die Level

TSV reveal: Copper nails height with CC300 and WLI

CC100 for wafer Level


METROLOGY SOLUTION



Substrat

Die

Correlation between electrical results and inter Die distance

ref

Non homogeneous

force during bonding

process

Die Stacking

35

35

34

34

25

32

26

31

27

31

31

31

28

26

27

34

36

32

32

31

32

34

29

30

30

31

32

26

25

30

W

Top surface profile

Die interface thickness mapping

IR inspection of interface


METROLOGY SOLUTION



Related Product:

T-MAP DUAL 3D

Unique solutions for R&D and pilot lines3D IC TSV


METROLOGY SOLUTION



Special thanks to Victor Vartanian & SEMATECH team

Thanks for your attention!!

Have a nice SEMICON West show!

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