EXPERIMENT NO:1

INTRODUCTION TO PSPICE

OBJECTIVE: To study about Pspice simulator.

Launch the ORCAD schematic editor by double-clicking on the ORCADdemoicon.Click on File from the main menubar and then select Open New Project.You should then see the following dialog box.

Use the Browse button to select the location where youwould like to save your files. Make sure the Analog or Mixed A/Doption has been selected. You may then click the OK button.

The following dialog box will appear.

Make sure to select Create a blank project and then click the OKbutton.

Let's create a simple voltage divider i.e. two resistors, each with a value of 10K. We will drive the series combination with a sinusoid and observe the voltage at the node between the two resistors. Voltage

division principles tell us that the voltage should be half of the input voltage.From the menu at the top, select Place and then Part (Shift-P if you wish can be used as a shortcut).The following dialog box will appear.

Click on the Add Library button and choose the ANALOG library. You will see the following

Select the R i.e. resistor component. This can be done by doubleclicking on the R. Place the component by clicking somewhere near the middle of the schematic page. Click again and place R2. You should

then hit the Esc key to exit the place mode. The resistor R2 should still be selected as is shown on the next page.

With resistor R2 selected, right mouse click on it. A menu will appear. Select the Rotate option. You should observe the following

Right mouse click on the 1k value on the R1 component. A menu will appear. Select Edit Properties. The dialog box shown below will appear. Change the value to 10K.

Do the same for the R2 component.At this point we should probably save our work. This can be done by

either typing Ctrl-S or by clicking on the diskette icon in the toolbar or by going to the File menu and selecting Save.Do a Place Part again. This time add the Source library, From the Source library, select VSIN. Place the sinewave generator and change the parameter values. VOFF should be 0. VAMPL should be set to 1.FREQ should be set to 1k.

Now place the ground symbol. Choose Place and Ground. Let's use the GND/CAPSYM symbol. Any of the grounds would work but this is my personal favorite!

In order for PSPICE to simulate the circuit correctly, we must change the name of the GND symbol from GND to 0. This is because in all versions of SPICE, circuit ground must always be assigned a nodename of

0. We can do this by selecting the GND symbol. Now, right mouse click on the symbol. A menu will pop up. Select the Edit Properties option.In the Name field where it says GND, change this to 0 as I have done

below. Use a right mouse click on the Name field to highlight the field and click on display. The Display Properties dialog box will appear.

Your circuit should look like the figure below.

It is now time to wire the components to one another. This can be done by placing a wire. Place Wire and Shift-w is the shortcut! Click on a pin then drag to mouse to another pin and click again.When the components are all wired together, leave the wiring mode by hitting the Esc key.Your circuit should look like mine below.

We now are ready to simulate the circuit. We must first prepare a simulation profile where we describe how we want the simulation to be performed. To do this select PSpice and then New Simulation Profile.

The following dialog box appears. I have entered a name for the simulation. I decided to call it tran. You may call it anything you wish. Click on the Create button to create the profile

We also need to tell PSPICE which nodes we would like to plot. We do this by going to the main menubar and selecting PSpice. We then select Markers and Voltage. We place the marker on the output of the voltage divider as shown below.

For comparison purposes, let's also place a marker on the input node as illustrated in the figure below.

At this point we should probably save our work. This can be done by either typing Ctrl-S or by clicking on the diskette icon in the toolbar or by going to the File menu and selecting Save.We are now ready to run the PSPICE simulation. We do this by selecting PSpice from the main menubar and then Run. We could also click on the the arrow icon on the toolbar. After a few seconds another window will open and you will see the following simulation traces

EXPERIMENT NO:5CLIPPER CLAMPER CIRCUIT

OBJECTIVE: To study &simulate clipper and clamper circuit.

PROGRAM:

*DIODE CLIPPER CIRCUIT

VIN10SIN(0101KHZ)

R1

201MEG

VDC30DC5

D1

32DIODE

.MODELDIODED

.TRAN20US3MSUIC

.PLOTTRANV(2)V(1)

.OP

.PROBE

.END

OUTPUT:

PROGRAM:

* DIODE CLAMPER CIRCUIT

VIN 1 0 SIN(0 10 1KHZ)

*CAPACITOR WITH AN INITIAL VOLTAGE OF -15V

C1 1 2 1UF IC=-15V

R1 2 0 1MEG

VDC 3 0 DC 5

D1 3 2 DIODE

.MODEL DIODE D

.TRAN 20US 3MS UIC

.PLOT TRAN V(2) V(1)

.OP

.PROBE

.END

OUTPUT:

CIRCUIT DIAGRAM(NEGATIVE CLIPPER):

OUTPUT:

CIRCUIT DIAGRAM(CLAMPER):

OUTPUT:

CIRCUIT DIAGRAM(BIASED CLAMPER):

OUTPUT:

EXPERIMENT NO:3CHARECTERISTIC OF DIODE,BJT AND FET

OBJECTIVE: To study &simulate characteristic of diode BJTand FET

*DIODE CHARACTERISTICS

PROGRAM:

VD 1 0 DC 0V

D1 1 2 D1N914

VX 2 0 DC 0V ;Measures diode current

.MODEL D1N914 D(IS=3.93E-9 RS=1 BV=100V IBV=5E6 CJO=1.7PF TT=2NS)

.TEMP 50 100 150 ;Operating temperatures:50,100,150

.OPTIONS NOPAGE NOECHO

OUTPUT:

*NPN BJT CHARACTERISTICS

PROGRAM:

IB01DC1MA

VCE20DC12V

Q1210Q2N2222A

.MODELQ2N2222ANPN(IS=2.105E-16BF=173VA=83.3VCJE=29.6PF

+CJC=19.4PF TF=489.88PS TR=4.9NS)

.DCVCE010V0.0SVIB01MA200UA

.PROBE

.END

OUTPUT:

*N-CHANNEL JFET CHARECTERISTIC:PROGRAM:

VGS 1 0 DC 0V

VX 3 2 DC 0V ;A dummy voltage source of 0v

VDD 3 0 DC 12V

J1 2 1 0 JMOD

.MODEL JMOD NJF (IS=100E-14 RD=10 RS=10 BETA=1E-3 VTO=-5)

.DC VDD 0 12 0.2 VGS 0 4 -1

.PLOT DC I(VX)

.PROBE

.ENDOUTPUT:

CIRCUIT DIAGRAM(DIODE CHRECTERISTIC):

OUTPUT:

CIRCUIT DIAGRAM(JFET CHARECTERISTIC):

OUTPUT:

EXPERIMENT NO:7DARLINGTON PAIR CIRCUIT

OBJECTIVE: To study &simulate the darlington pair circuit.

PROGRAM:

.OPTIONS NOPAGE NOECHO

VCC 2 0 DC 12V

VIN 1 0 DC 5V

Q1 2 1 3 QM

Q2 2 3 4 QM

RB 2 1 47K

RE 4 0 4.7K

.MODEL QM NPN (BF=100 BR=1 RB=5 RC=1 RE=0 VJE=0.8 VA=100)

.TF V(4) VIN

.END

OUTPUT:

SMALL SIGNAL BIAS SOLUTION TEMPERATURE = 27.000 DEG C

NODE VOLTAGES:

( 1) 5.0000 ( 2) 12.0000 ( 3) 4.3560 ( 4) 3.5909

VOLTAGE SOURCE CURRENTS

NAME CURRENT

VCC -9.129E-04

VIN 1.489E-04

TOTAL POWER DISSIPATION 1.02E-02 WATTS

**** SMALL-SIGNAL CHARACTERISTICS

V(4)/VIN = 9.851E-01

INPUT RESISTANCE AT VIN = 4.696E+04

OUTPUT RESISTANCE AT V(4) = 6.677E+01

JOB CONCLUDED

TOTAL JOB TIME 0.00

EXPERIMENT NO:2

POTENTIAL DIVIDER CIRCUIT

OBJECTIVE: To study &simulate the Potential divider circuit.

PROGRAM:

* POTENTIAL DIVIDER

VS 1 0 DC 10V

R1 1 2 1KOHM

R2 2 3 1KOHM

R3 2 4 1KOHM

VX 3 0 DC 0V

VY 4 0 DC 0V

.DC VS 10V 30V 10V

.PRINT DC V(2) I(VX) I(VY)

.PLOT DC I(VY)

.PROBE

.END

OUTPUT:

CIRCUIT DIAGRAM(POTENTIAL DIVIDER):

OUTPUT:

EXPERIMENT NO:6

BJT CE AMPLIFIER

OBJECTIVE: To study &simulate the BJT CE amplifier circuit.

PROGRAM:*Amplifier

VIN 1 0 AC 1 SIN(0 0.01 1KHZ)

VCC 0 7 DC 15V

RS 1 2 500

R1 7 3 47K

R2 3 0 2K

RC 7 4 10K

RE 5 0 2K

RL 6 0 20K

C1 2 3 1UF

C2 4 6 1UF

CE 5 0 10UF

XQ1 4 3 5 TRANS

.SUBCKT TRANS 6 7 5

RB 1 2 100

RE 3 5 1

RC 4 6 10

RPI 2 3 1K

CPI 2 3 2PF

RU 2 4 1MEG

CU 2 4 1PF

RO 4 3 100K

CSS 6 0 2PF

VI 1 7 DC 0V

F1 3 4 VI 20

.ENDS TRANS

.OPTIONS NOPAGE NOECHO

.TRAN 50US 2MS

.AC DEC 10 1HZ 10KHZ

.PLOT TRAN V(4) V(6) V(1)

.PLOT AC VM(6) VP(6)

.PROBE

.ENDOUTPUT:

EXPERIMENT NO:4RECTIFIERS

OBJECTIVE: To study &simulate the rectifier circuits.(a)Circuit diagram Half wave rectifier:

OUTPUT (Transient analysis):

(b) Circuit diagram :Full-wave rectifier with center tapped transformer.

OUTPUT:

(C)Circuit diagram Full wave bridge rectifier:

OUTPUT:

EXPERIMENT NO:8INTEGRATOROBJECTIVE: To study &simulate the integrator circuits.PROGRAM:

*INTEGRATOR CIRCUIT

VIN 1 0 PWL (0 0 1NS -1V 1MS -1V 1.0001MS 1V 2MS 1V

+ 2.0001MS -1V 3MS -1V 3.0001MS 1V 4MS 1V)

R1 1 2 2.5K

RF 2 4 1MEG

RX 3 0 2.5K

RL 4 0 100K

C1 2 4 0.1UF

XA1 2 3 4 0 OPAMP

.SUBCKT OPAMP 1 2 7 4

RI 1 2 2.0E6

GB 4 3 1 2 0.1M

R1 3 4 10K

C1 3 4 1.5619UF

EA 4 5 3 4 2E+5

RO 5 7 75

.ENDS OPAMP

.TRAN 50US 4MS

.PLOT TRAN V(4) V(1)

.PROBE

.END

OUTPUT:

EXPERIMENT NO:11Z-TRANSFORMOBJECTIVE: Write a MATLAB program to find Z-transform of a given function.PROGRAM:n=sym('n');

a=sym('a');

w=sym('w');%x1=(1/2)^n

x1=(1/2)^n;

y1=ztrans(x1);

disp('Z transform of (1/2)^n');

disp(y1);

w1=iztrans(y1);

disp('inverse Z-transform of y1');

disp(w1);%x2=cosw*n

x2=cos(w*n);

y2=ztrans(x2);

disp('Z transform of cos(w*n)');

disp(y2);

w2=iztrans(y2);

disp('inverse Z-transform of y2');

disp(w2);%x3=(a^n)*cos(w*n)

x3=cos(w*n);

y3=ztrans(x2);

disp('Z transform of (a^n)*cos(w*n)');

disp(y3);

w3=iztrans(y3);

disp('inverse Z-transform ofy3');

disp(w3);COMMAND WINDOW:Z transform of (1/2)^n

2*z/(2*z-1)

inverse Z-transform of y1

(1/2)^n

Z transform of cos(w*n)

(z-cos(w))*z/(z^2-2*z*cos(w)+1)

inverse Z-transform of y2

cos(w*n)

Z transform of (a^n)*cos(w*n)

(z-cos(w))*z/(z^2-2*z*cos(w)+1)

inverse Z-transform ofy3

cos(w*n)

EXPERIMENT NO:12POLES AND ZEROS FROM GIVEN TRANSFER FUNCTION

TRANSFER FUNCTION FROM GIVEN POLES AND ZEROSOBJECTIVE: Write a MATLAB program,

(a) To find poles and zeros from a given transfer function.

(b) To find transfer function from given poles and zeros.% To find poles and zeros from a given transfer function.

b = [2 3];

%coefficient of numerator

a = [1 0.4 1];

%coefficient of denominator

[z,p,k] = tf2zp(b,a)

zplane(b,a);

COMMAND WINDOW:

z =

-1.5000

p =

-0.2000 + 0.9798i

-0.2000 - 0.9798i

k =

2

%To find transfer function from given poles and zeros.z=input('enter the zeros');

z=z';

p=input('enter the poles');

p=p';

k=10;

[n,d]=zp2tf(z,p,k);

disp('numerator coefficients are:');

disp(n);

disp('denominator coefficients are:');

disp(d);

zplane(n,d);

title('location of poles and zeros in Z plane');

COMMAND WINDOW:enter the zeros[1 4 6]

enter the poles[2 5 8]

numerator coefficients are:

10 -110 340 -240

denominator coefficients are:

1 -15 66 -80

EXPERIMENT NO:9LOGIC GATESOBJECTIVE: To study &simulate Digital Logic gates

Circuit diagram AND gate:

OUTPUT:

Circuit diagram OR gate:

OUTPUT:

Circuit diagram NOT gate:

OUTPUT:

Circuit diagram NAND gate:

OUTPUT:

Circuit diagram NOR gate:

OUTPUT:

EXPERIMENT NO:

ADDER CIRCUITOBJECTIVE: To study &simulate Half adder and Full adder circuits.

Circuit diagram Half Adder:

OUTPUT:

Circuit diagram Full Adder :

OUTPUT:

EXPERIMENT NO:13PCB DESIGNINGOBJECTIVE: To study PCB designing using ORCAD capture and layout.STEP I: Starting a new project

Before you make a PCB layout, you need to have a circuit to layout. You will use Capture to make the schematic, so the first step is to start the Capture Once Capture is running, you should have a blank Capture session frame and a session log. Go to the file dropdown menu and navigate to file, new and click project as shown in figure.

The new project dialog box will pop up as shown in the figure.

Type a name for your project, and then select the PC board wizard radio button. Click ok. After you click OK, the PCB Project Wizard dialog box shown in figure will pop up. For now circuit simulation will not be performed, so leave the enable project simulation box unchecked. Click next.

After you click next, the PCB project wizard dialog box shown in figure will pop up. This box allows you to add specific libraries to your project. Scroll down until you find the discrete.olb library, highlight it by clicking on it, and then click the add button and then click finish. This completes the project set up. You should have a project manager window in the left side of the capture session frame as shown in figure.

You may also have a schematic window in the work space. If the schematic is not open, expand the projectname.dsn directory by clicking the - box that is to the left of the projectname.dsn icon. Click the - box next to the schematics folder, and then double click the file called page1. The schematic page should open.

STEP II: Placing parts

To add parts to your schematic, make the schematic page active and select place from the part dropdown menu or press P on your keyboard.

After you click ok you should immediately return to the schematic page.

STEP III: Wiring or connecting the parts

Next, connect the parts with wires. To place wires hit the W key or select Place Wire from the Place dropdown menu. Once you have finished connecting the circuit press the ESC key or right click and select End Wire to stop the place wire cursor and get the pointer back.

STEP IV: Creating the layout netlist in capture

Once all of the connections are complete the next step is to create a netlist (an ASCII text fi le that describes the circuit). Begin by making the project manager window active. As shown in figure, select tools, create netlist from the tools menu. The create netlist dialog box will pop up as shown in figure.

From the create netlist dialog box, select the layout tab and then save it to the current directory and remember where the netlist file is saved. Click finish to generate the netlist. Capture will display a warning text box stating Design Path/Yourname.dsn will be saved prior to netlisting. Click ok. Capture will then generate the netlist and report the results in the session log. At this point you have generated a netlist file with a .MNL extension that layout can use.STEP V: Designing the PCB with layout - Starting layout and importing the netlist

Now you will use the netlist to route a board using layout. Begin Orcad layout. Once layout is up and running you will be presented with a blank session frame initially. To begin working on your board you need to tell layout what kind of board you want to use and then import the netlist file you generated with capture into that board type. Begin by selecting new from the session frames file menu. An auto ECO dialog box will pop up as shown in figure. There are three pieces of information that need to be entered into the auto ECO dialog box. You will add the first two pieces of information in the TCH and the MNL text boxes and layout will enter a default value into the third MAX text box. The first step is to select a board technology template. Click the browse button across from the TCH text box and navigate to the tools-layout-data folder and select the default technology template as shown in figure. Once the technology file is assigned you need to select the Layout netlist .MNL file you generated in Capture. To do so, click the browse button across from the MNL text box and locate the .MNL file you created in capture. Once you have entered these first two pieces of information the wizard will fill in the MAX file information for you with a default name as shown in the figure. The MAX file is layouts project file that contains the information needed to build your board. You can use the default name or save it with a different name. Click the apply ECO button at the bottom of the dialog box. You do not need to make any changes to the options settings at this point.

Layout will immediately go about setting up the project environment. When setting up the project layout checks for footprint assignments for each part in the netlist. If no footprint was assigned or if a footprint that layout does not know about is assigned to a part, layout will ask you to choose a footprint with the link footprint to component dialog box shown in the figure. If you get the link footprint dialog box click on the link existing footprint to component button. Layout will initiate the footprint library utility shown in the figure. Depending on how layout has been used before you may have libraries different from those shown in the figure. If you are using the demo version you should at the very least have the ex-gui library which you should select. In the Footprints box below the Libraries box, find the SIP/TM/L.200/2 footprint. A picture of the footprint will be displayed in the preview window on the right of the dialog box. Once the auto ECO utility has completed assigning the footprints, you should end up in the board layout environment shown in figure. This is the design window for your board. Here you can see the component footprints as well as the silk screen and assembly details. Also visible is the board origin and the board drill symbol table.

STEP VI: Making a board outline

Next, we will add a board outline. Make sure that the online Design Rule Checkbox is off. If you do not see it, it is already off but if you see a dashed white box in the work space, the DRC box is on. To turn off the DRC box, click the button. To make a board outline click on the obstacle button. Move your cursor to the work area and right click with the mouse click the new option from the pop-up menu. The cross hair cursor will be smaller now, indicating that it is poised to do something. Right click on the work area again and select the properties option from the pop-up menu. The edit obstacle dialog box will pop up as shown in the figure. Make sure that board outline is selected in the obstacle type dropdown list and that global layer is selected in the obstacle layer dropdown list. Click ok. Create a board outline similar to the one shown in the figure. Place the cursor over the origin mark in the drill charts upper left corner. Click and release the left mouse button once. This begins the first vertex of the board outline. Next move the cursor to position 2. The border will stretch from the last place you clicked to the cursor. At position 2 left click and release again. Continue in the same manner to positions 3 and 4. After you have placed the final vertex at position 4, right click to bring up a menu box and click finish to complete the board outline. The board outline does not have to be rectangular, but for now it will help keep things simple.

STEP VII: Placing the parts

Make sure the component selection tool is selected and then left click once and release over a component. The component will be attached to the cursor so that you can move it to the desired location. As you move the part around you will be able to see the yellow netlist lines stretch and follow the pads. Click the left mouse button again to place the component inside the board outline. Once you have the parts where you want them you are ready to route the board.STEP VIII: Auto routing the board

To route the board automatically pull the auto menu down, as shown in the figure and select auto- autoroute -board. Layout will automatically choose the best paths and layers to route the entire board. Once the routing is finished an information dialog box pops up telling you so. Click ok.

STEP IX: Cleanup

To perform a cleanup go to auto-cleanup design as shown in the figure. Next check the items you want cleaned up using the cleanup design dialog box. Cleanup checks for routing problems such as off-grid or acute angles, bad pad exits, and overlapping vias.STEP X: Post processing the board design for manufacturing

At this stage layout has generated a design file that fully describes your board. This file is optimized for viewing, editing and saving on your computer but it is not in the format that many PCB manufacturers use for fabricating boards. The most common type of file system used in PCB manufacturing is the Gerber file system. Layout has the capability of translating its MAX file structure to a Gerber file system. This is called post processing the design. To start the postprocessor select auto -run post processor from the main menu bar as shown in the figure. Layout translates its MAX file into separate Gerber files for each layer that you enabled. Once post processing is completed a dialog box pops up telling you created Gerber design file. Click ok. Immediately another dialog box pops up telling you drill tape 1 written to throughole.tap. Click ok again. Finally, a text file automatically opens up in notepad. This is the postprocessor report which tells you what layers were generated and some information about them. At the bottom, look for the words no warnings or errors which means that the process was completed properly.