SCR-Stacking Structure With High Holding Voltage For I/O And Power Clamp ICECE 2015 Hyun young Kim,...
-
Upload
christian-heath -
Category
Documents
-
view
214 -
download
0
Transcript of SCR-Stacking Structure With High Holding Voltage For I/O And Power Clamp ICECE 2015 Hyun young Kim,...
SCR-Stacking Structure With High Hold-ing Voltage For I/O And Power Clamp
ICECE 2015
Hyun young Kim, Chung Kwang Lee, Han Hee Cho, Sang Woon ChoYong Seo Koo(Corresponding author)
Department of Electronics and Electrical EngineeringDankook UniversityGyeonggi-do, Republic of Korea
1. Introduction
2. SCR-based ESD Protection Circuit
3. Conclusions
Contents
1. Introduction
Discharge event due to tribo-electrically generated charges.
ESD is a high-current (~Amps) and short-duration (~ns) stress event.
ESD events are classified in three main categories. (HBM, MM, CDM)
ESD Protection Network turn on only when an ESD pulse is detected and turn off dur-ing normal operations.
I/O Clamp for ESD Protection circuits
Power Clamp for ESD Protection cir-cuits
[ESD Phenomenon and Basic Design of ESD Clamp]
SCR has been considered as an on-chip ESD protection circuit because of its high current capability and high failure current.
High trigger voltage (~20V) ▶Oxide breakdown Low holding voltage (1~2V) ▶Latch-up
As technology scale down, the value of trigger voltage(VT1) should be less than the oxide breakdown voltage.
In order to avoid the latch-up during normal operation condition, holding voltage should be greater than operating voltage(VDD)
< Cross section of the Conventional SCR circuits and equivalent circuits>
1. Introduction[Conventional SCR]
I/O Clamp
Power Clamp
2. SCR-based ESD Protection Circuit [Proposed ESD protection circuit]
< Cross section of the proposed ESD protection circuits and equivalent circuits>
< Simulation re-sults>
Proposed ESD protection circuit Conventional SCR
Trigger Voltage(Vt)[V]
20.5 26
Holding Voltage(Vh)[V]
3.3 1.5
The proposed ESD protection circuit has low trigger voltage and high holding voltage compared with conventional SCR ESD Protection circuit.
Low Trigger Voltage
High Holding Voltage
Additional BJT operation
I/O and power clamp
< Application circuit >
D1 Variation D2 Variation
2. SCR-based ESD Protection Circuit
D1 Variation[um]
5 7.5 10
Holding Voltage [V]
3.3 4.7 5.6
Trigger Voltage [V]
20.5 21.8 22.9
[Simulation Results]
D3 Variation Stack Variation
D2 Variation[um]
1 2 3
Holding Voltage [V]
3.3 4.8 7.9
Trigger Voltage [V]
20.5 21.8 23.8
D3 Variation[um]
1 3 5
Holding Voltage [V]
3.3 4.5 6.5
Trigger Voltage [V]
20.5 22.1 23.1
Stack Variation[number]
1 2 3
Holding Voltage [V]
3.3 6.8 10.5
Trigger Voltage [V]
20.5 41 58
< Result Table>
3. Conclusions
This paper proposed SCR-based ESD protection circuit with high holding voltage for I/O and Power Clamp.
In comparison to conventional SCR, these proposed circuit have low trigger voltage and high holding voltage.
The holding voltage for the single proposed SCR-based circuit has been increased from 3.3V to maximum 7.9V as a design parameters(D1,D2,D3) increases.
The holding voltage of each stack structure can be identified as 3.3V, 6.8V and 10.5V respectively.
The proposed SCR-based ESD protection circuit has latch-up immunity characteristics due to the high holding voltage and the high robustness is expected to improve reliabilty of integrated devices more.