School of Electrical and Electronic Engineering Queens University Belfast, N.Ireland Course Tutor Dr...

School of Electrical and Electronic EngineeringQueen’s University Belfast, N.Ireland

Course TutorDr R E Hurley

Semiconductor Device and Processing Technology

Northern Ireland Semiconductor Research Centre

School of Electrical & Electronic Engineering

The Queen’s University of Belfast


Semiconductor Device and Processing Technology

2. The future of siliconMoores LawWhat is realistic and possible for tomorrows production (advance to 22nm)?What next? New materialsBlue skies and on into the future. Sheets of carbon atoms

folded into a cylinderUnusual strength and electrical propertiesPromise to revolutionise electronics, computers, chemistry and materials science


International Technology Roadmap for Semiconductors

http://www.itrs.net/


Proposed new technologies

• Strained Si and SiGe

• Improve high-k/metal gate further

• Orientation (110 re 100)

• Multi-gates

• III-V or Ge

• Metallic S/D


Current question today is how to advance to 22nm?(in production)

IBM Research device


Current situation for immediate future

1. Lithography (immersion, EUV)

2. Mobility enhancement (strain eng)

3. High-k/metal gates improvements

4. Cu plugs contacts

5. Porous low-k interconnects.


Lithography

• 45 - 32 nm: Water immersion with ArF (NA = 1.35)

• 45 - 32 nm: Double patterning technique

• 22 - 13 nm: EUV expected (critical parameters: feature resolution, line-edge roughness (LER) and exposure sensitivity. )


Researchers used double patterning with water-based immersion lithography to achieve a proof-of-concept 32 nm flash memory pattern. The final k1 was 0.19 after the split.


Strain techniques

A buried SiGe island is very effective at inducing uniaxial tensile strain in the nFET channel for a 15% improvement in drive current. The TEM shows the device following silicon regrowth in the source/drain. (Source: IBM)

32 – 45 nm: strain engineering for CMOS. Put the silicon lattice under strain improves mobility in channel.1. Epitaxial SiGe in source and drain2. Compressive stressed nitride over gate3. Strained SOI


Ge layer on bulk Si Si layer on bulk Ge

Ge

Si

Ge on Si

Si on Ge

Si

Ge

Si expands laterally contracts vertically

Ge contracts laterally expands vertically


Strained Silicon

SiGe (X% Ge)

Silicon wafer

Epitaxial Silicon

Graded SiGe (0-X% Ge)

Strained silicon for high speed devices


relaxed Si1-x Gex

step

step

Si

Relaxed silicon germanium layer by graded growth on silicon

N.B. diagram exaggerated.

Lattice mismatch is only 4.2%!

With CVD, production of

layers is relatively easy. At QUB we

have experimented up to 60 layers.


Strained silicon for novel band gap engineered n- and p- MOSFETs with

significantly improved performance compared to pure silicon.

Strained silicon growth onto silicon germanium


Cross-sectional TEM image of a virtual substrate grown at 800 °C by ultra-high-vacuum CVD, showing the compositionally graded buffer Si1−xGex layer (x from

0 to 0.25) with significant number of dislocations and the constant-composition Si0.75Ge0.25 buffer free from

dislocations [Churchill et al., 1997].

TEM image of graded SiGe buffer layer


Strained silicon MOST

strained Si

n+poly-Si

SiO2 source

graded Si1-xGex

relaxed Si1-xGex

silicon substrate

drain 6-10nm

250-600nm

1.5m

n+ n+


Intel Approach to Strained Silicon

n+

p-silicon

n+ NiSi NiSi

NiSi

NiSi Si1-xGex Si1-xGex P+

n-silicon

P+ NiSi

Silicon in channel under compressive stress

P MOST 25-50%

Silicon in channel under tensile stress

n MOST 10%


Low-k for interconnects

At 22nm The interline capacitance between conductor lines (interconnects) must be reduced.

Use low-k (2.2 to 2.5)


Threshold voltage, Vt ,variability problem in MOSFETs

• As size reduces statistical variations in Vt start to show

• Random dopant fluctuations are major cause

For long transistors Vt = VFB + 2 ΦF - Qd/Cox

[ VFB == flat band voltage, ΦF is Fermi potential, Qd = depletion charge and Cox = MOS structure capacitance.]


The Vt fluctuations due to the random variations of dopant in the channel are given by

But this model does not work when dimensions are very small

i.e. ΔVt is a function of area and dielectric thickness



• Space-charge at source/drain junctions is around 0.05 µm for 0.18 and 0.12µm CMOS.

• When CMOS CD < 0.12µm , space-charge affects channel length significantly and potential barrier is reduced and Vt is reduced.

• This effect can vary from one transistor to the next.

Short channel effect

http://www.sciencedirect.com/science?_ob=ArticleURL&_udi=B6TY5-48170FN-8&_user=949370&_coverDate=07%2F31%2F2003&_alid=904895277&_rdoc=12&_fmt=high&_orig=search&_cdi=5609&_sort=d&_docanchor=&view=c&_ct=19&_acct=C000047720&_version=1&_urlVersion=0&_userid=949370&md5=f669b6dfc5830f8bd889e3e9ce503e4c#hit6









• High-k reduced ΔVt, but further improvements needed:

• Control work-function in the TiN gate1. nFET – Thin lanthanum oxide layer cap on

high-k2. pFET - Thin aluminium oxide layer on high-k



Copper interconnects into memory devices

Flash memory uses high fields needing thicker barrier layers and denser oxides

The interconnect of a flash device shows on-pitch Metal 1 with high-aspect-ratio vias above, which press the capabilities of barrier/seed coverage and copper fill. (Source: Micron)


Copper for contacts

• 32 nm: Copper to replace tungsten plugs(plugs make contact to S/D). Contact resistance affects RC and power consumption.

• Issues are barrier layers to protect silicon. (Cu poisons Si!). Barrier must be thin but reliable!


Beyond 22nm and high risk research

• Multi-gate devices (MuGFETs)

• Ge and III-V

• System on chip and 3D fusion technology.

Possible and realistic but difficult


MuGFET

Benefits from reproducible threshold voltage and low OFF leakage, but difficult to implement in production


Looking beyond 2010, for CMOS new materials required:

• For channel: SiGe, Ge or III-V

• In combination with high k dielectric and metal gates (to replace polysilicon) √

ITRS New material needs

School of Electronic Engineering and Computer ScienceQueen’s University Belfast, N.Ireland, UK

• Historically first bipolars and ICs were made from Ge

• Si replaced Ge because of SiO2 properties

• GeO is unstable at 4000C being volatile Bardeen, Brattain,

Shockley, 1947. Nobel Prize, 1956

Germanium, early days.


Importance of germanium in todays technology

Ge now reconsidered for:

1. Extending scaling limits of CMOS technology (<45nm)

2. Near IR optical telecommunication devices

3. Solar energy


Ge Si GaAsEnergy gap (ev) 0.67 1.1 1.4

Intrinsic carrier conc. ni (cm-3) 2.4 x 1013 1.45 x 1010 ~9 x 106

Electron mobility (cm2/Vsec)Hole mobility (cm2/Vsec)

39001900

1350480

8600250

Dielectric constant 16.3 11.7 12

Breakdown field (v/µ) ~8 ~30 ~35

Crystal Structure diamond diamond Zinc-blende

Lattice Constant (Ǻ) 5.66 5.43 5.65

Density, ρ (g/cm3) 5.32 2.33 5.32

Melting point (oC) 937 1415 1238

Thermal conductivity (W/cmoC) 0.6 1.5 0.81 ?

Thermal Coefficient of Expansion (oC-1) 5.8x10-6 2.5x10-6 5.9x10-6

Semiconductor Properties - Ge, Si, GaAs compared.


Germanium significant properties

• Electron mobility 3900 cm2/Vs (Si 1500)

• Hole mobility 1900 cm2/Vs (Si 450)

• Band gap 0.66 eV (Si 1.1 eV)


• Ge provides high electron and hole carrier mobility -- faster CMOS, larger drive currents.

• Compatibility with high k dielectric and low temperature metal gate technology

• Ge lattice match to GaAs permitting epitaxial growth -- n channel MOSFET

• Integration of rf & quantum electronics -- integration of opto-electronics (smaller optical band-gap)

Advantages of Germanium

3rd July 2008 Sheffield

Germanium

Highest hole mobility

High electron mobility

Low energy band gap

High density

More fragile than silicon

Scarce, expensive

Suitable for GaAs

epitaxy

Applications

High performance CMOS

Low temperature operation

IR detection/imaging

High energy particle

detection

Integrated optics &

electronics

Solar cells


Germanium problems with MOST

• Unstable oxide. GeO2 forms volatile GeO at 4000C, hence poor passivation of Ge surface

• Dopant solubility (in electrical terms) is poorer than expected. (Clustering? Vacancy-acceptor centres?)

• Dopant loss during annealing (related to ion-implantation damage)

• Some success with B, but n dopants ( implant damage greater) require higher anneal temps. Leads to high-k crystallisation, Ge diffusion etc..


Germanium: More problems!

• Smaller band-gap (than Si) leads to high intrinsic (ni),carrier concentration leading to surface leakage in p-n diode periphery. (problems also with surface states) [Satta, 2006}

• Lattice mismatch with silicon substrate means grading layers of SiGe or ‘smart-cut’ type solution if it can be made to work. Thermal expansion coefficients are significantly different.


Houssa et al., from Germanium-Based

Technologies, Elsevier Ltd. 2007.

GeMOSFET: p-n junction and metal gate/dielectric stack

Volume and surface charge carriers must be considered

GeMOSFET schematic


Thin epi-Si oxidised, with HfO2 by ALD give C-V improvement over GeON interlayer

Houssa et al., 2007

Ge gate-stack issues


GeMOSFET – circular geometry

Chi On Chui, Stanford University

Self-aligned, surface channel p-GeMOSFET ZrO2 (EOT 6-10 A), Pt gate.

BF2 35keV implant, 400C max temp in entire process.


TEM showing interface problems

• HfO and ZrO direct onto Ge leave a 3A GeO layer- enough to create instabilities and irreproducible characteristics

Ge/GEO2/HfO2 gate stack

(Houssa et al., 2007)

High density interface states, high leakage.


• Channelling is significant• End of range straggle • Annealing to remove damage and activation leads to loss of

dopant.

• Annealing temp must be kept below 400 to 500C to prevent:

1. Crystallisation of high-k material.

2. Out-diffusion of dopants.

3. Degradation of interfaces.

Shallow junctions: ion implantation problems


• Good p-channel devices OK

• n-channel mobility is poor

• Therefore, Ge for p-MOS

• GaAs or strained Si for n-MOS

• GaAs can be grown by epitaxy on Ge

Can GeOI really be used for CMOS?


Germanium on Insulator (GeOI)

Other possibilities for GeO

• Enhanced performance devices

• High speed photodetectors

• Template for GaAs epitaxy (→Si/III-V integration)


Smart-Cut method for GOI (QUB)


Bond and polish back to Ge layer 1±0.5µm

Silicon handle

oxide Ge

Silicon handle

oxide

Silicon (100)

Ge 92% Ge

92% Ge


3D integration → fusion technology

SEM of a 3-D via chain with 10,000 vias/mm2

density after etching the silicon in the top die.

(Source: IMEC)

FUSION = integration of memory, logic, sensor, processor and software using 3D stacked ICs


Optoelectronics: Photons weigh 250,000 times less than electrons, so why not use them to carry data? Bringing optical technology down to the processor level, DNA: ??Immersion lithography: This technique entails putting wafer in water and shooting the picture! Imprint lithography: A stamp (by e-beam litho) is immersed in liquid to create a pattern. HP. EUV lithography: By using highly polished mirrors and a laser EUV machines can create lines a few nanometers in length. Intel, AMD and IBM are the big proponents. 2009? (Think not! “SemiconInt”)


Spintronics: Uses the magnetic field created by an electron's spin (rather than the transport of electrons). Phase change: memory technology that relies on heating, and reheating, CD-like material. Philips and Intel, Nanowires and nanotubes: transport electrons from one point to another to create a 1 or 0. how to put billions into arrays.? Crossbar latches: This is one of the more radical transistor makeovers, HP. bad circuits no statistical consequenceResistance switching: Resistance change of molecule. III-V compounds: These materials behave like silicon but are faster. They also cost a lot more.

School of Electrical and Electronic Engineering Queens University Belfast, N.Ireland Course Tutor Dr...

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