SB-MOS DEVICE MODELING WITH APPLICATIONS TO NEUROMORPHICCOMPUTING

MIKE SCHWARZ, LAURIE CALVET, JOHN SNYDER, TILLMANN KRAUSS, UDO SCHWALKE, ALEXANDER KLOES

Scope

SOI and Multi-Gate MOSFETs.

High-res. TEM of a 22-nm SB-PMOS*.

*J. M. Larson, J. P. Snyder, ”Overview and status of metal S/D Schottky-barrier MOSFET technology”, IEEE Transaction Electron Devices 53 (5), 1048–1058, 2006.

Performance prediction with TCAD requires accurate

simulation/modeling of the device and its topology

Benefits at cryogenic temperatures, e.g. superior

carrier mobility due to less doping, lower temps

and reduced surface roughness scattering

01/28

Outline

• Physical Basics

• Part I: Simulation Methodologies

• Part II: Analysis Device Physics for Cryogenics

• Part III: SBs for Neuromorphic Computing

02/28

Physical Basics – Operation Principles of SB-MOSFETs

Operation principle of p-channel SB-MOSFETs.

03/28

Part I: Simulation Methodologies – Structure, Process & Device Simulation

Ideal structure simulation

of simplified geometries

Non ideal structure

by process description

Device simulations

04/28

Part I: Modeling & Simulation Hints - SB Simulation Models in TCAD

• Schottky barrier lowering model for thermionic

emission

• The dashed lines indicate the barrier height

with and without lowering

• The red line indicates the approximation used

by Sentaurus

• Schottky barrier lowering model for field

emission

• The solid black line is the barrier height without

lowering

• red line is the barrier lowering used in the

Sentaurus FE model

05/28

Part I: Modeling & Simulation Hints – Banddiagrams w and w/o SB Lowering

Band-diagram and quasi Fermi level of a Si SB-MOSFETs w and w/o SBL.

Correct SBL has to be accounted for and calculated manually. 06/28

Since 2019 TCAD version, SBL visualization

possible! Success of our work!!!

Part I: Modeling & Simulation Hints – Meshing of Non-Planar Devices

Test structure to account meshing difference and impact on electric field.07/28

Part I: Results – Device Simulation Models

Exemplary 2D slice for 3D device geometry of a

25nm PtSi SB-MOSFET for further analysis.

Within the TCAD simulation the following

models were activated:

• Fermi distribution

• doping dependency, high field saturation effect

on mobility

• mobility degradation at interface

• bandgap narrowing

• effect on effective intrinsic density (old Slotboom

model)

• lattice temperature

• nonlocal tunneling at metal-semiconductor

interfaces including Schottky barrier lowering

08/28

Part I: Results – TCAD compared to measurements: w/o retrograde implant

Id - Vg with Bp,PtSi = 0.22eV*.

*L. E. Calvet, ”Electrical Transport in Schottky Barrier MOSFETs”, PhD Thesis, Yale University, USA, 2001. 09/28

Part I: Take aways

• A methodology to account for more precise and realistic SB-MOSFETs simulation was presented

• It was shown that the capability of process simulation match experimental data

• This can lead to an improvement in the estimation of the off and on-current regions

• The quality of process information and selection of the correct calibration have an impact on the

simulation quality

• This significantly enhances the possibilities for further optimization of these devices

10/28

Part II: Analysis Device Physics for Cryogenics - Device Definition

Simplified geometry of a SB-DG-MOSFET.

Within the TCAD simulation the following

models were activated:

• Fermi distribution

• incomplete ionization, doping dependency, high

field saturation effect on mobility

• mobility degradation at interface

• bandgap narrowing

• effect on effective intrinsic density (old Slotboom

model)

• lattice temperature

• nonlocal tunneling at metal-semiconductor

interfaces including Schottky barrier lowering

• thermionic emission

11/28

Part II: Analysis Device Physics for Cryogenics - Temperature Impact on Carrier Densities

Impact of the temperature on the carrier densities n(E) and p(E).

The density-of-states, Fermi level and Fermi distribution function can affect

the effective mass of SB-MOS and improve transport by enhancing the

tunneling transport (transport bottleneck versus tunneling enhancement).12/28

Part II: Analysis Device Physics for Cryogenics - Banddiagrams w/woSchottky Barrier Lowering

Si SB-DG-MOSFET with Bn = 0.3eV w/wo SBL at the silicon/oxide interface

lch = 22nm, tch = 10nm, tox,SiO2 = 2nm.

13/28

Part II: Analysis Device Physics for Cryogenics - Simulation vs. Measurement

Si SB-DG-MOSFET with Bn = 0.3eV w/wo SBL at the silicon/oxide interface

lch = 22nm, tch = 10nm, tox,SiO2 = 2nm.

*L. Hutin et al., ”Dual Metallic Source and Drain Integration on Planar Single and Double Gate SOI CMOS down to 20nm: Performance and Scalability Assessment”, IEDM, 1–4,

December, 2009. 14/28

Part II: Analysis Device Physics for Cryogenics - Temperature Impact

Si SB-DG-MOSFET: IFETE - Vg and gm - Vg with Bn = 0.3eV

lch = 22nm, tch = 10nm, tox,SiO2 = 2nm.

15/28

Part II: Analysis Device Physics for Cryogenics - Impact Vds with/without SBL

Influence of Vds on ITE - Vg w/wo SBL with Bn = 0.3eV

lch = 100nm, tch = 20nm, tox,SiO2 = 2nm.

16/28

Part II: Analysis - Impact Vds with/without SBL

Influence of Vds on ITE - Vg, IFE - Vg w/wo SBL with Bn = 0.3eV

lch = 100nm, tch = 20nm, tox,SiO2 = 2nm.

16/28

Part II: Analysis - SB-DG-MOSFET vs. conventional DG-MOSFET

SB-DG-MOSFET w SBL vs. conv. DG-MOSFET: Id - Vg of IFETE with Bn = 0.3eV vs. IDD with S/D doping ND =

1e20cm-3, lch = 22nm, tch = 10nm, tox,SiO2 = 2nm. lsource = 5nm and l = 5nm.

Improvement at RT by SBL and due to voltage drop at the SB.

Smaller field in the channel and a reduced velocity saturation.

At LT current improve due to the mobility enhancement from reduced phonon scattering. 17/28

Part II: Take aways

• Smaller m* reduced drive current due to density-of-states effects

• SBL effect influences the dominating conduction mechanism total amount of current especially

in the low temperature regime

• SBL can significantly improve SB-MOSFET performance particular at low temperatures

• Currents for the SB and conventional MOSFETs were found to be comparable

• At RT higher currents for the ideal SB-MOSFET large voltage drop at the SB increased

mobility

• Potential candidate as device/circuit to bridge RT circuits and quantum electronics (qubits)

18/28

Part III: SBs for Neuromorphic Computing - Human brain vs. Computer

19/28

Numbers Von Neumann computer Human brain

# elements 107–108 transistors 1010 – 1012 neurons

# connections / element 10 104 – 103

switching frequency 109 Hz 103 Hz

energy / operation 10-6 Joule 10-16 Joule

power consumption 100 – 500 Watt 22 Watt

reliability of elements reasonable low

reliability of systems reasonable high

Part III: SBs for Neuromorphic Computing - Types of Synaptic Devices

20/28

Filamentary

devices*

Ferroelectric

synapses**

Atomic switches

***

Phase change

synapses

****

Spin torque

synapses

*****

Floating gate

transistors

******

Signals travel electro-chemically

Neurons communicate, synapses transfer and store

Ion channels are the

current source

~5nm

*Barbara et al ACS Nano 2015, **Chanthbouala et al Nat Mat 2012, ***Ohno et al Nat Mat 2011, ****Tuma et al Nat Nano 2016, *****Vincent et al IEEE Trans Biomed

Cir Sys 2015, ******Mead et al IEEE Trans 1996

Part III: SBs for Neuromorphic Computing - Floating Gate Device Physics

21/28

SLC floating gate transistor*.

*https://www.androidcentral.com/smartphone-futurology-3-chips

Physical principle:

• Tunneling or Hot Electron Injection of charge carriers towards the floating gate by the control gate

Within TCAD simulation modeling as follows:

• Lucky electron, Poole Frenkel

• Transient with trap statement unfill, fill

Part III: SBs for Neuromorphic Computing - Floating Gate vs. SONOS Device Physics

22/28

*Overview of Emerging Non-volatile Memory Technologies September 2014 Nanoscale Research Letters 9(526):1-33

**https://floadia.com/technology/

Physical principle SONOS:

• Tunneling of charge carriers towards the trapping nitride (discrete) by the control gate

Part III: SBs for Neuromorphic Computing - SONOS vs. SB-SONOS Device Definition

23/28

toxb = 1.8nmtoxt = 4nm

125nm

Lg = 130nm

tsn = 8nm tgate = 5nm

0.6µm

tsp = 7nm

toxb = 1.8nmtoxt = 4nm

tsil = 20nmLg = 130nm

tsn = 8nm tgate = 5nm

0.6µm

tsp = 7nm

Part III: SBs for Neuromorphic Computing - Pulse Device Definition / Biasing

24/28

Vd1

Vd2

Vd3

Vd4

Output Neurons

Input

Bias

Vs Vs Vs

Biasing:

• Vg and Vs are tied together and the

MOSFET works as a Memristor

Pulsing:

*(inspired by Ziegler et al APL 101 263504 2012)

synapse

Pulsing:

Part III: SONOS Simulation Results CTG0_HID0

25/28

Part III: SB - SONOS Simulation Results CTG0_HID0

26/28

wo SBL

Part III: SB - SONOS Simulation Results CTG2_HID3

27/28

wo SBL

Part III: Take aways

• Simulation of SONOS devices possible, SONOS allows superior number of read/write cycles than

conventional floating gate MOSFETs

• Enhancement of SB-SONOS to benefit from possible SB performance boost (wSBL, still pending)

(low-voltage, excellent cycling, endurance and data retention*)

• Possibilitiy to simulate device physics and parameter studies for device improvements, engineering

of structure to optimize the timing

28/28*C.-H. Shih et al., ”Schottky Barrier Silicon Nanowire SONOS MemoryWith Ultralow Programming and Erasing Voltages”, EDL, vol. 32, no. 11, 2011.