Sanjeev Chauhan

Email IDchauhansanjeev1987@gmail.com

Contact NoMobile: +91 8867001088

Personal DataFather’s Name : Surender Singh

Date of Birth : 18-Oct-1987

Gender : Male

Nationality : Indian

Marital Status : Single

Passport # : L6230567

Facebook :

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LinkedIn :

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Contact AddressA 209, Fern Saroj ApptLBS NAGARBangalore 560017

Experience Summary

Having 4 years and 10 months of experience in Semiconductor Industry Presently working with Einfochips as Senior Verification Engg (VLSI domain) Experience and knowledge in various aspects of Verification and debug, integration, Test

Bench development, Test plan Development, Documentation including Bug Documentation and Tracking.

An effective communicator with excellent relationship building & interpersonal skills.Educational Qualification

2005 – 2009 BTech - 62% From United College Of Engineering & Research, Greater Noida UP Technical University, Lucknow2005 HSC (74 %) Assisi Convent School, Noida (CBSE Board)2003 SSLC (82%) Assisi Convent School, Noida (CBSE Board)

Primary Skill Sets: System Verilog, Verilog, C, NCSIM, ARMCC, KEIL, DVE , VERDI

Key Points

Working as Sr. Verification Engineer with Einfochips from July’13 - present Worked on power estimation by running GLS regressions. Worked on pre/post-silicon performance validation of GPU. Worked on ARM Cortex-M0 based SoC design and architecture Proficient in RTL Compilation, Elaboration and Simulation using NCSIM. Worked on standard bus protocols such as AHB and APB and network protocols such

as I2C. SoC verification in System Verilog using UVM methodology UVM based Verification plan development Testplan, Test-bench development and Test-case coding using System Verilog, UVM and

C. Pre-silicon validation of FPGA through SIMULATION Eminent communication skills with the ability to successfully build strong working

relationships with clients and colleagues.

Technical Expertise

Primary Domain Functional Verification(ASIC/SoC) using HVLs(SV), UVM

Operating System Unix, Windows

Languages System Verilog[OOPS concepts], C

Tools/Utilities NCSIM, ARMCC, KEIL, DVE , Verdi

Protocols AHB,APB, I2C

Microprocessor Cortex M0, M4

Employment Recital Einfochips, Bangalore

July’13 To Present Sr. Verification Engineer

Power Calculation and Performance validation of 3d GPURole and Contribution: Performance Validation Engineer

Running Netlist simulations and calculating the power consumption.Building GLS model by integrating Netlist with RTL models.Performance validation for GPU architectures by running benchmark tests and comparing the results/performance

with the previous generation architectures.Automating the work flow by developing shell/perl scripts.

WIPRO TECHNOLOGIES, KOCHI May’11 to July’13

Verification Engineer

SoC level verification of CORTEX M0 based Microcontroller using UVM methodologyRole and Contribution: Verification Engineer

Responsibilities include setting up the C-based environment which included the BOOTCODE, library functions, MAKEFILE and UVM based testbench to compile and link the c-code and generate the HEX-Code

TESTPLAN creation for I2C verification.Owned I2C verification at the SoC level, build UVM based testbench for I2C for System Verilog/C co-verification

using porthole mechanism.Helped in automating the RTL compilation/simulation flow through MAKEFILE.

FPGA RTL Verification of 32-bit Micro ControllerRole and Contribution: Verification Engineer

Main responsibilities were FPGA verification through simulation which included clock and reset checks, GPIO tog-gling and program execution from NVM.

Worked on the Test plan development.Was also responsible for verification of firmware routines for NVM access (READ/WRITE/ERASE).

Module level Verification of 32-bit Micro ControllerRole and Contribution: Verification Engineer

Worked on porting of testcases from the parent chip to derivative chipWas responsible for running regression for GPIO module.

Centum Electronics Pvt. Ltd., Bangalore April’10 – May’11

Testing Engineer

Role and Contribution: Testing Engineer

Responsible for card and box-build level testing of PCBA.Diagnosing problem in process and achieving solution through root cause analysis.Participated in “LEAN Manufacturing” training-sessions for ‘Value Stream Mapping’ and helped in increasing the

productivity of the organization through implementation of KAIZENs.

DeclarationI hereby declare that all the information furnished above is true to the best of my knowledge.

SANJEEV CHAUHAN