Samsung Plasma Training Manual

5/21/2018 Samsung Plasma Training Manual

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PDP Training

(Alexander)


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1.Explanation of Layout and

Function of Circuit Board

2.Operation Explanation per Board

2-1 Drive Description on SMPS2-2 Operation Explanation of Driving Circuit

2-3 Logic-Main Board

2-4 Scaler Board

Agenda


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1. Explanation of Layout & Function of Circuit Board

COF x 7

Y-MAIN

SMPS

X-MAIN

Logic-Main

Y buffer Upper

Y buffer

Lower

E-buffer F-buffer G-buffer

[PDP Module Picture]


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[ Function Description by board - 1 ]

.SMPS(Switching Mode Power Supply)

: It is the supplier to provide voltage and current to work the drive voltage and panel in each board.

.X-MAIN BOARD

: It makes the drive wave form by switching FETs to Timing Controlle coming from logic-board and

supplies X electrode of panel with the drive wave form via connector.

.Y-MAIN BOARD

: It makes the drive wave form by switching FETs to Timing Controller coming from the logic-board and

provides Y electrode of panel with the drive wave form via Scan Driver IC on Y buffer board in order.

.LOGIC MAIN BOARD

: It process image signal and performs buffering of the logic-main board (to create XY drive signal and

output) and the address driver output signal.

Then it supplies the output signal to the address driver IC(COF Module).


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[ Function Description by board - 2 ]

.LOGIC BUFFER(E,F,G) : It delivers the data signal and control signal to the COF.

.Y-BUFFER (Upper,Lower)

: It is the board to impress the scan waveform on the Y board and consist of 2 boards

(upper board and lower board).

8 Y-buffers are fixed at the scan driver (STV7617 of STC corp. : 64 or 65 Output).

.AC Noise Filter

: It has functions to remove noise(low frequency) coming from AC LINE and prevent surge.

It gives serious effects on the safety regulations (EMC, EMI) according to AC filter.

.COF(Chip on Flexible)

: It impress the Va pulse to the address electrode in the address section and forms the address

discharge by electric potential difference with scanning pulse to be dismissed by the Y electrode.

It is made in the form of COF and one COF consists of 4 Data Drive IC (STV7610A :96 Output),

otherwise single scan is made of 7 COF.


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CELL STRUCTURE OF PDP

Bus electrode

Dielectric

ITO electrodeMgO layerBarrier Phosphors

AddressElectrode

Front panel

Back panel


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Electro Arrangement of SD PDP

Y1

Y2

Y480

X

X

X

A1 A2 A3 A4 A5 A 6 A7

Reference

- A1,A2, , , : Address Electrode

- Y1,Y2, , , : Scan & Sustain Electrode

- X : Com mon & Sustain Electrode


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ADDRESS OPERATION

In order to display picture,

select the cells.


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SUSTAIN OPERATION

Display cells through strong

Sustain discharge.


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1 SUB-FIELD IMAGE PROCESS (ADS)

Reset Address Sustain

Function

Sustain Erase

Wall Charge Set

Issue

Operation margin

Contrast

Short Time

Function

Select On Cell

Issue

High Speed

Low VoltageLow Failure

Function

Discharge On Cell

Issue

High Efficiency

Low VoltageERC Performance


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FRAME STRUCTURE (ADS)

SF1 SF2 SF3 SF4 SF5 SF6 SF7 SF8

1

.....2

480

128T64T32T16T8T4T2T1T

1TV field (time)

scan

line

address

sustain

sub-field

Reset

Period

Address

Period

Sustain

Period

X

Y1

Y2

Yn

D


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1 Picture Structure by 8 sub-field

SF1 SF2 SF3 SF4 SF5 SF6 SF7 SF8

1

.....2

480

128T64T32T16T8T4T2T1T

1TV field (time)

scan

line

address

sustain

sub-field


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2. Explanation of Operation per Boards

PDP Panel

852 X 480 Pixels

853 X 3 X 480 Cells

Logic B'd Display

Data

Driver

Timing

Scan

Timing

Input

Data

Processor

Clock :

27MHz

Data

Controller

Clock :

60MHz

DRAM

Driver

Timing

Controller

Clock :

20MHz

40MHz

Y-Main B'd

Row

Driver

Y-Pulse

Generator

X-Main B'd

X-Pulse

Generator

Column Driver

Power B'd

Power Supply

Digital B'd Analog B'dLVDS

AC Power

Source

220V

Image

Enhancer

Image

Scalerr

AD

Converterr

TMDS

Receiverr

Video

Decoder

De-

interlacer

Micom

Tuner

AudioProcessor

VideoS/W

CombFilter

[Whole Block Diagram]


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1 Picture Structure by 8 sub-field

CN805

(10P)

CN805

(10P)

CN806)

CN812

(5P)

CN804

(9P)

CN804

(9P)

CN802

(11P)

CN801

(10P)

CN803

(10P)

CN803(10P)

CN806)

LA03

(31P)

CN201CN201 CN101CN101

CN801CN802CN601CN111 CN101

CN102

CN103

CN401 CN402 CN403

EF1 FE1 FG1 GF1

AC

Inlet

Analog

igital

Y-Main X-Main

SMPS

Logic

[Wiring Diagram Schematic]


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PIN CONFIGURATION

CN101(Control)

NO PIN Name

1 GND

2 SCL1

3 SDA1

4 GND

5 SAFT6 GND

7 MUTE

8 GND

9 MAFT

10 GND

11 ANAL_CVBS

12 GND

CN102(Video/Sync)NO PIN Name

1 ANAL_YCOMB

2 GND

3 ANAL_CCOMB

4 GND

5 ANAL_Y26 GND

7 ANAL_PB2

8 GND

9 ANAL_PR2

10 GND

11 ANAL_H12 ANAL_V

CN103(Video/Sync)

NO PIN Name

1 ANAL_YCOMB

2 GND

3 ANAL_CCOMB

4 GND

5 ANAL_Y2

6 GND

7 ANAL_PB2

8 GND

9 ANAL_PR2

10 GND

11 ANAL_H

12 ANAL_V

NO PIN Name NO PIN Name

1 GND 16 Tx CLK Out+ / Rx CLK In+

2 GND 17 GND

3 Tx Out0- / Rx In0- 18 GND

4 Tx Out0+ / Rx In0+ 19 Tx Out0- / Rx In0-

5 GND 20 Tx Out0- / Rx In0-

6 GND 21 GND


8 Tx Out1+ / Rx In1+ 23 GND

9 GND 24 GND

10 GND 25 RESET_MN


12 Tx Out2+ / Rx In2+ 27 IIC SCL2

13 GND 28 GND

14 GND 29 IIC SDA2

15 Tx CLK Out- / Rx CLK In- 30 GND

31 GND

[ Scaler : Analog

Dgital ]

[ Scaler Dgital Logic CN601 ]


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PIN CONFIGURATION

CN802(Digital Tu)

NO Power

1 THEM_D

2 STD_5V

3 GND

4 PS_ON

5 N.C.

6 GND

7 GND

8 D3.3V

9 D3.3V

10 GND

11 D6V

CN801(Analog Tu)

NO Power

1 GND

2 A33V

3 GND

4 GND

5 AMP12V

6 AMP12V

7 GND

8 D12V

9 GND

10 D6V

CN803(Logic)

NO Power

1 D3.3V

2 D3.3V

3 GND

4 GND

5 D5V

6 GND

7 IC2

8 IC2

9 PS_ON

10 GND

CN804(X-Main)

NO Power

1 D5V

2 VG

3 GND

4 GND

5 VE

6 GND

7 GND

8 VS

9 VS

CN805(Y-Main)

NO Power

1 D5V

2 VG

3 GND

4 Vscan

5 GND

6 Vset

7 GND

8 GND

9 VS

10 VS

CN806/812(Buffer)

NO Power

1 Va

2 Va

3 N.C.

4 GND

5 GND

[ SMPS

Analog / D igital / Log ic ]

[ SMPS

X,Y-Main / Buffe r ]

CN807/811(FAN)

NO Power

1 12V

2 GND

5 Fan_D

[FAN B+:For VMB]


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2-1. Drive Description on SMPS


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Operation Description on SMPS

1. Overview

SMPS used in PDP 42" developed into the compact-sized with high efficiency.

The asymmetrical half bridge and the flyback converter are applied into all output. To comply with the

harmonic restrictions, it takes the power factor improvementcircuit, which converts AC into the high DC

and uses as the input of another converter controller.

2. Input controller

SMPS works in whole section of AC 90~264V. It is possible to start in the AC 90 and can restart with new

input voltage, even in interruption of electric power. STD_5V comes out when AC is impressed

3. Output Controller

Given SMPS have 15 output voltages. The following shows the specification of output voltage and output

current in case of their successive drive.


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Name Volt ag e Cu rren t(Max.) Usin g in P DP D riv ing

VS +75V ~ 100V 4.5A Sustain Voltage

VA +65V ~ 80V 0.6A Address Voltage

VSCA N +65V ~ 100V 0.1A

VSET +80V ~ 100V 0.1A

VE +100V ~ 120V 0.1A

VG +15V 1.5A Driving Voltage of Fet

D12V +12V 0.1A

Name Voltag e Cu rren t(Max.) Usin g in P DP Dr iv ing

A12V +12V 0.3A

D6V +6V 0.1A

A6V +6V 0.1A

D5V +5V 1.0A IC Driving Voltage of Logic

D3.3V +3.3V 4.5A

12VAMP +12V 1.7A Amp Voltage of Audio

VT +33V 0.003A

STD_5V +5V 0.6A Standby for Remote

Control

3-1. Overvoltage protection

It has circuit to maintain normal voltage, additionally with circuit for sensing overvoltage, so it means any

overvoltage does not give impacts on other output controller.SMPS prevents overvoltage in the latch mode.

VS(85V) works protection function more than 100V, over 94V for VA(75V), over 8.2V for D6V,

over 4.7V for D3.3V


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3-2. Short circuit and overvoltage protection

It forms definition that in the short circuit of output controller the output impedance is lower than 300mohm.

If the VS output have a short circuit in case of given SMPS, SMPS stops its working.

Even in the case of short circuit between main output and STD_5V, SMPS does not break down.

When the short circuit is removed, it restarts.

4. Detail Description

AC-DC Converter

It converts AC into DC by using the power factor improvementcircuit. This converter was designated to

control the high frequency noise, with the function to improve the power factor. This part becomes input

controller of another constant-voltage.

[ PFC Drive FET(SPW47N60) Drain Pulse ] [ PFC Drive FET(SPW47N60) Gate Pulse ]


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Auxiliary Power

It is the part to supply power of mycom for remote control. When the power is on, it will work,

which means that MICOM is on standby.

This output part is stand_by voltage. When the power-on signal from remote control impress,

it works main power panel of SMPS via stand_by voltage.

Configuration of VS output

Major part of PDF SMPS outputs 85V 5A. It takes asymmetrical half bridge converter and connects

2 converters with 85V output in parallel, which increases efficiency than one 85V converter,

on the other hand, decreases its size.

[ Driving FET 2SK2372) Drain Pulse Current wave. ] [ Driving FET 2SK2372 Gate Pulse ]


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- PWM Part

It uses PWM part of ML4824, but there are some points to take cautions. As this part is synchronized with

the PFC part, PWM wave in the current mode drive is induced via the current sensor resistance or current

transformer, and shows the current flowing in the output controller.

DC-DC Converter : Input of VSCAN, VSET and VE belongs to the VS part

[ VSET Pulse ]

[ VE Pulse ]

[ Vscan Pulse ]


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Output (VA,Multi Outputs) Pulse

[ Va Main Pulse ]

[ Multi Outputs Main Pulse ]


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Trouble shooting on SMPS

STB_5V

Power O N

Check cord connec ti on

PFC

PFC

PFC

NG

Check the IC2,D28

Check the IC1,Q1,Q2

OK

OK

OK

OK

NG

NG

Check the IC35

Check the IC7


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Trouble shooting on SMPS

VS

Vscan

VE Vset

NG

Check the Q6,Q8

Check the IC16, IC17, IC18

OK

OK

Check the Other board Image Board or Driver Board or Cable.


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2-2. Operation Explanation of Driving Circuit1. Overview of Driver Circuit

1) Definition of Driver Circuit

The driver circuit division drives the panel with the proper wave form (high voltage pulse) to develop image on

the outside terminal division (X electrode group, Y electrode group, Address electrode).

High voltage switching pulse is made by MOSFET combination.

2) Working Principle of Driver Circuit

To develop image on the PDP, the voltage should be impressed into the X, Y and ADDRESS electrodes

(which are component of each pictorial element) under the proper conditions. The driver wave form which is

currently applied to is ADS (Address & Display Separate: Driving method to work by dividing address and

constant-current section ) Based on this method, the discharge to be done in the pictorial element of PDP

can be divided into 3 types as follows.

Address Discharge: to form the wall voltage within pictorial element by providing lighting pictorial

element with information(impressing data voltage)

: It is the discharge produced by difference between the positive electric potential of address electrode

(normally, Va impressed voltage of 70~75V +Positive Wall charge) and

negative electric potential of Y electrode

(GND level impression+ Negative Wall charge).


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Operation Description on Driving Board

Constant-current Discharge: It is the display section to form discharge voluntarily with the help of

wall voltage formed by address discharge. (It makes optical power to create image)

: It is the Self Sustaining Discharge made by combining the electric potential of coherent pulse, normally

160-170Volt, which alternates the X electrode with Y electrode in the sustain section, with the wall voltage

according to the pictorial element condition changed by if the former discharge exists or not. That is to say,

it works according to Memory characteristic (it means that former working condition defines the

current condition) as the basic feature of AC PDP.

If the wall voltage formerly exists in the pictorial element(i.e., the pictorial element is on), the discharge makes

forms again because the voltage higher than one of the discharging starting time is impressed by combination

of the wall voltage and of the next impressed constant-current.

While if the wall voltage does not exist in the pictorial element (i.e., the pictorial element is off), the discharge

does not form because the voltage could not reach to the level of the discharging starting time, only with

constant-current.



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Erasing discharge: To selectively perform the address discharge for respective pixel, pixels of all

panels must be on same conditions (same wall charge state and space charge state).

Therefore the erasing discharge zone is important factor to obtain driving margins.

There are various methods such as application of log waveform but the wall voltage control method

by the Ramp Waveform is now widely applied.

: The purpose of intialization (Erasing) discharge is to make wall voltage within the the whole of Pixels.

In other words, the erasing discharge must make difference between wall voltages uniform depending on

whether or not the sustain discharge exists in the previous state. Namely it must remove the wall voltage

formed by the sustain discharge and supply ions or elements by causing discharge for removing the wall

voltage. In the other words, To remove the wall voltage, limit the time when polarity of the wall voltage is

reversely charged by causing discharge or prevent polarity form being reversely charged by supplying

appropriate quantity of ions or elements through forming weak discharge [low voltage of erasing].

There are two types of the weak discharge [low voltage]as known so far. 1) Log Waveform adopted by

the F-company 2) Weak erasing discharge by the Ramp Waveform largely adopted by Matsushita

company, etc. Outside applied voltage is adjusted depending on difference of wall voltage within Pixel,

since discharge is formed when the sumof the existing wall voltage remained and the voltage on a

rising waveform exceed the driving beginning voltage, by slowly applying the

rising slope of the erased waveform for these two methods. In addition,

weak discharge is formed since the strength of applied voltage is small.


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3) Essential factors for driving board operation

- Supplied from power board and the optimum value may somewhat differ fromthe below cases.

Vs : 85V - Sustain

Vset : 60V ~ 70V - Y Rising Ramp

Ve : 110V - Ve bias

Vscan : 70V ~ 80V - Scan bias

Vdd : 3.3V - Logic signal buffer IC

Vcc : 15V - FET Gate drive IC

Logic Signal

: Supplied from logic board

: Gate signal of each FET


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Driving Waveform Specification Arrangement

Y rising

Ramp

Y falling

Ramp

Y scan

Pulse

Y sustain

Pulse

X sustain

Pulse

Address

Pulse

A1,2..... Address =Data) Electrode

X Common Sustain Electrode

Y1,2.... Scan Sustain Electrode

Vs 85V Ve 110V

Vset 95V Va 79V

Vscan 85V


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Explanation of Function per Pulse

Y Rising Ramp Pulse

Outside voltage of about 390V~400V is applied to the Y electrode in the Y Rising Ramp zone, and weak

discharge begins if respective gap voltage equals to the discharge beginning voltage.

Negative Wall charges accumulate on the Y electrode and the Positive Wall charges on the X electrode in

the whole while weak discharge is maintained.

Y Falling Ramp Pulse

Most of Negative Wall charges accumulated on the Y electrode by the X bias of about 200V are used to

remove Positive Wall charges in the Y Falling Ramp zone, and most of Positive charges accumulated on

the (0V) Rising Ramp zone toward the address electrode are maintained, having distribution of wall

charges beneficial for the subsequent address discharge.

E l ti f F ti P l


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Explanation of Function per Pulse

Y Scan Pulse

Y scan pulse is called as injection pulse, and selects the Y electrode one by one (Line-at-a-time).

In this case, Vscan is called as Scan bias. For the electrode line with the Vscan voltage applied,

voltage of about 70 Volt (Vscan) is applied, and voltage of 0 Volt(GN0) is applied.

However, since Negative Wall charges accumulate on the Y electrode by the application of Ramp pulse

and Positive Wall charges accumulate on the address electrode, voltage of more than the discharge

beginning voltage is applied to the cell where address pulse(70V~75V) is allotted and thus address

discharge occurs. Address time of the PDP is very long since both scan pulse and data pulse must be

applied in line at a time.

1st Sustain Pulse

The Sustain Pulse always begins from the Y electrode, it is because Positive Wall charges are formed on

the Y electrode if address discharge occurs. The wall charges formed by the address discharge are less

than those for the sustain discharge, and thus the strength of the initial discharge is weak.

Sustain discharge usually become stable after 5~6 times of discharge depending on structure of electrode

and environment. Therefore, the initial long sustain pulse is intended to form the initial

discharge stable and form the wall charges much as possible as.

T bl h ti D i i B d


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1. Y buffer- To check whether there is failure of the Y Main, firstly check normal operation of the Y buffer.

- After separating both the Y Main and the Y buffer connector,

- Check forward voltage drop of 0.4V ~ 0.5V by diode check between OUTL and OUTH.

- In addition, resistance between both ends is also more than several k.

Trouble shooting on Driving Board

OUTL

OUTH

OUTH

OUTL

OUTL OUTH

T bl h ti D i i B d


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Trouble shooting on Driving Board2. Y Main

- After connecting both the Y Main and the Y buffer, check that output of one of OUT1~8 of the Y buffer

is done as follows in application of power

OUT1

OUT2

OUT4

OUT3

OUT6

OUT5

You must check 1EA of Scan pulse is output

T bl h ti D i i B d


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Trouble shooting on Driving Board3. X Main

- Check output of the TPOUT on the X board is done as follows in application of power

TPOUT


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2-3. Operation Explanation of Logic Board

LVDS

EP20K400EBC652-1

FPGA

FRONT_XY MEMORY

CONTROLLER

SPS10-MEM

ASIC

64M

SDRAM

64M

SDRAM

EPC2 EPC2 EPC2 RESET

Circuit

28BV256K

Image Signal Logic Power

3.3V,5VVs StartSignal

Image Signal

8 bit per DATA R.G.B

1 bit per H,V SYNC

IIC SCL,SDA)

IIC

SCL,SDA)

Y CONTROL

X CONTROL

8 bit per DATA R.G.B

1 bit per H,V SYNC

1 bit per DATA_EN,TSC,POL,SEN,SDA,SCLK

_nRESET

Vs start

60MHz

40MHz

Y CONTROL

X CONTROL

IICVCC(3.3V)GND

e-buffer f-buffer g-buffer

ADRV101~106

ADRV201~206

ADRV301~306

CLK,BLK,POL,STB

ADRV401~406

CLK,BLK,POL,STB

ADRV501~506

ADRV601~606

ADRV701~706

CLK,BLK,POL,STB

CLK_XY 20MHz),SV_SYNC

27MHz

nRESET

SW2001

28.636MHzOSC

CY2305

CY2305

LA03 CN803

CN101

CN201

CN2002

CN401 CN402 CN403

U2005

U2001 U2000

U2014 U2013U2003 U2002

U2011 U2007 U2006

U2004

X2000

X2001

X2002

[Logic Block Diagram]

Definition of Name and Terms on Logic Board


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Definition of Name and Terms on Logic Board

No. Item Explanation

LVDS connector Connector for receiving RGB, H, V, DATAEN, DCLK encoded in the LVDS from image board.

LED for operation check LED to show that Sync, clock is normally input into the logic board

I2C connector Connector connecting the Key Scan Board that checks and adjusts 256K data

256K Eeprom to save

tab le , APC tab le , dri vi ng wav ef orm tim in g and oth er opt io n, etc

Y connector Connector to output control signal of the Y driving board

X connector Connector to output control signal of the X driving board

CN401 E-address buffer connector Connector to output address data, control signal to the E-buffer board

CN402 F-address buffer connector Cnnector to output address data, control signal to the F-buffer board

CN403 G-address buffer] connector Connector to output address data, control signal to the G-buffer board

Power connector Connector to receive power 95V] to the logic board

Power fuse Fuse attached to power [5V] to the logic board

OPTION S/W Inner/Outer cut-off S/W

M O D E L

LOGIC BOARD

OPTION S/W

STATUS

REMARKS

42 SD

External

: 2 4 On

Internal

: 3 On

2 3 4

ON

OFF

Explanation of Logic Board


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Explanation of Logic Board

Logic board is composed of a logic main board that generates and outputs the address driver output signal

and the XY driving signal by processing image signal, and a buffer board that buffers the address driver output

signal and delivers it to the address driver IC (COF Module).

Logic Board Function Remarks

Logic Main

- Processes Image signal W/L, error dispersion, APC)

- Outputs image signal as address driver control signal,

data signal buffer board

- Outputs the XY driving board control signal

Buffer Board

E Buffer board

- Delivers data signal and control signal to the

right/right COF

F Buffer boadr


middle/lower COF

G Buffer board


Right/ Lower COF

2 4 Explanation of Scaler(Image Board) Operation


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2-4. Explanation of Scaler(Image Board) Operation

DIGITAL BOARD IC SIGNAL BLOCK DIAGRAM

ANALOG SignalCRYSTAL DIGITAL Signal CLOCK Signal

SDA6000

DVI

SNI

ASI500

FLI2200

VPC3230

M27V160

K4S643232E

AD9883

SiI161A

K4S643232E

K4S643232E

K4S641632E

M27V160

VPC3230K4S643232E

K4S643232E

DS90C385

6M

20.25M

DVI SOUND D-SUB D-SUBSound

S-VIDEO S-VIDEO/VIDEO SoundRS-232

FROM SMPS

FROMCONTROL

PCB74HC4052

14.3181M

20.25M

Z86129

BA7657

TO LOGIC

S-VHS Y/CR/G/B/H/V

CVBS

Y/C

Y/Pb/Pr/H/V

DVI L/R

D-SUB L/R

DVI,D-SUB L/R

S-VHS L/R

Explanation of Scaler(Image Board) Operation


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Explanation of Scaler(Image Board) OperationANALOG BOARD IC SIGNAL BLOCK DIAGRAM

ANALOG SIGNALCRYSTAL DIGITAL SIGNAL CLOCK SIGNAL

TA1101

TEA6425

BA7657

COMPONENT1 COMPONENT1 SOUNDVODEO COMPONENT2 SOUNDCOMPONENT2 Sub-wooferOutput

CXA2151

4M

MSP3451

18.432M

UPD6408320M

FROM SMPS

Y/Pb/Pr 1 Y/Pb/Pr 2VIDEO-CVBS

S-CVBS

CVBS CVBS

Y/C

Y/Pb/Pr

Y/Pb/Pr/H/V S-VHS L/R

DVI,D-SUB L/R

L/R

SUB WOOPER

SOUND OUTPUT

TUNER 2 TUNER 1

RFINPUT

M-CVBS

CN103

CN102

CN101

CN801

Factory Data per each Mode


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1. UPD 64083 (COMB FILTER)

ITEM TV/Video/S-Video/Component 1,2 SD) Component 1,2 HD) PC DVI

VAPGAIN 4 4 4 4

VAPINV 16 16 16 16YPFP 3 3 3 3

YPFG 9 9 9 9

2. VPC 3230(M) : Main VCD


CONTRAST 43 43 43 43BRIGHTNESS 47 47 47 47

PEAKING 5 5 5 5

CORING 0 0 0 0

LUMA DELAY 255 255 255 255

HPLL SPEED 1 1 1 1

YUV CONTRAST 29 29 29 29

YUV BRIGHTNESS 68 68 68 68

YUV SATCB 42 42 42 42

YUV SATCR 42 42 42 42

YUV TINT 3 3 3 3

SATURATION 2000 2000 2000 2000

TINT 32 32 32 32



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3. VPC 3230(S) : SUB VCD


PIP CONTRAST 43 43 43 43

PIP BRIGHTNESS 47 47 47 47

YUV CONTRAST 29 29 29 29

YUV BRIGHTNESS 68 68 68 68

LUMA DELAY 255 255 255 255

H POSITION 0 0 0 0

V POSITION 0 0 0 0

4. FLI 2200 (De-Interlacer)


Y CLAMP 64 64 64 64

C CLAMP 512 512 512 512

Y DELAY 4 4 4 4

C DELAY 11 11 11 11

MOTION DETECT 48 48 48 48



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5. ASI500 (SCALER MAIN / OSD)


R CONTRAST 32

G CONTRAST 32

B CONTRAST 32

R BRIGHTNESS 0

G BRIGHTNESS 0

B BRIGHTNESS 0

TEXT ALPHA 1

TEXT THRESHOLD 7

FILTER ML 0

FILTER MR 0

FILTER FR 0

FILTER MC 16

FILTER UC 0

FILTER LC 0

FILTER YPASS 0

R GAMMA 32

G GAMMA 32

B GAMMA 32

H POSITION 0

V POSITION 0

H SIZE 0

V SIZE 0

OVERSCAN B 63

OVERSCAN G 63

OVERSCAN R 63



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6. ASI500 (SCALER PIP)


PIP R CONT 32

PIP G CONT 32

PIP B CONT 32

PIP R BRIGHT 0

PIP G BRIGHT 0

PIP B BRIGHT 0

PIP FILTER LC 0

PIP FILTER ML 0

PIP FILTER MR 0PIP FILTER UC 0

8. CXA2151HD (COMPONENT MUX)


GAIN-SEL 1 1 1 1

CR GAIN 7 7 7 7

CB GAIN 7 7 7 7

Y GAIN 7 7 7 7



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7. DNIe (Picture Enhancer)

ITEM TV/Video/S-Video/Component 1 ,2(SD) Component 1,2(HD) PC DVI

BRIGHT OFFSET 0

CONTRA OFFSET 0

NR SCALE MAX 52

NR SCALE MIN 18

DE GAIN COR 3

DE GAIN CLIP 60

CE UPPER 240

CE CUTOFF 64

CE GAIN 48

WTE Y THRE 230

R CTL 2

SYNC MODE 1

PATT SEL 0

RED CONPENSA 616

BLUE CONPENSA 616

WTE GAIN 58

RAST VSIZE 1023RAST HSIZE 895

SHARP OFFSET 0



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Factory Data per each Mode9. AD 9883 (AD Converter)


R GAIN 142 142 142 142

G GAIN 142 142 142 142

B GAIN 142 142 142 142R, CR OFFSET 60 60 54 60

G, Y OFFSET 48 48 54 48

B, CB OFFSET 64 64 54 64

Auto Color

10. Logic (PDP Driver)


R DRIVE 140 140 140 140

G DRIVE 130 130 130 130

B DRIVE 120 120 120 120

R CUTOFF 0 0 0 0

G CUTOFF 0 0 0 0

B CUTOFF 0 0 0 0

GAMMA 1

GTS SET 0

ERD MODE 2

RANDOM NOISE 0

DIFF FILTER 1

APC 1

APC SET 0

APC VALUE 127

ACTIVE VPOS 12

ACTIVE HPOS 19

VSYNC POS 3

HSYNC POS 32

VSYNC WIDTH 2

HSYNC WIDTH 12



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Factory Data per each Mode11. TP LOG-ASI : Test Pattern LOGIC/SCALER


LOG PATTERN 0

LOG HIGH LEVEL 255

LOG LOW LEVEL 0

ASI COLORBAR 0

12. Option

ITEM TV/Video/S-Video/Component 1,2(SD) Component 1,2(HD) PC DVI Remark

PIX SHIFT 0 0 : OFF 1 : ON

SHIFT TEST 0 0 : minute 1 : second

PIX NUMBER 2 Number of shifted Lines horizontally

SHIFT LINE 1 Number of shifted Lines vertically

SHIFT TIME 4 Time fixed at SHIFT TEST

COUNTRY 0 0 : domestic 1 : USA 2 : Japan

TEMP PROTECT 0

SNI DEMO 0 0 : OFF 1: ON

SNI THROUGH 0 0 : NOT THROUGH 1 : THROUGH

VIDEO MUTE 10 Unit : 100msec

IRC AFN 0 0 : for customer 1 : for military

LANGUAGE 0 0 : English 1 : French 2 : Spanish

CUSTOMER 0 0 : CE 1 : VMB

TUNER 0 0:1 TUNER 1:2 TUNER

Signal Waveform at AV(Audio & Visual) Board


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Signal Waveform at AV(Audio & Visual) BoardInput Signal : 8-Color Bar

A NA LO G BO AR D IC1 03 (T EA 64 25 D) P IN 6( VI DE O- CV BS ) AN AL OG B OA RD C N1 02 P IN 12 (3D _Y _O UT )

A NAL OG BO ARD CN 102 PI N10 (3D _C_ OUT ) DI GIT AL B OA RD I C1 01( VPC 323 0D- C5) P IN5 7(V PC_ VSY NC)



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g ( & )Input Signal : 8-Color Bar

* Dimensions in mm

DIGITAL BOARD IC101(VPC3230D-C5) PIN56(VPC_HSYNC) DIGITAL BOARD IC101(VPC3230D-C5) PIN28(VPC_CLK)

DIGITAL BOARD IC104(FLI2200) PIN91(FLI_VSYNC) DIGITAL BOARD IC104(FLI2200) PIN92(FLI_HSYNC)



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g ( )Input Signal : 8-Color Bar

DIGITAL BOARD IC104(FLI2200) PIN90(FLI_DE) DIGITAL BOARD IC104(FLI2200) PIN117(FLI_CLK)

DIGITAL BOARD RW507(ASI500 OUTPUT) PIN2(MN_IN_V) DIGITAL BOARD RW507(ASI500 OUTPUT) PIN1(MN_IN_H)



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DIGITAL BOARD RW507(ASI500 OUTPUT) PIN4(MN_IN_CLK) DIGITAL BOARD IC601(SNI OUTPUT) PIN9(OUT_VSYNC)

DIGITAL BOARD IC601(SNI OUTPUT) PIN10(OUT_HSYNC) DIGITAL BOARD IC601(SNI OUTPUT) PIN8(OUT_DE)



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DIGITAL BOARD IC601(SNI OUTPUT) PIN12(OUT_CLK) ANALOG BOARD IC101(CXA2151 OUTPUT) PIN27(COMP_Y)

ANALOG BOARD IC101(CXA2151 OUTPUT) PIN26(COMP_PB) ANALOG BOARD IC101(CXA2151 OUTPUT) PIN25(COMP_PR)



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ANALOG BOARD IC101(CXA2151 OUTPUT) PIN23(COMP_V) ANALOG BOARD IC101(CXA2151 OUTPUT) PIN22(COMP_H)

DIGITAL BOARD IC705(AD9883 OUTPUT) PIN64(ASI_SUB_V) DIGITAL BOARD IC705(AD9883 OUTPUT) PIN66(ASI_SUB_H)



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DIGITAL BOARD IC705(AD9883 OUTPUT) PIN65(ASI_SUB_SOG) DIGITAL BOARD IC705(AD9883 OUTPUT) PIN67(ASI_SUB_CLK)

DIGITAL BOARD IC702(SII169CT OUTPUT) PIN47(DVI_VSYNC) DIGITAL BOARD IC702(SII169CT OUTPUT) PIN48(DVI_HSYNC)



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Signal Waveform at AV(Audio & Visual) BoardInput Signal : 8-Color Bar

DIGITAL BOARD IC702(SII169CT OUTPUT) PIN46(DVI_DE) DIGITAL BOARD IC702(SII169CT OUTPUT) PIN44(DVI_CLK)

Trouble Shooting for PDP Set


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g

Turn on the set

L ED N or ma l

OK

NO

C h eck V S _ON (3V)

CN803(SMPS pin2)

NO

Change

Logic

R e mov e a l l C o nne c tor s

f ro m S MP S( ex ce pt A V) a nd

C h eck t h e p r ote c tio n

o r v o lta g es

P r ote c tio n o r

L E D p r obl e ms

C h eck P S _ON (0V : S MP S C N8 02 p in 4)

C he ck s ta nd _b y 5 V( SMP S C N8 02 p in 2)

OK

Connect

X-Main

OK

Connect

Address

Buffer

Connect

Y-Main

OK

OK

Check

other

Boards

Change

Address

Buffer

NO

hange

Y-Main

NO

hange

X-Main

NO

NO LED

Change

SMPS

NO

C h eck V o lta g es

on the SMPS

(Vs,Va,Ve,Vset..)

OK

C he ck t he

Key-Pad

R e mov e a l l C o nne c tor s

f ro m S MP S a nd C he ck t he

v ol ta ge s o n A V B oa rd s

NO

OK

Change

Digital

Change

SMPS

NO

R em ov e C on ne ct or s f ro m

X,Y-Main,Address

B uf fe rs a nd C he ck t he

v ol ta ge s o n S MP S a ga in

NO

NO

Change

SMPS

OK

OK

N O V o lta g es

Check thedamaged

components on

X , Y-M a in

Address Board

Ye s C ha ng e t he

damaged Board

N O D a mag e d C o mpo n ent s

C he ck t he F us es o n

X,Y-Main Boards

(F4003,F5003)

NO

C ha ng e t he

damaged Board

OK

Change Y-Main

NO

Change X-Main

NO

Check whether

a lw ay s N o V id eo

a bo ut a ll A V i np ut s

NO, can t see

a n y V i deo

Change

Digital

NO NO

C he ck t he

L VD S c ab le

Change

Logic

I can see some Video

e x) T V, Vi de o o r e tc I np ut so ur ce

Change

Analog

A lm os t N o

Voltages

o n t he S MP S?

Only Vs or Va cannot be measured

Comparison with New Models


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p

Project Alexander (V2) Mozart (V3) Nelson (V3)

Design

Brightness 700cd/m2 1000cd/m2 1000cd/m2

Contrast ratio 1200:1 3000:1 3000:1

Tuner 2Tuner 2Tuner 1Tuner

Audio out 10W x 2 15W x 2 15W x 2

Sound Dolby Virtual SRS Tru Surround XT SRS Tru Surround XT

Speaker Not Included Included Not Included

Video input 1Rear 2Rear 1Rear

S-Video input 1Rear 1Rear 1Rear

ComponentInput

2Rear 2Rear 1Rear

Side Input - CVBS, S-Video -

DVI 1Rear 1Rear 1Rear

PowerConsumption

330W 330W 330W

Etc. - Touch Pad, Melody -

Samsung Plasma Training Manual

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