SAMA5D3 Xplained Evaluation Kit User's...
Transcript of SAMA5D3 Xplained Evaluation Kit User's...
2019 Microchip Technology Inc. DS50002884A-page 1
Scope
This user guide introduces the Microchip SAMA5D3 Xplained evaluation kit and describes the development and debug-ging capabilities for applications running on a SAMA5D36 Arm®-based microprocessor unit (MPU).
This guide provides details on the SAMA5D3 Xplained evaluation kit. It is made up of four main sections:
• Section 1. “Evaluation Kit Specifications” describes the evaluation kit content and its main features. • Section 2. “Power-Up” provides instructions to power up the SAMA5D3 Xplained board. • Section 3. “Hardware Introduction” provides an overview of the SAMA5D3 Xplained board.• Section 4. “Board Components” describes the SAMA5D3 Xplained board components.
Contents
• Boards- One SAMA5D3 Xplained board
• Cables- One Micro-AB type USB cable
• A welcome letter
Related Items
• SAMA5D3 Series Data Sheet• SAMA5D3 Xplained Getting Started
SAMA5D
3XPLAINE
D
SAMA5D3 Xplained Evaluation Kit User’s Guide
SAMA5D3 XPLAINED
SAMA5D3 XPLAINED
DS50002884A-page 2 2019 Microchip Technology Inc.
1. Evaluation Kit Specifications
1.1 Electrostatic Warning
1.2 Power Supply Warning
Table 1-1: Evaluation Kit Specifications
Characteristic Specifications
TemperatureOperating 0°C to +70°C
Storage -40°C to +85°C
Relative Humidity 0 to 90% (non-condensing)
RoHS status Compliant
Ordering code ATSAMA5D3-XPLD
WARNINGESD-Sensitive Electronic Equipment!
The evaluation kit is shipped in a protective anti-static package. The board system must not be sub-ject to high electrostatic potentials.
We strongly recommend using a grounding strap or similar ESD protective device when handlingthe board in hostile ESD environments (offices with synthetic carpet, for example). Avoid touchingthe component pins or any other metallic element on the board.
WARNINGHardware Power Supply Limitation
Using a power adapter greater than 5Vcc (e.g. the 12Vcc power adapters from other kits such asArduino kits) may damage the board.
WARNINGHardware Power Budget
Using the USB as the main power source (max. 500 mA) is acceptable only with the use of the on-board peripherals and low-power LCD extension.
When external peripheral or add-on boards need to be powered, we recommend the use of an exter-nal power adapter connected to a J2 DC Jack (can provide up to 1.2A on the 3.3V node).
Electrostaticsensitivedevice
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SAMA5D3 XPLAINED
2. Power-Up
Several power source options are available to power up the SAMA5D3 Xplained board.
The board can be:
• USB-powered through the USB Micro-AB connector (J6 connector - default configuration)• Powered through an external AC-to-DC adapter connected via a 2.1 mm center-positive plug into the optional power jack of the
board. The recommended output voltage range of the power adapter is 5V at 2A.• Powered through the Arduino shield
2.1 Power up the Board
Unpack the board, taking care to avoid electrostatic discharge. Simply connect the USB Micro-AB cable to the connector (J6).Then, con-nect the other end of the cable to a free USB port of your PC.
2.2 Sample Code and Technical Support
After booting up the board, you can run sample code or your own application on the board. You can download sample code and get tech-nical support from the Microchip website.
Linux® software and demos can be found on the website Linux4SAM.
WARNINGUnlike Arduino Uno boards, the SAMA5D3 Xplained board runs at 3.3V. The maximum voltage thatthe I/O pins can tolerate is 3.3V. Providing higher voltages (e.g. 5V) to an I/O pin could damage theboard.
Table 2-1: Electrical Characteristics
Electrical Parameter Values
Input voltage 5 VCC
Maximum input voltage 6 VCC
Max DC 3.3V current available 1.2A
I/O Voltage 3.3V only
SAMA5D3 XPLAINED
3. Hardware Introduction
3.1 Introduction
The SAMA5D3 Xplained board is a fully-featured evaluation platform for Microchip SAMA5D3 series MPUs. It allows users to extensivelyevaluate, prototype and create application-specific designs.
3.2 Equipment List
The SAMA5D3 Xplained board is built around the integration of a Cortex®-A5-based MPU (BGA 324 package) with external memory, dualEthernet physical layer transceiver, two SD/MMC interfaces, two host USB ports and one device USB port, one 24-bit RGB LCD interfaceand one debug interface.
Seven headers, compatible with Arduino R3, are available for various shield connections.
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SAMA5D3 XPLAINED
3.3 Board features
Table 3-1: Board Specifications
Characteristics Specifications
PCB characteristics 125 x 75 x 20mm (10-layers)
ProcessorSAMA5D36 (324-ball BGA package) ARM Cortex-A5 Processor with ARM v7-A Thumb2® instruction set, core frequency up to 536 MHz.
Processor clock sources12-MHz crystal oscillator
32.768-kHz crystal oscillator
Memory2 x 1Gb DDR2 (16M x 16 bits x 8 banks)
1 x 2Gb SLC NAND Flash (256M x 8 bits)
Optional on-board memoryOne Serial EEPROM SPI
One 1-Wire EEPROM
SD/MMCOne 8-bit SD card connector
One optional 4-bit Micro-SD card connector
USBTwo USB Hosts with power switch
One Micro-AB USB device
Display interfaceOne LCD interface connector, LCD TFT Controller with overlay, alpha-blending, rotation, scaling and color space conversion
EthernetOne Gigabit Ethernet PHY (GRMII 10/100/1000)
One Ethernet PHY (RMII 10/100)
Debug portOne JTAG interface connector
One serial DBGU interface (3.3V level)
Expansion connectors
Arduino R3 compatible set of headers
The SAMA5D36 GPIO,TWI, SPI, USART, UART, Audio and ISI interfaces are accessible through these headers.
Board supply voltage
5V from USB or power jack or Arduino shield
On-board power regulation is performed by a Power Management Unit (PMU)
Battery On-board optional power Cap for CMOS backup
User interfaceReset, wake-up and free user push button
One red user/power LED and one blue user LED
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SAMA5D3 XPLAINED
4. Board Components
4.1 Board Overview
The full-featured SAMA5D3 Xplained board integrates several peripherals and interface connectors, as shown in Figure 4-1.
Figure 4-1: SAMA5D3 Xplained Board Overview
ATSAMA5D36 CU
1401 AXXXXXXXXXX ARM
J15 PIO Expansion
1Gb DDR2 Memory
1Gb DDR2 Memory
2Gb Nand Flash Memory
System Buttons
JTAG Interface
LCD Connector
Ethernet 10/100
GigaBit Ethernet
J18 PIO Expansion
Free User Push Button
ADC Inputs and CAN Interfaces
Debug Interface
SAMA5D36
Voltages and Reset Interface
ADC Inputs Expansion
Optional Supply Input
USB A DeviceSupply Input
SPI Interface
J20 PIO Expansion
J19 PIO Expansion
XX
USB Host Interfaces
ectorA
t
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SAMA5D3 XPLAINED
The SAMA5D3 Xplained board is equipped with the interface connectors described in Table 4-1.
Table 4-1: SAMA5D3 Xplained Board Interface Connectors
Header Interfaces to
J2 Main power supply
J6 USB-A device. Supports USB device using a Micro-AB connector
J7 (upper) USB-B Host. Supports USB host using a type A connector
J7 (lower) USB-C™ Host. Supports USB host using a type A connector
J23 Serial DBGU 3.3V level
J24 JTAG, 20-pin IDC connector
J10 SD/MMC connector
J11 Micro-SD connector
J12 Gigabit Ethernet ETH0
J13 Ethernet ETH1
J22Expansion connector with all LCD controller signals for display module connection (QTouch®, TFT LCD display with Touch Screen and backlight
C41 Optional SuperCap
J14–J21 Expansion connectors with Arduino R3 compatible PIO signals
– Various test points located on the board
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SAMA5D3 XPLAINED
4.2 Function Blocks
Figure 4-2: Evaluation Kit Architecture
4.2.1 Processor
The SAMA5D3 Xplained board is built around the SAMA5D36, a Cortex-A5 application processor which combines high-performance com-puting device with low-power consumption and a wide range of communication peripherals. It features a combination of user interfacefunctionalities and high data rate IOs, including LCD controller, touchscreen, camera interface, Gigabit and 10/100 Ethernet ports, high-speed USB and SDIO.
The ARM Cortex-A5 supports the latest generation of DDR2 and NAND Flash memory interfaces for program and data storage. An internal166-MHz multi-layer bus architecture associated with 24 DMA channels and two 64-Kbyte SRAM blocks, sustains the high bandwidthrequired by the processor and the high-speed peripherals.
4.2.2 Clock Circuitry
The SAMA5D3 Xplained evaluation board features four clock sources:
• Two clocks are alternatives for the SAMA5D3 series processor main clock• Two crystal oscillators are used for the GETH and Ethernet MII/RMII chip
Table 4-2: Main Components Associated with the Clock Systems
Quantity Description Component Assignment
1 Crystal for internal clock, 12 MHz Y1
1 Crystal for RTC clock, 32.768 kHz Y2
1 Oscillator for ethernet clock RGMII, 25 MHz Y3
1 Oscillator for ethernet clock RMII, 25 MHz Y4
JTAGDBGU
JTAG & DBGU
SERIALDATAMicro SD
CARD
10/100/1000FAST ETHERNET
10/100ETHERNETSD
CARDLCD
Connector FLASH ETH0 ETH1
PIO A,...EPIO A,...E
SinglePMU
Solution5V INPUT
SAMA5D36
CORTEX®-A5 PROCESSOR
2GbDDR2
SDRAM
2GbNANDFLASH
USBDEVICE
USBHostx2
ANALOG Reference
VBAT
USERLEDS
PIO
Exp
ansio
n H
eaders
Power rails
USB A,B,C
ResetForce PwrOn
PushButtons
EBI
5V & 3V3
(Up to 4Gb)
(Up to 4Gb)
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SAMA5D3 XPLAINED
4.2.3 Power Supplies
The on-board power supply generation is based on the Active-Semi® Power Management Unit (PMU) featuring a 3-channel (3.3V / 1.8V/1.2V or 1.0V) topology. For maximum efficiency, these supply channels are generated by three integrated step-down converters.
In addition to these 3 DCDC channels, 4 LDO channels with low noise and high PSRR performance are available for the application. Thesechannels are disabled at startup by default and can be turned on and adjusted under software control through an I²C link. They are alsoused to supply the 2.5V VDDFUSE and the 3.3V VDDANA power inputs of the processor.
The power supply sequencing of the three primary channels is controlled by the PMU itself in full compliance with the SAMAD3 require-ments. The turn-on sequence is: 3.3V first, then 1.8V and finally 1.2V.
Table 4-3 summarizes the power specifications.
WARNINGThere is a known error on the ACT8865 I²C implementation. The port must be shut off after config-uration or problems may occur with devices using the same I²C channel, e.g., TM43xx LCD display.
Refer to the ACT8865 data sheet at http://www.active-semi.com/ for more details.
WARNINGThis evaluation kit was equipped with an engineering version of ACT8865 PMIC known asACT8865QI303-T. The singularity of this engineering version is that OUT4 and OUT5 outputs, nor-mally enabled at power-up, are disabled at power-up. Consequently, VDDANA and VDDFUSEpower inputs of the processor are OFF when the external reset pin (NRST) is released. They musttherefore be turned on by software in the very first execution steps of the application. In particular,VDDFUSE is needed to switch SAMA5D3 devices in Secure mode.
The engineering version ACT8865QI303-T of the active semi PMIC is end-of-life (EOL) and replacedby ACT8865QI305-T devices that have OUT4 and OUT5 enabled by default at power-up. Refer tothe following application note:
https://active-semi.com/wp-content/uploads/ActiveSemi_-ACT8865QI305-T_versus_ACT8865QI303-T.pdf
Table 4-3: Supply Group Configuration
Nominal Name Power Domains Power Source
3.0V VDDBUThe slow clock oscillator, the internal 32K RC, the internal 12 MHz RC and a part of the system controller
Optional on-board battery
3.3V VDDIOP0 A part of peripheral I/O lines
PMU
3.3V VDDIOP1 A part of peripheral I/O lines
3.3V VDDUTMII The three USB interfaces
3.3V VDDOSC The main oscillator cells
3.3V VDDANA The analog-to-digital converter
1.2V VDDCOREThe core, including the processor, the embedded memories and the peripherals
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SAMA5D3 XPLAINED
Note: Jumper footprints are available on-board to measure power consumption on main power lines. By default, the jumpers are notimplemented. They are short-circuited by a thin PCB wire. To use this functionality, open the short circuit and mount a 2-pinjumper.
Figure 4-3: Board Power Management Schematic
1.2V VDDUTMIC The USB UTMI + core
PMU
1.2V VDDPLLA The PLLA cell
1.8V VDDIODDR DDR2 interface I/O lines
1.8V VDDIOMNAND, NOR Flash and SMC interface I/O lines
3.0V to
3.3VADVREF ADC reference voltage J15 header
2.5V VDDFUSE Fuse box for programming PMU
Table 4-3: Supply Group Configuration (Continued)
Nominal Name Power Domains Power Source
BP2
BP1
5V_MAIN
VDDCORE
VDDIOP1
VDDIOP0
VDDANA
VDDPLLA
VDDOSC
VDDIODDR
VDDIOM
AVDDL_PLL
DVDDL
AVDDL
FUSE_2V5
5V_MAIN
3V3
3V3
VDDUTMIC
3V3
TWCK_PMIC[7]TWD_PMIC[7]
NRST[5,9,10,11]
SHDN[5]
PC31[7]
WKUP[5]PE30[7] (1V2)
(1V8)
(3V3)
(3V3)
(2V5)
RESETWAKUP orForce Power ON
AutoPWRON(option)
PC27PC26
C10100nFC10100nF
L9 2.2uHL9 2.2uH
R1450KR1450K
C212.2uFC212.2uF
BP2BP2
C41uFC41uF
C1310uFC1310uF
R16 0RR16 0R
C232.2uFC232.2uF
R17 2R2R17 2R2
C20100nFC20100nF
MN1 ACT8865MN1 ACT8865
GN
DP
129
GN
DA
2
INL45 5VP131
INL67 6
GN
DP
228
VP226
GN
DP
314
EX
PA
D33
VP316NC225
VDDREF23
nRST011nIRQ12nPBSTAT13VSEL20NC118PWRHLD10PWREN17
SCL21SDA22
REFBP32
nPBIN9
SW1 30OUT1 1
OUT2 24SW2 27
SW3 15OUT3 19
OUT4 3
OUT5 4
OUT6 7
OUT7 8
C24.7uFC24.7uF
JP1 DNP(JUMPER)JP1 DNP(JUMPER)
1 2
Q1
IRLML2502
Q1
IRLML2502
1
3
2
C51uFC51uF
R19
100K 1%
R19
100K 1%
C14.7uFC14.7uF
R150RR150R
L11180ohm at 100MHz
L11180ohm at 100MHz
1 2
L8180ohm at 100MHz
L8180ohm at 100MHz
1 2
C1847nFC1847nF
C222.2uFC222.2uF
JP3 DNP(JUMPER)JP3 DNP(JUMPER)
1 2
R11 0RR11 0R
TP2SMD
TP2SMD
C264.7uFC264.7uF
C6
1uF
C6
1uF
R61.5K 1%
R61.5K 1% L5 2.2uHL5 2.2uH
JP4 DNP(JUMPER)JP4 DNP(JUMPER)1 2
C25100nF
C25100nF
L6
10uH60mA
L6
10uH60mA
C34.7uFC34.7uF
JP2 DNP(JUMPER)JP2 DNP(JUMPER)
1 2
R71.5K 1%R7
1.5K 1%
C114.7uFC114.7uF
R5 2R2R5 2R2
R810KR810K
R41RR41R
C17100nFC17100nF
C910uFC910uF
L7 2.2uHL7 2.2uH
C19100nF
C19100nF
L12
10uH60mA
L12
10uH60mA
C74.7uFC74.7uF
R186 0RR186 0R
L3180ohm at 100MHz
L3180ohm at 100MHz
1 2
L1180ohm at 100MHz
L1180ohm at 100MHz
1 2
R12 49.9K
L10180ohm at 100MHz
L10180ohm at 100MHz
1 2
C1510uFC1510uF
TP1SMD
TP1SMD
C14100nFC14100nFR18 1KR18 1K
C13010nFC13010nF
C1610uFC1610uF
C810uFC810uF
R9 DNP(0R)R9 DNP(0R)
C242.2uFC242.2uF
R13 0RR13 0R
R10 2R2R10 2R2
L4
10uH60mA
L4
10uH60mA
L2180ohm at 100MHz
L2180ohm at 100MHz
1 2
BP1BP1
C1210uFC1210uF
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SAMA5D3 XPLAINED
4.2.3.1 Power Options
Several power options are available to configure the SAMA5D3 Xplained board powering scheme.
The power sources are selected by a set of 0R resistors.
The USB-powered operation is the default configuration. The power source is the USB device port (J6) connected to a PC or a mini-AB5V DC supply. The USB supply is sufficient to power the board in most applications if USB host ports are not used. If USB host ports areused, it is recommended to use a DC supply source.
Schematic diagrams of various power options are illustrated in Figure 4-4.
Figure 4-4: Input Powering Scheme Option Schematic
Note: USB-powered operation is a good “single cable” solution because it combines powering and board control through a uniquecable. Consequently, it eliminates the need for other wires and batteries. This power option is suitable for most projects thatonly require 5 volts at up to 500 mA.
4.2.3.2 Mains Power Adapter
A mains power supply adapter can be used to provide power to the board. A regulated 5V DC supply of typically 2A is required but acurrent range of 3A is recommended if the USB ports and expansion headers are likely to be used. It needs a 2.1 mm plug with a center-hot configuration.
If you are using the USB host ports or expansion board Arduino shields, a higher current is required. To supply the full 500 mA per port,a mains power adapter must be used.
4.2.3.3 VBAT
By default, VDDBU is delivered through the 3.3V node. An optional SuperCap (C41), used for real-time clock backup, is provided. Theboard does not come equipped with the SuperCap. When the SuperCap is not installed, an R185 must be installed. You must make surethat the R185 is removed prior to installing the SuperCap.
Figure 4-5: VBAT Powering Scheme Option Schematic
4.2.4 Reset Circuitry
The reset sources for the SAMA5D3 Xplained board are:
5V_MAINVbus[5]
5V_Ext[11]
R175 0RR175 0R
J2
DNP(DC JACK)
J2
DNP(DC JACK)
3
12
R176 DNP(0R)R176 DNP(0R)D4
P4SMAJ5.0A
D4
P4SMAJ5.0A12
R3 DNP(0R)R3 DNP(0R)
R1 0RR1 0R
R2 DNP(0R)R2 DNP(0R)
R177 DNP(0R)R177 DNP(0R)
TDITMSTCKTDONTRST
NRST
VDDBU
3V3
3V3
TMS[11]TCK[11]TDO[11]
TDI[11]
NRST[4,9,10,11]NTRST[11]
VBat[11]
(Super)-Capacitorenergy storage
Place TP4 to Bottom
Populate R185 ifno Super Cap (C41)
R25 10KR25 10K
R185
1.5K 1%
R185
1.5K 1%
D1
BAT54CLT1
D1
12
3
TP4SMDTP4SMD
C2710nFC2710nF
C28100nFC28100nFC41
DNP(0.2F/3V3)
C41
DNP(0.2F/3V3)
TDOM11
TMSN10TCKP9
NTRSTP11
TDIR8 JTAGSELT9
BMSU9 TSTU15
NRSTV9
VDD
BUV1
5
R231.5K 1%R231.5K 1%
R21100K 1%
R21100K 1%
R22DNP(100K)R22DNP(100K)
R20 100RR20 100R
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SAMA5D3 XPLAINED
• Power-on reset from the Power Management Unit (PMU),• Reset Push button BP2,• JTAG reset from an in-circuit emulator (through JTAG interface)
4.2.5 Memory Organization
The SAMA5D3x-series processor features a DDR2/SDRAM memory interface and an External Bus Interface (EBI) to interface with a widerange of external memories and to almost any kind of parallel peripherals.
The memory devices that equip the SAMA5D3 Xplained evaluation kit are as follows:
• Two DDR2/SDRAM (MT47H64M16HR) used as main system memory (256 MByte). The board includes 2 Gbits of on-board sol-dered DDR2 (double data rate) SDRAM. The footprints can also host two DDR2 (MT47H128M16RT) from Micron® for a total of 512 MBytes of DDR2 memory. The memory bus is 32 bits wide and operates with a frequency of up to 166 MHz (See Figure 4-6).
• One NAND Flash (MT29F2G08ABAEAWP) connected to the processor. The default size is 256 Mbytes. The footprint can also host a 4-Gbit Micron chip for a total of 512 MBytes of NAND Flash memory (See Figure 4-7).
Figure 4-6: DDR2 Schematic
DDR_A8DDR_D9DDR_D10DDR_D11DDR_D12DDR_D13
DDR_D15DDR_D14
DDR_A1
DDR_A9
DDR_A2 DDR_D2
DDR_A10
DDR_A3
DDR_A11
DDR_A4
DDR_A12
DDR_A5
DDR_D1
DDR_VREF
DDR_D0
DDR_A6
DDR_D4DDR_D3
DDR_A7DDR_D6DDR_D5
DDR_D7DDR_D8
DDR_A0
DDR_A8
DDR_D27DDR_D26DDR_D25
DDR_D31
DDR_D29DDR_D28
DDR_D30
DDR_A1
DDR_A9
DDR_A2
DDR_A10
DDR_D18DDR_A3
DDR_A11
DDR_A4
DDR_A12
DDR_A5
DDR_VREF
DDR_D17DDR_D16
DDR_A6
DDR_D19DDR_D20
DDR_D22DDR_A7 DDR_D23
DDR_D21
DDR_D24
DDR_A0
DDR_DQM0
DDR_DQS1
DDR_DQS0
DDR_CS
DDR_BA0DDR_BA1DDR_BA2
DDR_CKE
DDR_WE
DDR_CLK
DDR_RAS
DDR_CLKN
DDR_CAS
DDR_DQM2
DDR_DQS2
DDR_DQS3
DDR_CS
DDR_BA0DDR_BA1DDR_BA2
DDR_WE
DDR_CKE
DDR_RAS
DDR_CLK
DDR_CAS
DDR_CLKN
DDR_A13
DDR_DQM1DDR_DQM3
DDR_A13
VDDIODDRVDDIODDR
VDDIODDR
VDDIODDR
DDR_A[0..13]
DDR_D[0..31]
C98100nFC98100nF
C73 100nFC73 100nF
C100100nFC100100nF
C68 100nFC68 100nF
R39 4.7KR39 4.7K
C93 100nFC93 100nF
C90 100nFC90 100nF
C69 100nFC69 100nF
R41 4.7KR41 4.7K
C91 100nFC91 100nF
C70 100nFC70 100nF
C97 100nFC97 100nF
MT47H64M16HR
DDR2 SDRAM
MN5
MT47H64M16HR
DDR2 SDRAM
MN5
A0M8A1M3A2M7A3N2A4N8A5N3A6N7A7P2A8P8A9P3A10M2
BA0L2
ODTK9
DQ0 G8DQ1 G2DQ2 H7DQ3 H3DQ4 H1DQ5 H9DQ6 F1DQ7 F9
UDQSB7UDQSA8
LDMF3
VDD J9VDD M9
VDDL J1
VREF J2
VDDQ E9
VSS A3VSS E3
VDDQ A9
VDD E1
RFU1A2RFU2E2
CKEK2
CKJ8CKK8
CASL7RASK7
WEK3
CSL8 VDDQ C3VDDQ C7VDDQ C9
VSSQ D8VSSQ E7VSSQ F2VSSQ F8
VDD A1
VSS J3
A11P7
BA1L3
A12R2
BA2L1
VSS N1
VSSDL J7
VSSQ B2
RFU3R3
DQ8 C8DQ9 C2
DQ10 D7DQ11 D3DQ12 D1DQ13 D9DQ14 B1DQ15 B9
VDD R1
VDDQ G1
VDDQ G7VDDQ G9
VSS P9
VSSQ D2
VSSQ A7
VSSQ B8
VSSQ H2VSSQ H8
VDDQ G3
VDDQ C1
UDMB3
LDQSE8 LDQSF7
RFU4R7
A13R8
R40 4.7KR40 4.7K
C79 100nFC79 100nF
R36 DNP(1K)R36 DNP(1K)C71 100nFC71 100nF
R42 4.7KR42 4.7K
MT47H64M16HR
DDR2 SDRAM
MN4
MT47H64M16HR
DDR2 SDRAM
MN4
A0M8A1M3A2M7A3N2A4N8A5N3A6N7A7P2A8P8A9P3A10M2
BA0L2
ODTK9
DQ0 G8DQ1 G2DQ2 H7DQ3 H3DQ4 H1DQ5 H9DQ6 F1DQ7 F9
UDQSB7UDQSA8
LDMF3
VDD J9VDD M9
VDDL J1
VREF J2
VDDQ E9
VSS A3VSS E3
VDDQ A9
VDD E1
RFU1A2RFU2E2
CKEK2
CKJ8CKK8
CASL7RASK7
WEK3
CSL8 VDDQ C3VDDQ C7VDDQ C9
VSSQ D8VSSQ E7VSSQ F2VSSQ F8
VDD A1
VSS J3
A11P7
BA1L3
A12R2
BA2L1
VSS N1
VSSDL J7
VSSQ B2
RFU3R3
DQ8 C8DQ9 C2
DQ10 D7DQ11 D3DQ12 D1DQ13 D9DQ14 B1DQ15 B9
VDD R1
VDDQ G1
VDDQ G7VDDQ G9
VSS P9
VSSQ D2
VSSQ A7
VSSQ B8
VSSQ H2VSSQ H8
VDDQ G3
VDDQ C1
UDMB3
LDQSE8 LDQSF7
RFU4R7
A13R8
C94 100nFC94 100nF
C78 100nFC78 100nF
C74 100nFC74 100nFR38 0RR38 0R
C95 100nFC95 100nF
C75 100nFC75 100nF
C96 100nFC96 100nF
R37 0RR37 0R
C88 100nFC88 100nF
C80 100nFC80 100nF
C89 100nFC89 100nF
C82 100nFC82 100nF
R35 DNP(1K)R35 DNP(1K) C66 100nFC66 100nF
C83 100nFC83 100nFC81 100nFC81 100nF
C84 100nFC84 100nF
C76 100nFC76 100nF
C86 100nFC86 100nFC85 100nFC85 100nF
C77 100nFC77 100nF
C67 100nFC67 100nF
C87 100nFC87 100nF
C92 100nFC92 100nF
C72 100nFC72 100nF
DDR_VREF
VDDIODDR
R461.5K 1%R461.5K 1%
R451RR451R
R471.5K 1%R471.5K 1%
C1014.7uFC1014.7uF
TP3SMDTP3SMD
L16
10uH60mA
L16
10uH60mA
C102100nFC102100nF
C104100nFC104100nF
C1034.7uFC1034.7uF
DS50002884A-page 12 2019 Microchip Technology Inc.
SAMA5D3 XPLAINED
Figure 4-7: NAND Flash Schematic
The following memory part numbers are recommended:
4.2.6 SD/MMC Interface
The SAMA5D3 Xplained board features two high-speed Multimedia Card Interfaces (MCI).
• The first interface is used as an 8-bit interface (MCI0), connected to a SD/MMC card slot (J10) located on the bottom side of the PCB.
• The second interface is used as a 4-bit interface (MCI1), connected to an optional Micro-SD card connector (J11) located on the top side of the PCB.
The MCI0 SD card power line is enabled by default. It is PIO-controlled through a MOSFET transistor.
Note: The power source is VCC (3.3 volts).
4.2.6.1 J10 SD Card Slot
When a card is inserted into the SD/MMC connector, the Card Detect pin (PE0) is tied to ground.
Table 4-4: Recommended Memories
Part Number Supplier Size Type
MT47H128M16 Micron 2 Gb (16 M x 16 x 8 banks) DDR2 - BGA
MT47H128M32 Micron 4 Gb (32 M x 16 x 8 banks) DDR2 - BGA
MT29F2G08 Micron 2 Gb NAND Flash - TSOP
MT29F4G08 Micron 4 Gb NAND Flash - TSOP
NRDNWE
M_EBI_D2
M_EBI_D4M_EBI_D3
M_EBI_D6M_EBI_D7
M_EBI_D5
M_EBI_D0M_EBI_D1
NANDRDY
PE21PE22
NCS3 VDDIOM
VDDIOM
(NANDCE)
(NANDCLE)(NANDALE)
C105100nFC105100nF
R48100K 1%
R48100K 1%
R50100K 1%
R50100K 1%
JP5
JUMPER
JP5
JUMPER
12
R49100K 1%
R49100K 1%
MN6MT29F2G08ABAEAWPMN6MT29F2G08ABAEAWP
WE18
N.C66
VCC 37
CE9
RE8
N.C1120
WP19
N.C55
N.C11N.C22N.C33N.C44
DNU121DNU222
N.C1223N.C1324
R/B7
I/O8_N.C 26I/O9_N.C 27
I/O10_N.C 28
I/O0 29
VCC_N.C 34
N.C1435VSS 36
DNU338
VCC_N.C 39
VCC 12
VSS 13
ALE17
N.C811N.C710
N.C914N.C1015
CLE16
VSS_N.C 25
I/O11_N.C 33
I/O1 30
I/O3 32I/O2 31
I/O15_N.C 47I/O14_N.C 46I/O13_N.C 45
I/O7 44I/O6 43I/O5 42I/O4 41
I/O12_N.C 40
VSS_N.C 48
C106100nFC106100nF
2019 Microchip Technology Inc. DS50002884A-page 13
SAMA5D3 XPLAINED
Figure 4-8: J10 SD Card Schematic
4.2.6.2 J11 SD Card Slot (optional)
When a card is inserted into the Micro SD connector, the Card Detect pin is tied to ground. This is detected on pin PE1 of the main pro-cessor.
Figure 4-9: J11 Micro SD Card Schematic
4.2.7 Serial Peripheral Interface (SPI)
The SAMA5D3X-series processor features two high-speed Serial Peripheral Interfaces. One port is used to interface with the optional on-board serial DataFlash®.
There are four main signals used in the SPI interface; Clock, Data In, Data Out, and Chip Select.
VDDIOP1VDD_MCI0
VDDIOP1
VDDIOM
PD1[7]
PE2 [7]
PD9[7]
PD0[7]PD4[7]PD3[7]
PE0[7]
PD6[7]PD7[7]PD8[7]
PD5[7]
PD2[7]
(MCI0_CD)
(MCI0_WP)
(MCI0_DA1)(MCI0_DA0)
(MCI0_CK)
(MCI0_CDA)(MCI0_DA3)(MCI0_DA2)
(MCI0_DA4)(MCI0_DA5)
(MCI0_DA7)(MCI0_DA6)
C10810uFC10810uF
R55
DNP(4.7K)
R55
DNP(4.7K)
R12
268
KR
122
68K
R182 22RR182 22R
R12
768
KR
127
68K
J10
7SDMM-B0-2211
J10
7SDMM-B0-2211
8
5
76
43219
141516
13121110
R54
10K
R54
10K
R12
468
KR
124
68K
R53100K 1%R53100K 1%
R57 0RR57 0R
R12
668
KR
126
68K
R12
168
KR
121
68K
Q3IRLML6402Q3IRLML6402
1
3 2
R12
368
KR
123
68K
R5610KR5610K
R12
868
KR
128
68K
C109100nFC109100nF
R12
568
KR
125
68K
VDDIOM
VDDIOP1
PB20[7]PB21[7]PB22[7]PB23[7]
PB19[7]PB24[7]
PE1[7]
(MCI1_DA1)
(MCI1_CK)(MCI1_CDA)
(MCI1_DA3)(MCI1_DA2)
(MCI1_CD)
(MCI1_DA0)
Micro SD CARD INTERFACE - MCI1
C11010uFC11010uF
R183 22RR183 22R
J11
DNP(MCTF-0403)
J11
DNP(MCTF-0403)
DAT07DAT18DAT21DAT32
VDD4VSS6
CD9PGND10
PGND 11PGND 12PGND 13
NC 14NC 15
CMD3CLK5
R12
968
KR
129
68K
R5910KR5910K
R58
10K
R58
10K
R13
068
KR
130
68K
R11
2D
NP
(68K
)R
112
DN
P(6
8K)
R13
168
KR
131
68K
R13
268
KR
132
68K
C111100nFC111100nF
DS50002884A-page 14 2019 Microchip Technology Inc.
SAMA5D3 XPLAINED
Figure 4-10: Optional Serial DataFlash Schematic
PD11
PD12PD10
PD13
VDDIOP1
VDDIOP1
(SPI0_MIS0)(SPI0_MOSI)
(SPI0_SPCK)
(SPI0_CS)
C107100nFC107100nF
MN8
DNP(N25Q032A13ESE40F)
MN8
DNP(N25Q032A13ESE40F)
HOLD/DQ3 7GND 4
VCC 8
S1
C6
DQO5DQ12
W/Vpp/DQ2 3
JP6JUMPER
JP6JUMPER
1 2
R52100K 1%
R52100K 1%
2019 Microchip Technology Inc. DS50002884A-page 15
SAMA5D3 XPLAINED
4.2.8 Optional 1-Wire EEPROM
The SAMA5D3 Xplained board can use a 1-Wire device as “soft label” to store data such as chip type, manufacturer’s name, productiondate, etc.
Figure 4-11: Optional One-Wire EEPROM Schematic
4.2.9 10/100/100 Ethernet Port
The SAMA5D3 Xplained board features a MICREL PHY device (KSZ9031RN) operating at 10/100/1000 Mb/s. The board supports theRGMII Interface mode. The Ethernet interface consists of four pairs of low-voltage differential pair signals designated from GRX± andGTX± plus Control signals for link activity indicators. These signals are routed to the 10/100/1000BASE-T RJ45 connector (J12).
For monitoring and control purposes, LEDs are integrated in the RJ45 connectors to indicate activity, link, and speed status informationfor the corresponding ports.
For more information about the Ethernet controller device, refer to the MICREL KSZ9031RN data sheet.
Figure 4-12: Gigabit Ethernet Schematic
PE23
VDDIOM
R511.5KR511.5K
MN7
DNP(DS2431)
MN7
DNP(DS2431)
IO2
GN
D1
NC1 3NC2 4NC3 5NC4 6
MN11
DNP(DS28E05)
MN11
DNP(DS28E05)
NC2
IO1
GND 3
PB3PB2PB1PB0
PB4PB5
PB6PB7
ETH0_A+ETH0_A-
ETH0_B-ETH0_C+ETH0_C-
ETH0_D+ETH0_D-
PB16PB11
PB13
PB9
PB17PB10
ETH0_LED2
XI XO
ETH0_LED1
XI
XOPB18
PB8
ETH0_B+
VDDIOP1
DVDDL
AVDDL
AVDDH
AVDDL_PLL
VDDIOP1
VDDIOP1
VDDIOP1
VDDIOP1
PB[0..31]
[7,8,10,11]
NRST [4,5,10,11]
G125CK
GTX0GTX1GTX2GTX3
GRX0GRX1
GRX2GRX3
GTXCK
GTX_CTL
GRXCK
GRX_CTL
GMDC
GMDIOINT_GETHR
10Base-T/100Base-TX/1000BASE-T
R64
4.7K
R64
4.7K
R68 22RR68 22R
+ C12710uF
+ C12710uF
C112 20pFC112 20pF
R61 1KR61 1K
C12010nFC12010nF
R67
4.7K
R67
4.7K
C13610nFC13610nF
+ C11310uF
+ C11310uF
Y325MHz
Y325MHz
123 4
C12110nFC12110nF
C13510nFC13510nF
C12910nFC12910nF
+ C12610uF
+ C12610uF
C116 20pFC116 20pF
R694.7KR694.7K
C11910nFC11910nF
L17180ohm at 100MHz
L17180ohm at 100MHz
1 2
C12210nFC12210nF
C11510nFC11510nF
R65
4.7K
R65
4.7K
C13410nFC13410nF
C12810nFC12810nF
C11810nFC11810nF
C11410nFC11410nF
C13310nFC13310nF
C12310nFC12310nF
KSZ9031RNI48-pin QFN
MN10KSZ9031RN
KSZ9031RNI48-pin QFN
MN10KSZ9031RN
VSS_
PS13
LED
215
DVD
DH
16LE
D1
17
DVD
DL
14
TXD
019
TXD
120
TXD
221
TXD
322
DVD
DL
18
DVD
DL
23G
TX_C
LK24
TX_EN 25DVDDL 26RXD3 27
VSS 29DVDDL 30RXD1 31RXD0 32RX_DV 33DVDDH 34RX_CLK 35MDC 36
MD
IO37
INT_
N38
DVD
DL
39D
VDD
H40
CLK
125_
ND
O41
RES
ET_N
42LD
O_O
43
XO45
XI46
AVD
DH
47IS
ET48
AVDDH1TXRXP_A2TXRXM_A3
TXRXP_B5TXRXM_B6TXRXP_C7TXRXM_C8
TXRXP_D10TXRXM_D11AVDDH12
RXD2 28
AVD
DL_
PLL
44
P_G
ND
49
AVDDL4
AVDDL9
R66
4.7K
R66
4.7K
R63 12.1K 1%R63 12.1K 1%
C13810nFC13810nF
R60 4.7KR60 4.7K
+ C11710uF
+ C11710uF
C13710nFC13710nF R70 22RR70 22R
+ C13210uF
+ C13210uF
R62 22RR62 22R
EARTH_ETH0ETH0_GND
R73 0RR73 0RL18 180ohm at 100MHzL18 180ohm at 100MHz1 2
ETH0_B+ETH0_B-
ETH0_D+ETH0_D-
ETH0_A+ETH0_A-
ETH0_C+ETH0_C-
ETH0_LED1
ETH0_LED2
AVDDH
VDDIOP1
EARTH_ETH0
ETH0_GND
LINK
ACT
Left Green LED
Right Yellow LED
C124100nFC124100nF
R71
470R
R71
470R
J12
48F-01GY2DPL2NL
J12
48F-01GY2DPL2NL
TD2+3
TD1+1TD1-2
TD3+7TD3-8
RCT6
TD2-4
GRLA 11GRLC 12
TD4+9TD4-10
TCT5
YELC 13YELA 14
GND 15GND 16GND 17GND 18
R72
470R
R72
470R
R111 DNP(0R)R111 DNP(0R)
C125
DNP(10uF 0805)
C125
DNP(10uF 0805)
DS50002884A-page 16 2019 Microchip Technology Inc.
SAMA5D3 XPLAINED
4.2.10 Ethernet 10/100 Port
The SAMA5D3 Xplained board features a MICREL PHY device (KSZ8081RNB) operating at 10/100 Mb/s. The board supports RMII inter-face modes. The Ethernet interface consists of two pairs of low-voltage differential pair signals designated from GRX± and GTX± plusControl signals for link activity indicators. These signals are routed to the 10/100BASE-T RJ45 connector (J13).
For monitoring and control purposes, an LED functionality is added on the RJ45 connectors to indicate activity, link, and speed statusinformation for the corresponding ports.
For more information about the Ethernet controller device, refer to the MICREL KSZ8081RNB controller manufacturer's data sheet.
Figure 4-13: RMII Ethernet Schematic
4.2.11 Indicators
Two LEDs are available on the SAMA5D3 Xplained board. Both can be software-controlled by the user.
• The red LED indicates that power is applied to the board (by default). It can be controlled via software.• The blue LED is mainly controlled by one GPIO line.
Figure 4-14: LED Indicators Schematic
ETH1_XO
ETH1_XI
ETH1_XO
ETH1_XI
ETH1_LED0
ETH1_LED0
TX+TX+
TX-
RX+
RX-RX-
RX+
TX-
ETH1_LED1ETH1_LED1
VDDIOP1 VDDIOP0
VDDIOP0E1_AVDDT
VDDIOP0
EARTH_ETH1EARTH_ETH1
GND_ETH1
VDDIOP0
EARTH_ETH1GND_ETH1
VDDIOP0
NRST [4,5,9,11]
ETH1_PC2 [7]ETH1_PC3 [7]
ETH1_PC0 [7]
ETH1_PC5 [7]ETH1_PC6 [7]
ETH1_PC7 [7]
ETH1_PC4 [7]
ETH1_PC8 [7]ETH1_PC9 [7]PB12 [7]
ETH1_PC1 [7]
10Base-T/100Base-TX
ACT
LINK
+ C14810uF
+ C14810uF
L19
180ohm at 100MHz
L19
180ohm at 100MHz1 2
MN9
KSZ8081RNB
MN9
KSZ8081RNB
RXC/B-CAST_OFF 19
CRS/CONFIG1 29COL/CONFIG0 28
TXD1 25TXD0 24TXEN 23
RXD3/PHYAD0 13RXD2/PHYAD1 14RXD1/PHYAD2 15RXD0/DUPLEX 16
RXDV/CONFIG2 18RXER/ISO 20
MDC 12MDIO 11
INTRP/NAND 21
VDDA_3V3 3
VDDIO 17
RESET 32
TXP7
TXM6
RXP5
RXM4
VDD_1V22
GND1PADDLE33TXC22TXD226TXD327REXT10
XO8
XI9
LED0/NWAYEN30LED1/SPEED31
R11
610
KR
116
10K
+ C14610uF
+ C14610uF
R12
010
KR
120
10K+ C144
10uF+ C144
10uF
C139100nFC139100nF
R11
410
KR
114
10K
R11
510
KR
115
10K
C147 20pFC147 20pF
C140100nFC140100nF C141 2.2uFC141 2.2uF
R79 470RR79 470R
Y425MHz
Y425MHz
123 4
C142 100nFC142 100nF
R80 470RR80 470R
C149
20pF
C149
20pF
R766.49k/1% R766.49k/1% C143100nFC143100nF
R75
1K
R75
1K
C145100nFC145100nF
R74
1K
R74
1K
R11
310
KR
113
10K
R81 0RR81 0R
R7810KR78
10K
L20180ohm at 100MHz
L20180ohm at 100MHz
1 2
R7710KR77
10K
R11
710
KR
117
10K
R11
810
KR
118
10K
1
2
3
6
4
5
7
8
75
75
75 75
1nF
TD+
TD-
CT
NC
RD-
CT
TX+
TX-
RX+
RX-
RD+
Left Green LED Right yellow LED
J1313F-64GYD2PL2NL
1
2
3
6
4
5
7
8
75
75
75 75
1nF
TD+
TD-
CT
NC
RD-
CT
TX+
TX-
RX+
RX-
RD+
Left Green LED Right yellow LED
J1313F-64GYD2PL2NL
1
2
7
8
3
6
5
4
9101112
1314
1516
R11
910
KR
119
10K
PE23
PE24
3V3
PE[0..31][4,7,8,11]
LEDD3
RED
D3
RED
R34470RR34470R
R33 100K 1%R33 100K 1%
Q2IRLML2502Q2IRLML2502
1
32
R32470RR32470R
D2
BLUE
D2
BLUE
2019 Microchip Technology Inc. DS50002884A-page 17
SAMA5D3 XPLAINED
4.2.12 USB
The SAMA5D3 Xplained board features three USB communication ports:
• Port A: High-speed (EHCI) and full-speed (OHCI) host multiplexed with high-speed USB device Micro-AB connector (J6)• Port B: High-speed (EHCI) and full-speed (OHCI) host, standard type A connector (J7 upper port)• Port C: Full-speed OHCI host, standard type A connector (J7 lower port)
The two USB host ports are equipped with 500-mA high-side power switch for self-powered and bus-powered applications.
The USB device port A (J6) features a VBUS insert detection function through the ladder-type resistors R26 and R27.
Figure 4-15: USB Interface Schematic
4.2.13 Push Button Switches
The following push button switches are available:
• One board reset button (BP2). When pressed and released, this push button causes a Power-on Reset of the whole board.• One wake-up push button that brings the processor out of Low-Power mode (BP1)• One user push button (BP3)
Figure 4-16: Push Button Schematic
HHSDPC
HHSDMAHHSDPA
HHSDMBHHSDPB
HHSDMC
HHSDMCHHSDPC
HHSDMBHHSDPB
5V_USBB 5V_USBC
5V_USBB
5V_USBC
GNDUTMIGNDUTMI
EARTH_USB
5V_MAIN
EARTH_USB
EARTH_USB_A
PE5 [7]
Vbus[4]
PE9[7,11]
PE4 [7]
PE3 [7]
OVCUR_USB
USB A DEVICE INTERFACE
(VBUS_SENSE)
J7_USB_A_Up J7_USB_B_DownEN5V_USBC
EN5V_USBB
C6010pFC6010pF
32.768KY2Y2
11233 44
R27200KR27200K
C5C533 20pF20pFpp
MN3
SP2526A-2E
MN3
SP2526A-2E
ENA 1
FLGA 2
ENB 4
OUTA8
GNG6 FLGB 3
IN7
OUTB5
J6UBAF-1015PJ6UBAF-1015P
MN2HSAMA5D3x_BGA324
MN2HSAMA5D3x_BGA324
GN
DC
OR
E_1
AA1166
GN
DC
OR
E_2
CC99
GN
DIO
DD
R_1
EE1144
GN
DIO
DD
R_2
F10
F10
GN
DIO
DD
R_3
F13
F13
GN
DIO
DD
R_4
F15
F15
GN
DIO
DD
R_5
H1
H144
GN
DIO
P_1
JJ77
GN
DIO
M_1
J1J111
GN
DA
NA
L4
ADVREF
VDDANA
GN
DIO
P_2
N1
N111
GN
DC
OR
E_3
N1
N133
GN
DFU
SE
PP44
GN
DP
LLPP
1100
GN
DU
TMI_
1R
12
VDDPLLA
VBGR11
GN
DC
OR
E_4
T8T8
GN
DO
SC
T11
T11
GN
DB
UT1
3T1
3
GN
DC
OR
E_5
T14
T14
GN
DIO
M_2
T17
T17
GN
DIO
P_3
UU77
VDDOSC
VDDUTMII
XIN32U16
XOUTV8
VDDUTMIC
XOUT32V16
GN
DC
OR
E_6
VV1177
GN
DIO
P_4
EE55
HHSDMAV10HHSDPAU10
HHSDMCV14HHSDPCU14
HHSDPBU12 HHSDMBV12
DIBNU6DIBPV6
C61100nFC61100nF
L21 180ohm at 100MHzL21 180ohm at 100MHz1 2
C5C566 20pF20pF
12MHz
333 4444
C64100nFC64100nF
R305.62K 1%R305.62K 1%
L13180ohm at 100MHz
L13180ohm at 100MHz
1 2
C6210uFC6210uF C63
100nFC63100nF
L15180ohm at 100MHz
L15180ohm at 100MHz
1 2
A
B
J7Dual USB A
A
B
J7Dual USB A
5
8
67
9 10
1234
1112
R31 0RR31 0R
C5C511 20pF20pFpp
L14180ohm at 100MHz
L14180ohm at 100MHz
1 2
C6510uFC6510uF
R26 100K 1%R26 100K 1%
33333333333
EARTH_USB_A
VBUSDMDPID
GND
VBUSDMDPID
GND
12345
76
8
BP2
BP1
RESETWAKUP or Force Power ON
AutoPWRON(option)
R1450KR1450K
BP2BP2
C20100nFC20100nF
GN
DP
129
GN
DA
2
GN
DP
228
REFBP32
nPBIN9
Q1
IRLML2502
Q1
IRLML2502
1
3
2R19
100K 1%
R19
100K 1%
R150RR150R
C1847nFC1847nF
C25100nF
C25100nF
R12 49.9K
C13010nFC13010nF
BP1BP1
PE29[7,11]
Place TP5 to Bottom
BP3BP3
TP5SMDTP5SMD
USER BUTTON
DS50002884A-page 18 2019 Microchip Technology Inc.
SAMA5D3 XPLAINED
4.2.14 LCD
The SAMA5D36 processor drives 24 bits of Data and Control signals to the LCD interface. Other signals are used to control the LCD andare also routed to the J22 connector: TWI, SPI, 2 GPIOs for interrupt, ID for 1-Wire EEPROM (ID_SYS) and power supply lines.
4.2.14.1 LCD Connector
One 1.27 mm pitch 50-pin header is provided to gain access to the LCD signals.
Figure 4-17: LCD Expansion Header Interface Schematic
4.2.14.2 LCD Power
To operate correctly with various LCD modules, regardless of the processor, two voltage lines are available: 3V3 by default and 5V_MAIN,both selected by 0R resistors R92 and R93.
4.2.15 Debug JTAG/ICE and DBGU
4.2.15.1 Debug JTAG/ICE
A 2x10-pin JTAG header is implemented on the SAMA5D3 Xplained board to enable the software development and debugging of theboard by using various JTAG emulators. The interface signals have a voltage level of 3.3V.
PA0PA1PA2PA3
PA4PA5PA6PA7
PA8PA9PA10PA11
PA15PA14PA13PA12
PA25
PA24
PC13PC12PC11
PC14
PC10PC15PE27PE28
PA29PA27PA26
PE8PE7
TWD_LCDTWCK_LCD
PE23
PD10
PD11
PD12
PD16
PD20
PD21
PD22
PD23
PE6NRST
TWCK_LCDTWD_LCD
PA28
3V35V_MAIN
TWCK_LCD[7]TWD_LCD[7]
LCD Connector
(ID_SYS)
(SPI0_SPCK)
(SPI0_MOSI)
(SPI0_MISO)
(SPI0_NPCS3)
(AD0)
(AD1)
(AD2)
(AD3)
(RST_LCD)
(LCDDAT0)(LCDDAT1)(LCDDAT2)(LCDDAT3)
(LCDDAT4)(LCDDAT5)(LCDDAT6)(LCDDAT7)
(LCDDAT8)(LCDDAT9)(LCDDAT10)(LCDDAT11)
(LCDDAT12)(LCDDAT13)(LCDDAT14)(LCDDAT15)
(LCDDAT16)(LCDDAT17)(LCDDAT18)(LCDDAT19)
(LCDDAT20)(LCDDAT21)(LCDDAT22)(LCDDAT23)(LCDPCK)
(LCDVSYNC)(LCDHSYNC)(LCDDEN)
(LCDDISP)
(LCDPWM)(IRQ2)IRQ1)
R101 22RR101 22R
R103 22RR103 22R
R93 0RR93 0R
R102 DNP(0R)R102 DNP(0R)
R100 DNP(0R)R100 DNP(0R)
R184 22RR184 22R
R99 DNP(0R)R99 DNP(0R)
J22J22
FP520T1-50SR04
1234567891011121314151617181920212223242526272829303132333435363738394041424344454647484950
5251
R92 DNP(0R)R92 DNP(0R)
R94 0RR94 0R
R96 22RR96 22R
R98 DNP(0R)R98 DNP(0R)
R97 22RR97 22R
R95 DNP(0R)R95 DNP(0R)
SeeErrata section
2019 Microchip Technology Inc. DS50002884A-page 19
SAMA5D3 XPLAINED
Figure 4-18: JTAG/ICE Interface Schematic
4.2.15.2 DBGU
The SAMA5D3 Xplained board has a dedicated serial port for debugging, which is accessible through the 6-pin male header J23. Variousinterfaces can be used as USB/Serial DBGU port bridge, such as FTDI TTL-232R-3V3 USB to TTL serial cable or basic breakout boardfor the 232/USB converter.
These interfaces are available on the following websites:
• Adafruit: http://www.adafruit.com/products/284• Sparkfun: https://www.sparkfun.com/products/9873
Figure 4-19: DBGU Interface Schematic
R171 and R172 are optional (not implemented) resistors that can be used for power selection. Power can be delivered either by theSAMA5D3 Xplained board or by the debug interface tool. To avoid a contention between your debug interface (e.g. FTDI) and the on-board power system, be careful during the installation of one of these resistors.
4.2.16 Expansion Ports
Five 8-pin, one 10-pin, one 6-pin and one 2x18-pin headers (J14 to J21) are implemented on the board to enable the PIO connection ofvarious expansion cards that could be developed by users or by other sources. Due to multiplexing, different signals can be provided oneach pin. These connectors are mechanically- and footprint- compatible with the Arduino R3 shields. As the SAMA5D3 signals have avoltage level of 3.3V, 5-V level shields must not be used on the SAMA5D3 Xplained.
In addition to its standard IO functionality, the SAMA5D3 processor can provide alternate functions to external IO lines available on theJ14 to J21 headers.
These alternate functions are:
• UARTs: UART0, UART1• USARTs: USART0, USART1, USART2, USART3 • SPI: SPI1
TCKTMS
RTCK
TDI
TDO
3V3
VDDIOP0
NRST [4,5,9,10]TDO [5]
TDI [5]
TCK [5]TMS [5]
NTRST [5]
JTAG
R106100K 1%R106100K 1%
J24J2412345678910111213151719
14161820
R105100K 1%R105100K 1%
R108 0RR108 0R
R104100K 1%R104100K 1%
R109 0RR109 0R
R107100K 1%R107100K 1%
R110 0RR110 0R
DEBUG(TXD)(RXD)
PE13
PE14
5V_MAIN3V33V3
PB31[7]PB30[7]
R19
068
K
J23
P101-1*06SGF-116A-NX
123456
R173 0R
R17
1D
NP
(0R
)
R174 0R
R18
968
K
R17
2D
NP
(0R
)
DS50002884A-page 20 2019 Microchip Technology Inc.
SAMA5D3 XPLAINED
• I²C: TWI0, TWI1• Timer capture and compare: TIOA, TIOB• Clock out: PCK0, PCK1, PCK2• PWMs: PWML0, PWMH0, PWML1, PWMH1• DIGITAL AUDIO: TD0, TK0, TF0, RD0, RK0, RF0• ISI: ISI[D0:D11], ISI_HSYNC, ISI_VSYNC, ISI_PCK• CAN: CAN-RX0, CANTX0, CANRX1, CAN_TX1• Analog: AD[0:11], ADTRG, ADREF• GPIO: MISC• RESET• VBAT
Refer to the SAMA5D3 series data sheet for further details on the PIO multiplexing and alternate function selection.
2019 Microchip Technology Inc. DS50002884A-page 21
SAMA5D3 XPLAINED
4.2.16.1 Functions Available Through the Arduino Headers
The following tables illustrate the functionalities provided by the SAMA5D3 Xplained board. They show the pins used to implement eachfunctionality.
Note: Some pins are multiplexed for different functionalities, which means that only one at a time can be active for each pin.
Table 4-5: Function by PIO (Part 1)
PIO NAME PCK ISI SSC CAN SPI
PC16 -- -- TK0 -- --
PC17 -- -- TF0 -- --
PC18 -- -- TD0 -- --
PC20/PD28 -- -- RF0 -- --
PC21/PD29 -- -- RD0 -- --
PC19/PD30 PCK0 -- RK0 -- --
PD30/PC15 PCK0/PCK2 -- -- -- --
PD31 PCK1 -- -- -- --
PB14 -- -- -- CANRX1 --
PD14 -- -- -- CANRX0 --
PB15 -- -- -- CANTX1 --
PD15 -- -- -- CANTX0 --
PC22/PC1 -- -- -- -- SPI1_MISO
PC24/PC0 -- -- -- -- SPI1_SPCK
PC23/PC2 -- -- -- -- SPI1_MOSI
PC25 -- -- -- -- SPI1_NPCS0
PC26/PA30 -- ISI_D11/VSYNC -- -- SPI1_NPCS1
PC27/PA31 -- ISI_D10/HSYNC -- -- SPI1_NPCS2
PC28 -- ISI_D9 -- -- SPI1_NPCS3
PC29 -- ISI_D8 -- -- --
PA23 -- ISI_D7 -- -- --
PA22 -- ISI_D6 -- -- --
PA21 -- ISI_D5 -- -- --
PA20 -- ISI_D4 -- -- --
PA19 -- ISI_D3 -- -- --
PA18 -- ISI_D2 -- -- --
PA17 -- ISI_D1 -- -- --
PA16 -- ISI_D0 -- -- --
PC30 -- ISI_PCK -- -- --
PA30 -- ISI_VSYNC -- -- --
PA31 -- ISI_HSYNC -- -- --
DS50002884A-page 22 2019 Microchip Technology Inc.
SAMA5D3 XPLAINED
Table 4-6: Function by PIO (Part 2)
PIO NAME TWI UART/USART ANALOG MISC
3V3/5V -- -- -- 3V3/5V
nRTS -- -- -- nRTS
GND -- -- -- GND
AREF -- -- AREF --
5V -- -- -- 5V
PC18 -- -- AD0 --
PD21 -- -- AD1 --
PD22 -- -- AD2 --
PD23 -- -- AD3 --
PD24 -- -- AD4 --
PD25 -- -- AD5 --
PD26 -- -- AD6 --
PD27 -- -- AD7 --
PC20/PD28 -- -- AD8 --
PC21/PD29 -- -- AD9 --
PC19/PD30 -- -- AD10 --
PD31 -- -- AD11 --
PD19/PB15 -- -- ADTRG --
PA19 TWCK2 -- -- --
PA18 TWD2 -- -- --
PC26 TWD1 -- -- --
PA30 TWD0 URXD1 -- --
PA31 TWCK0 UTXD1 -- --
PC26/PA30 TWD0/TWD1 URXD1 -- --
PC27/PA31 TWCK0/TWCK1 URTD1 -- --
PC30 -- UTXD0 -- --
PC29 -- URXD0 -- PWMFI2
PD14 -- SCK0 -- --
PD15 -- CTS0 -- --
PD18 -- TXD0 -- --
PD17 -- RXD0 -- --
PB25 -- SCK1 -- --
PB26 -- CTS1 -- --
PB29 -- TXD1 -- --
PB28 -- RXD1 -- --
2019 Microchip Technology Inc. DS50002884A-page 23
SAMA5D3 XPLAINED
PB27 -- RTS1 -- PWMH1
PE20 -- SCK2 -- --
PE23 -- CTS2 -- --
PE26 -- TXD2 -- --
PE25 -- RXD2 -- --
PE24 -- RTS2 -- --
PE15 -- SCK3 -- --
PE16 -- CTS3 -- --
PE19 -- TXD3 -- --
PE18 -- RXD3 -- --
PE17 -- RTS3 -- --
PC22/PC1 -- -- -- GPIO
PC23/PC2 -- -- -- GPIO
PC24/PC0 -- -- -- GPIO
PC9 -- -- -- GPIO
PE9 -- -- -- GPIO
PE10 -- -- -- GPIO
PE11 -- -- -- GPIO
PE12 -- -- -- GPIO
PE16 -- -- -- GPIO
PE31 -- -- -- IRQ/PWML1
PC28 -- -- -- PWMFI0
PA20 -- -- -- PWMH0
PA22 -- -- -- PWMH1
PA21 -- -- -- PWML0
PA23 -- -- -- PWML1
PE29 -- -- -- TCLK2
PC5 -- -- -- TCLK4
PC8 -- -- -- TCLK5
PC3 -- -- -- TIOA4
PC6 -- -- -- TIOA5
PC4 -- -- -- TIOB4
PC7 -- -- -- TIOB5
Table 4-6: Function by PIO (Part 2) (Continued)
PIO NAME TWI UART/USART ANALOG MISC
DS50002884A-page 24 2019 Microchip Technology Inc.
SAMA5D3 XPLAINED
4.2.16.2 J15 Header
Figure 4-20: J15 Header
Table 4-7: J15 Header IOs
Silkscreen PIO Function 1 Function 2 Function 3 PIO Function 4 Function 5
SCL0 PA31 TWCK0 UTXD1 ISI_HSYNC -- -- --
SDA0 PA30 TWD0 URXD1 ISI_VSYNC -- -- --
ARFE -- -- -- -- -- -- --
GND -- -- -- -- -- -- --
13 PC24 SPI1_SPCK -- -- PC0 ETX0 TIOA3
12 PC22 SPI1_MISO -- -- PC1 ETX1 TIOB3
11 PC23 SPI1_MOSI -- -- PC2 ERX0 TCLK3
10 PC25 SPI1_NPCS0 -- -- -- -- --
9 PC3 ERX1 TIOA4 -- -- -- --
8 PC4 ETXEN TIOB4 -- -- -- --
2019 Microchip Technology Inc. DS50002884A-page 25
SAMA5D3 XPLAINED
4.2.16.3 J18 Header
Figure 4-21: J18 Header
Table 4-8: J18 Header IOs
Silkscreen PIO Function 1 Function 2 Function 3
7 PC5 ECRSDV TCLK4 --
6 PC6 ERXER TIOA5 --
5 PC7 EREFCK TIOB5 --
4 PC28 SPI1_NPCS3 PWMFI0 ISI_D9
3 PC8 EMDC TCLK5 --
2 PC9 EMDIO -- --
1 PC30 UTXD0 ISI_PCK --
0 PC29 URXD0 PWMFI2 ISI_D8
DS50002884A-page 26 2019 Microchip Technology Inc.
SAMA5D3 XPLAINED
4.2.16.4 J20 Header
Figure 4-22: J20 Header
Table 4-9: J20 Header IOs
Silkscreen PIO Function 1 Function 2 Function 3 PIO Function 4 Function 5 Function 6
TXD3 14 PE19 A19 TXD3 -- -- -- -- --
RXD3 15 PE18 A18 RXD3 -- -- -- -- --
TXD1 16 PB29 TXD1 -- -- -- -- -- --
RXD1 17 PB28 RXD1 -- -- -- -- -- --
TXD0 18 PD18 TXD0 -- -- -- -- -- --
RXD0 19 PD17 RXD0 -- -- -- -- -- --
SDA 20 PC26 SPI1_NPCS1 TXWD1 ISI_D11 PA30 TWD0 URXD1 ISI_VSYNC
SCL 21 PC27 SPI1_NPCS2 TWCK1 ISI_D10 PA31 TWCK0 UTXD1 ISI_HSYNC
2019 Microchip Technology Inc. DS50002884A-page 27
SAMA5D3 XPLAINED
4.2.16.5 J19 Header
Figure 4-23: J19 Header
Table 4-10: J19 Header IOs
Silkscreen PIO Function 1 Function 2 Function 3 PIO Function 4 Function 5
PD30 PD30 AD10 PCK0 -- PC15 PCI2_CK PCK2
PC17 PC17 TF0 -- -- -- -- --
PB26 PB26 CTS1 GRX7 -- -- -- --
PE9 PE9 A9 -- -- -- -- --
PA17 PA17 LCDDAT17 ISI_D1 -- -- -- --
PA19 PA19 LCDDAT19 TWCk2 ISI_D3 -- -- --
PA21 PA21 LCDDAT21 PWML0 ISI_D5 -- -- --
PA23 PA23 LCDDAT23 PWML1 ISI_D7 -- -- --
PE15 PE15 A15 SCK3 -- -- -- --
PE17 PE17 A17 RTS3 -- -- -- --
PE11 PE11 A11 -- -- -- -- --
PE23 PE23 A23 CTS2 -- -- -- --
PE25 PE25 A25 RXD2 -- -- -- --
DS50002884A-page 28 2019 Microchip Technology Inc.
SAMA5D3 XPLAINED
PE13 PE13 A13 -- -- -- -- --
PE29 PE29 NWR1/NBS1 TCLK2 -- -- -- --
PC26 PC26 SPI1_NPCS1 TXWD1 ISI_D11 -- -- --
PC16 PC16 TK0 -- -- -- -- --
PB25 PB25 SCK1 GRX6 -- -- -- --
PB27 PB27 RTS1 PWMH1 -- -- -- --
PE10 PE10 A10 -- -- -- -- --
PA16 PA16 LCDDAT16 ISI_D0 -- -- -- --
PA18 PA18 LCDDAT18 TWD2 ISI_D2 -- -- --
PA20 PA20 LCDDAT20 PWMH0 ISI_D4 -- -- --
PA22 PA22 LCDDAT22 PWMH1 ISI_D6 -- -- --
PE16 PE16 A16 CTS3 -- -- -- --
PE20 PE20 A20 SCK2 -- -- -- --
PE12 PE12 A12 -- -- -- -- --
PE24 PE24 A24 RTS2 -- -- -- --
PE26 PE26 NCS0 TXD2 -- -- -- --
PE14 PE14 A14 -- -- -- -- --
PE31 PE31 IRQ PWML1 -- -- -- --
PB15 PB15 GCOL CANTX1 -- -- -- --
Table 4-10: J19 Header IOs (Continued)
Silkscreen PIO Function 1 Function 2 Function 3 PIO Function 4 Function 5
2019 Microchip Technology Inc. DS50002884A-page 29
SAMA5D3 XPLAINED
4.2.16.6 J16 Header
Figure 4-24: J16 Header
Table 4-11: J16 Header IOs
Silkscreen PIO Function 1
MISO1 PC22 SPI1_MISO
5V/3V3 -- Power supply
SPCK PC24 SPI1_SPCK
MOSI1 PC23 SPI1_MOSI
RST NRST System reset
GND -- Power ground
DS50002884A-page 30 2019 Microchip Technology Inc.
SAMA5D3 XPLAINED
4.2.16.7 J14 Header
Figure 4-25: J14 Header Position
Table 4-12: J14 Header IOs
Silkscreen Function
VBAT VBAT supply
3V3 AREF. Reference voltage for the analog inputs of the SAMA5D36 processor.
RST System reset
3V3Main 3.3V supply - generated by the on-board regulator. Maximum sourced current is 1.2A. This regulator also provides the power supply to the SAMA5D36 microcontroller and components.
5V Main 5.0V supply
GND System ground
GND System ground
NC Not connected
2019 Microchip Technology Inc. DS50002884A-page 31
SAMA5D3 XPLAINED
4.2.16.8 J17 Header
Figure 4-26: J17 Header
Table 4-13: J17 Header IOs
Silkscreen PIO Function 1 Function 2 Function 3 PIO Function 4 Function 5
A0 PC18 TD0 -- -- PD20 AD0 --
A1 PD21 AD1 -- -- -- -- --
A2 PD22 AD2 -- -- -- -- --
A3 PD23 AD3 -- -- -- -- --
A4 PD24 AD4 -- -- -- -- --
A5 PD25 AD5 -- -- -- -- --
A6 PD26 AD6 -- -- -- -- --
A7 PD27 AD7 -- -- -- -- --
DS50002884A-page 32 2019 Microchip Technology Inc.
SAMA5D3 XPLAINED
4.2.16.9 J21 Header
Figure 4-27: J21 Header
Table 4-14: J21 Header IO
Silkscreen PIO Function 1 Function 2 Function 3 PIO Function 4 Function 5
A8 PC20 RF0 -- -- PD28 AD8 --
A9 PC21 RD0 -- -- PD29 AD9 --
A10 PC19 RK0 -- -- PD30 AD10 PCK0
A11 PD31 PCK1 -- -- -- -- --
** PB14 GCRS CANRX1 -- -- -- --
** PD19 ADTRG -- -- PB15 GCOL CANTX1
CANRX0 PD14 SCK0 SPO_NPCS1 CANRX0 -- -- --
CANTX0 PD15 CTS0 SPI0_NPCS2 CANTX0 -- -- --
2019 Microchip Technology Inc. DS50002884A-page 33
SAMA5D3 XPLAINED
4.3 Other Connector Details and PIO Usage Summary
4.3.1 Power Supply
Figure 4-28: Power Supply Connector J2 (Optional)
4.3.2 JTAG/ICE Connector
Figure 4-29: JTAG Port J24
Table 4-15: Power Supply Connector J2 Signal Description
Pin Mnemonic Signal Description
1 Center +5V
2 -- GND
3 -- Floating
Table 4-16: JTAG/ICE Connector J24 Signal Descriptions
Pin Mnemonic Signal Description
1 VTref 3.3V power
This is the target reference voltage. It is used to check if the target has power, to create the logic-level reference for the input comparators and to control the output logic levels to the target. It is normally fed from VDD on the target board and must not have a series resistor.
2 Vsupply 3.3V powerThis pin is not connected in SAM-ICE™. It is reserved for compatibility with other equipment. Connect to VDD or leave open in target system.
3nTRST Target Reset - Active-low Output signal that resets the target.
JTAG Reset. Output from SAM-ICE to the Reset signal on the target JTAG port. Typically connected to nTRST on the target CPU. This pin is normally pulled high on the target to avoid unintentional resets when there is no connection.
4 GND Common ground.
1 3 5 7 9 11 13 15 17 19
2 4 6 8 10 12 14 16 18 20
DS50002884A-page 34 2019 Microchip Technology Inc.
SAMA5D3 XPLAINED
4.3.3 USB Type-A Dual Port
Figure 4-30: USB Type-A Dual Port J19
5TDI Test Data Input - Serial data output line, sampled on the rising edge of the TCK signal.
JTAG data input of target CPU. It is recommended that this pin is pulled to a defined state on the target board. Typically connected to TDI on target CPU.
6 GND Common ground.
7 TMS Test Mode Select.
JTAG mode set input of target CPU. This pin should be pulled up on the target. Typically connected to TMS on target CPU. Output signal that sequences the target's JTAG state machine, sampled on the rising edge of the TCK signal.
8 GND Common ground.
9TCK Test Clock - Output Timing signal, for synchronizing test logic and control register access.
JTAG Clock signal to target CPU. It is recommended that this pin is pulled to a defined state on the target board. Typically connected to TCK on target CPU.
10 GND Common ground.
11RTCK - Input Return Test Clock signal from the target.
Some targets must synchronize the JTAG inputs to internal clocks. To fulfill this requirement, a returned and resynchronized TCK can be used to dynamically control the TCK rate. SAM-ICE supports adaptive clocking which waits for TCK changes to be echoed correctly before making further changes. Connect to RTCK if available, otherwise to GND.
12 GND Common ground.
13TDO JTAG Test Data Output - Serial data input from the target.
JTAG data output from target CPU. Typically connected to TDO on target CPU.
14 GND Common ground
15 nSRST RESET Active-Low Reset signal. Target CPU Reset signal.
16 GND Common ground
17 RFU This pin is not connected.
18 GND Common ground
19 RFU This pin is not connected.
20 GND Common ground
Table 4-16: JTAG/ICE Connector J24 Signal Descriptions (Continued)
Pin Mnemonic Signal Description
2019 Microchip Technology Inc. DS50002884A-page 35
SAMA5D3 XPLAINED
-
4.3.4 USB Micro-AB
Figure 4-31: USB Host/Device Micro-AB Connector J6
Table 4-17: USB Type-A Dual Port J19 Signal Descriptions
Pin Mnemonic Signal Description
A1 Vbus - USB_A 5V power
A2 DM - USB_A Data minus
A3 DP - USB_A Data plus
A4 GND Common ground
B1 Vbus - USB_A 5V power
B2 DM - USB_A Data minus
B3 DP - USB_A Data plus
B4 GND Common ground
Mechanical pins
-- Shield
Table 4-18: USB Device Micro-AB Connector J6 Signal Descriptions
Pin Mnemonic Signal Description
1 Vbus 5V power
2 DM Data minus
3 DP Data plus
4 ID On-the-go identification
5 GND Common ground
1 2 3 4 5
DS50002884A-page 36 2019 Microchip Technology Inc.
SAMA5D3 XPLAINED
4.3.5 DEBUG Connector
Figure 4-32: DEBUG Connector J23
4.3.6 SD/MMC Plus MCI0
Figure 4-33: SD/MMC Socket J10
Table 4-19: DEBUG Connector J23 Signal Descriptions
Pin Mnemonic PIO Signal Description
1 -- PE13 --
2 TXD (transmitted data) PB31 RS232 Serial Data Input signal
3 RXD (transmitted data) PB30 RS232 Serial Data Output signal
4 -- -- Power line (5V/3V3)
5 -- PE14 --
6 GND -- Common ground
Table 4-20: SD/MMC Socket J10 Signal Descriptions
Pin Mnemonic PIO Signal Description
1 DAT3 PD4 Data bit
2 CMD PD0 Command line
3 VSS -- Command line
4 VCC -- Supply voltage 3.3V
5 CLK PD9 Clock / command line
6 CD PE0 Card detect
7 DAT0 PD1 Data bit
8 DAT1 PD2 Data bit
9 DAT2 PD3 Data bit
10 DAT4 PD5 Data bit
11 DAT5 PD6 Data bit
12 DAT6 PD7 Data bit
13 DAT7 PD8 Data bit
2019 Microchip Technology Inc. DS50002884A-page 37
SAMA5D3 XPLAINED
4.3.7 MicroSD MCI1
Figure 4-34: MicroSD Socket J11
4.3.8 Gigabit Ethernet ETH0 RJ45 Socket J12
Figure 4-35: Gigabit Ethernet RJ45 Socket J12
14 WP R57 Protect
15 VSS -- Common ground
16 VSS -- Common ground
Table 4-21: MicroSD Socket J11 Signal Descriptions
Pin Mnemonic PIO Signal Description
1 DAT2 PB22 Data bit 2
2 CD/DAT3 PB23 Card detect / data bit 3
3 CMD PB19 Command line
4 VCC -- Supply voltage 3.3V
5 CLK PB24 Clock / command line
6 VSS -- Common ground
7 DAT0 PB20 Data bit 0
8 DAT1 PB21 Data bit 1
9 SW1 -- Not used, grounded
10 CARD DETECT PE1 Card detect
Table 4-20: SD/MMC Socket J10 Signal Descriptions
Pin Mnemonic PIO Signal Description
1 2 3 4 5 6 7 8
RJ-45
DS50002884A-page 38 2019 Microchip Technology Inc.
SAMA5D3 XPLAINED
4.3.9 Ethernet ETH1 RJ45 Socket J13
Figure 4-36: Ethernet RJ45 Socket J13
4.3.10 LCD Socket J22
Figure 4-37: LCD Socket J22
Table 4-22: LCD Socket J22 Signal Descriptions
PIN Signal Display Module Interface Function MCU Interface Function
1 ID_SYSExtension module identification (connected to 1-wire EEPROM available on LCD display module)
Extension module identification
2 GND GND GND
3 D0 Data line Data line
4 D1 Data line Data line
5 D2 Data line Data line
6 D3 Data line Data line
7 GND GND GND
8 D4 Data line Data line
9 D5 Data line Data line
10 D6 Data line Data line
11 D7 Data line Data line
12 GND GND GND
13 D8 Data line Data line
14 D9 Data line Data line
15 D10 Data line Data line
16 D11 Data line Data line
17 GND GND GND
18 D12 Data line Data line
1 2 3 4 5 6 7 8
RJ-45
2019 Microchip Technology Inc. DS50002884A-page 39
SAMA5D3 XPLAINED
Note 1: See Section 5. “Errata”.
19 D13 Data line Data line
20 D14 Data line Data line
21 D15 Data line Data line
22 GND GND GND
23 D16 Data line Data line
24 D17 Data line Data line
25 D18 Data line Data line
26 D19 Data line Data line
27 GND GND GND
28 D20 Data line Data line
29 D21 Data line Data line
30 D22 Data line Data line
31 D23 Data line Data line
32 GND GND GND
33 PCLK Pixel clock --
34 VSYNC/CS Vertical sync Chip select
35 HSYNC/WE Horizontal sync Write enable
36DATA_ENABLE/RE
Data enable Read enable
37 (1) SPI_SCK (1) -- SPI_SCK (1)
38 (1) SPI_MOSI (1) -- SPI_MOSI (1)
39 (1) SPI_MISO (1) -- SPI_MISO (1)
40 (1) SPI_CS (1) -- SPI_CS (1)
41 ENABLE Display Enable signal Display Enable signal
42 TWI_SDA I2C data line (maXTouch®) I2C data line (maXTouch)
43 TWI_SCL I2C clock line (maXTouch) I2C clock line (maXTouch)
44 IRQ1 maXTouch interrupt line maXTouch interrupt line
45 IRQ2 Interrupt line for other I2C devices Interrupt line for other I2C devices
46 PWM Backlight control Backlight control
47 RESET Reset for both display and maXTouch Reset for both display and maXTouch
48 VCC 3.3V or 5V supply (0R) 3.3V supply
49 VCC 3.3V or 5V supply (0R) 3.3V supply
50 GND GND GND
Table 4-22: LCD Socket J22 Signal Descriptions (Continued)
PIN Signal Display Module Interface Function MCU Interface Function
DS50002884A-page 40 2019 Microchip Technology Inc.
SAMA5D3 XPLAINED
4.3.11 PIO Usage
Most signals can also be configured as simple inputs or outputs from the processor.
Table 4-23: PIO A Pin Assignment and Signal Description
Power Rail PIO Signal Signal Signal Main Board Function Extended Function
VDDIOP0 PA0 LCDDAT0 – – – LCDDAT0
VDDIOP0 PA1 LCDDAT1 – – – LCDDAT1
VDDIOP0 PA2 LCDDAT2 – – – LCDDAT2
VDDIOP0 PA3 LCDDAT3 – – – LCDDAT3
VDDIOP0 PA4 LCDDAT4 – – – LCDDAT4
VDDIOP0 PA5 LCDDAT5 – – – LCDDAT5
VDDIOP0 PA6 LCDDAT6 – – – LCDDAT6
VDDIOP0 PA7 LCDDAT7 – – – LCDDAT7
VDDIOP0 PA8 LCDDAT8 – – – LCDDAT8
VDDIOP0 PA9 LCDDAT9 – – – LCDDAT9
VDDIOP0 PA10 LCDDAT10 – – – LCDDAT10
VDDIOP0 PA11 LCDDAT11 – – – LCDDAT11
VDDIOP0 PA12 LCDDAT12 – – – LCDDAT12
VDDIOP0 PA13 LCDDAT13 – – – LCDDAT13
VDDIOP0 PA14 LCDDAT14 – – – LCDDAT14
VDDIOP0 PA15 LCDDAT15 – – – LCDDAT15
VDDIOP0 PA16 LCDDAT16 ISI_D0 – – ISI_D0
VDDIOP0 PA17 LCDDAT17 ISI_D1 – – ISI_D1
VDDIOP0 PA18 LCDDAT18 TWD2 ISI_D2 – TWD2/ISI_D2
VDDIOP0 PA19 LCDDAT19 TWCK2 ISI_D3 – TWCK2/ISI_D3
VDDIOP0 PA20 LCDDAT20 PWMH0 ISI_D4 – ISI_D4
VDDIOP0 PA21 LCDDAT21 PWML0 ISI_D5 – ISI_D5
VDDIOP0 PA22 LCDDAT22 PWMH1 ISI_D6 – ISI_D6
VDDIOP0 PA23 LCDDAT23 PWML1 ISI_D7 – ISI_D7
VDDIOP0 PA24 LCDPWM – – – LCDPWM
VDDIOP0 PA25 LCDDISP – – – LCDDISP
VDDIOP0 PA26 LCDVSYNC – – – LCDVSYNC
VDDIOP0 PA27 LCDHSYNC – – – LCDHSYNC
VDDIOP0 PA28 LCDPCK – – – LCDPCK
VDDIOP0 PA29 LCDDEN – – – LCDDEN
VDDIOP0 PA30 TWD0 URXD1ISI_VSYN
CTWD0 URXD1/ISI_VSYNC
VDDIOP0 PA31 TWCK0 UTXD1ISI_HSYN
CTWCK0 UTXD1/ISI_HSYNC
2019 Microchip Technology Inc. DS50002884A-page 41
SAMA5D3 XPLAINED
Table 4-24: PIO B Pin Assignment and Signal Description
Power Rail PIO Signal Signal Signal Main Board Function
Extended Function
VDDIOP1 PB0 GTX0 PWMH0 – GTX0 –
VDDIOP1 PB1 GTX1 PWML0 – GTX1 –
VDDIOP1 PB2 GTX2 TK1 – GTX2 –
VDDIOP1 PB3 GTX3 TF1 – GTX3 –
VDDIOP1 PB4 GRX0 PWMH1 – GRX0 –
VDDIOP1 PB5 GRX1 PWML1 – GRX1 –
VDDIOP1 PB6 GRX2 TD1 – GRX2 –
VDDIOP1 PB7 GRX3 RK1 – GRX3 –
VDDIOP1 PB8 GTXCK PWMH2 – GTXCK –
VDDIOP1 PB9 GTXEN PWML2 – GTXEN –
VDDIOP1 PB10 GTXER RF1 – INT_GETH --
VDDIOP1 PB11 GRXCK RD1 – GRXCK --
VDDIOP1 PB12 GRXDV PWMH3 – INT_ETH –
VDDIOP1 PB13 GRXER PWML3 – GRXER –
VDDIOP1 PB14 GCRS CANRX1 – – CANRX1
VDDIOP1 PB15 GCOL CANTX1 – – CANTX1
VDDIOP1 PB16 GMDC – – GMDC --
VDDIOP1 PB17 GMDIO – – GMDIO –
VDDIOP1 PB18 G125CK – – G125CK –
VDDIOP1 PB19 MCI1_CDA GTX4 – MCI1_CDA --
VDDIOP1 PB20 MCI1_DA0 GTX5 – MCI1_DA0 –
VDDIOP1 PB21 MCI1_DA1 GTX6 – MCI1_DA1 --
VDDIOP1 PB22 MCI1_DA2 GTX7 – MCI1_DA2 --
VDDIOP1 PB23 MCI1_DA3 GRX4 – MCI1_DA3 –
VDDIOP1 PB24 MCI1_CK GRX5 – MCI1_CK –
VDDIOP1 PB25 SCK1 GRX6 – – SCK1
VDDIOP1 PB26 CTS1 GRX7 – – CTS1
VDDIOP1 PB27 RTS1 PWMH1 – – RTS1
VDDIOP1 PB28 RXD1 – – – RXD1
VDDIOP1 PB29 TXD1 – – – TXD1
VDDIOP0 PB30 DRXD – – DRXD (DBGU) --
VDDIOP0 PB31 DTXD – – DTXD (DBGU) --
DS50002884A-page 42 2019 Microchip Technology Inc.
SAMA5D3 XPLAINED
Table 4-25: PIO C Pin Assignment and Signal Description
Power Rail PIO Signal Signal SignalMain Board
Function Extended Function
VDDIOP0 PC0 ETX0 TIOA3 – ETX0 ETX0/TIOA3
VDDIOP0 PC1 ETX1 TIOB3 – ETX1 ETX1/TIOB3
VDDIOP0 PC2 ERX0 TCLK3 – ERX0 ERX0/TCLK3
VDDIOP0 PC3 ERX1 TIOA4 – ERX1 ERX1/TIOA4
VDDIOP0 PC4 ETXEN TIOB4 – ETXEN ETXEN/TIOB4
VDDIOP0 PC5 ECRSDV TCLK4 – ECRSDV ECRSDV/TCLK4
VDDIOP0 PC6 ERXER TIOA5 – ERXER ERXER/TIOA5
VDDIOP0 PC7 EREFCK TIOB5 – EREFCK EREFCK/TIOB5
VDDIOP0 PC8 EMDC TCLK5 – EMDC EMDC/TCLK5
VDDIOP0 PC9 EMDIO -- – EMDIO EMDIO
VDDIOP0 PC10 MCI2_CDA LCDDAT20 – – LCDDAT20
VDDIOP0 PC11 MCI2_DA0 LCDDAT19 – – LCDDAT19
VDDIOP0 PC12 MCI2_DA1 TIOA1 LCDDAT18 – LCDDAT18
VDDIOP0 PC13 MCI2_DA2 TIOB1 LCDDAT17 – LCDDAT17
VDDIOP0 PC14 MCI2_DA3 TCLK1 LCDDAT16 – LCDDAT16
VDDIOP0 PC15 MCI2_CK PCK2 LCDDAT21 – LCDDAT21/PCK2
VDDIOP0 PC16 TK0 – – – TK0 Audio
VDDIOP0 PC17 TF0 – – – TF0 Audio
VDDIOP0 PC18 TD0 – – – TD0 Audio
VDDIOP0 PC19 RK0 – – – RK0 Audio
VDDIOP0 PC20 RF0 – – – RF0 Audio
VDDIOP0 PC21 RD0 – – – RD0 Audio
VDDIOP0 PC22 SPI1_MISO – – – SPI1_MISO
VDDIOP0 PC23 SPI1_MOSI – – – SPI1_MOSI
VDDIOP0 PC24 SPI1_SPCK – – – SPI1_SPCK
VDDIOP0 PC25 SPI1_NPCS0 – – – SPI1_NPCS0
VDDIOP0 PC26 SPI1_NPCS1 TWD1 ISI_D11 – SPI1_NPCS1/TWD1
VDDIOP0 PC27 SPI1_NPCS2 TWCK1 ISI_D10 – SPI1_NPCS2/TWCK1
VDDIOP0 PC28 SPI1_NPCS3 PWMFI0 ISI_D9 – SPI1_NPCS3/ISI_D9
VDDIOP0 PC29 URXD0 PWMFI2 ISI_D8 – URXD0/ISI_D8
VDDIOP0 PC30 UTXD0 ISI_PCK – – UTXD0/ISI_PCK
VDDIOP0 PC31 FIQ PWMFI1 – IRQ_PMIC –
2019 Microchip Technology Inc. DS50002884A-page 43
SAMA5D3 XPLAINED
Table 4-26: PIO D Pin Assignment and Signal Description
Power Rail PIO Signal Signal Signal Main Board Function
Extended Function
VDDIOP1 PD0 MCI0_CDA – – MCI0_CDA –
VDDIOP1 PD1 MCI0_DA0 – – MCI0_DA0 –
VDDIOP1 PD2 MCI0_DA1 – – MCI0_DA1 –
VDDIOP1 PD3 MCI0_DA2 – – MCI0_DA2 –
VDDIOP1 PD4 MCI0_DA3 – – MCI0_DA3 –
VDDIOP1 PD5 MCI0_DA4 TIOA0 PWMH2 MCI0_DA4 –
VDDIOP1 PD6 MCI0_DA5 TIOB0 PWML2 MCI0_DA5 –
VDDIOP1 PD7 MCI0_DA6 TCLK0 PWMH3 MCI0_DA6 –
VDDIOP1 PD8 MCI0_DA7 PWML3 – MCI0_DA7 –
VDDIOP1 PD9 MCI0_CK – – MCI0_CK –
VDDIOP1 PD10 SPI0_MISO – – SPI0_MISO SPI0_MISO
VDDIOP1 PD11 SPI0_MOSI – – SPI0_MOSI SPI0_MOSI
VDDIOP1 PD12 SPI0_SPCK – – SPI0_SPCK SPI0_SPCK
VDDIOP1 PD13 SPI0_NPCS0 – – SPI0_NPCS0 –
VDDIOP1 PD14 SCK0 SPI0_NPCS1 CANRX0 –SCK0/
SPI0_NPCS0/CANRX0
VDDIOP1 PD15 CTS0 SPI0_NPCS2 CANTX0 –CST0/
SPI0_NPCS2/CANTX0
VDDIOP1 PD16 RTS0 SPI0_NPCS3 PWMFI3 – SPI0_NPCS3
VDDIOP1 PD17 RXD0 – – – RXD0
VDDIOP1 PD18 TXD0 – – – TXD0
VDDIOP1 PD19 ADTRG – – – ADTRG (HSYNC)
VDDANA PD20 AD0 – – – AD0/LCD TSC
VDDANA PD21 AD1 – – – AD1/LCD TSC
VDDANA PD22 AD2 – – – AD2/LCD TSC
VDDANA PD23 AD3 – – – AD3/LCD TSC
VDDANA PD24 AD4 – – – AD4
VDDANA PD25 AD5 – – – AD5
VDDANA PD26 AD6 – – – AD6
VDDANA PD27 AD7 – – – AD7
VDDANA PD28 AD8 – – – AD8
VDDANA PD29 AD9 – – – AD9
VDDANA PD30 AD10 PCK0 – -- AD10/PCK0
VDDANA PD31 AD11 PCK1 – – AD11/PCK1
DS50002884A-page 44 2019 Microchip Technology Inc.
SAMA5D3 XPLAINED
Table 4-27: PIO E Pin Assignment and Signal Description
Power Rail PIO Signal Signal SignalMain Board
Function Extended Function
VDDIOM PE0 A0/NBS0 – – MCI0_CD –
VDDIOM PE1 A1 – – MCI1_CD –
VDDIOM PE2 A2 – – PWR_MCI0 –
VDDIOM PE3 A3 – – EN5V_USBB –
VDDIOM PE4 A4 – – EN5V_USBC –
VDDIOM PE5 A5 – – OVCUR_USB –
VDDIOM PE6 A6 – – – RST_LCD
VDDIOM PE7 A7 – – – IRQ1 / ChgMXT
VDDIOM PE8 A8 – – – IRQ2/ChgQT
VDDIOM PE9 A9 – – VBUS_SENSE A9
VDDIOM PE10 A10 – – – A10
VDDIOM PE11 A11 – – – A11
VDDIOM PE12 A12 – – – A12
VDDIOM PE13 A13 – – – A13
VDDIOM PE14 A14 – – – A14
VDDIOM PE15 A15 SCK3 – – A15/SCK3
VDDIOM PE16 A16 CTS3 – – A16/CTS3
VDDIOM PE17 A17 RTS3 – – A17/RTS3
VDDIOM PE18 A18 RXD3 – – A18/RXD3
VDDIOM PE19 A19 TXD3 – – A19/TXD3
VDDIOM PE20 A20 SCK2 – – A20/SCK2
VDDIOM PE21 A21/NANDALE – – A21/NANDALE –
VDDIOM PE22 A22/NANDCLE – – A22/NANDCLE –
VDDIOM PE23 A23 CTS2 – 1-Wire / User LED A23/1-Wire/CTS2
VDDIOM PE24 A24 RTS2 – Power LED A24/RTS2
VDDIOM PE25 A25 RXD2 – – A25/RXD2
VDDIOM PE26 NCS0 TXD2 – – NCS0/TXD2
VDDIOM PE27 NCS1 TIOA2 LCDDAT22 – LCDDAT22
VDDIOM PE28 NCS2 TIOB2 LCDDAT23 LCDDAT23
VDDIOM PE29 NWR1/NBS1 TCLK2 – USER_PB NWR1/NBS1/TCLK2
VDDIOM PE30 NWAIT – – nPBSTA_PMIC –
VDDIOM PE31 IRQ PWML1 – – IRQ/PWML1
2019 Microchip Technology Inc. DS50002884A-page 45
SAMA5D3 XPLAINED
4.4 SAMA5D3 Xplained Board Schematics
This section contains the following schematics:
• General information• Block Diagram• PIO Multiplexing Table• Power Supplies• SAMA5D3 Device and USB Interfaces• DDR2 Memory• NAND Flash and Optional Memories• SD and Micro-SD Interfaces• Gigabit Ethernet• Ethernet 10/100• LCD, JTAG, DEBUG and Extended Connectors
DS50002884A-page 46 2019 Microchip Technology Inc.
SAMA5D3 XPLAINED
Figure 4-38: General information5 5
4 4
3 3
2 2
1 1
DD
CC
BB
AA
RE
VD
ATE
MO
DIF
.D
ES
.D
ATE
VE
R.
SC
ALE
1/1
RE
V.
SH
EE
T
INIT
ED
ITAA
Rev
A
1 11A
XX-X
XX-X
XPP
nXX
X
Title
& R
evis
ion
His
tory
27-S
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3
SAM
A5D
3 Xp
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ed
Embe
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-Feb
-14
XXX
XX-X
XX-X
X
RE
VD
ATE
MO
DIF
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.D
ATE
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R.
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ALE
1/1
RE
V.
SH
EE
T
INIT
ED
ITAA
Rev
A
1 11A
XX-X
XX-X
XPP
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Title
& R
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ion
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tory
27-S
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SAM
A5D
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-Feb
-14
XXX
XX-X
XX-X
X
RE
VD
ATE
MO
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ES
.D
ATE
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ALE
1/1
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V.
SH
EE
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INIT
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ITAA
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A
1 11A
XX-X
XX-X
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nXX
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& R
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ion
His
tory
27-S
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3
SAM
A5D
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ed
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-Feb
-14
XXX
XX-X
XX-X
X
Schematic: SAMA5D3 Xplained
SHEET
SHEET NAME
01
02
03
04
05
06
07
08
09
Title & Revision History
Block Diagram
Power Supply
SAMA5D3x-I & USB
SAMA5D3x-II & NAND
HSMCI
Ethernet_ETH1_10/100
Connectors
SAMA5D3x-II & DDR2
10
11
Ethernet_ETH0_10/100/1000
PIO Assignment
NO
IT
PI
RC
SE
DE
TA
DREVISION
19 Feb 2014
SAMA5D3 Xplained RevA
Official Release
2019 Microchip Technology Inc. DS50002884A-page 47
SAMA5D3 XPLAINED
Figure 4-39: Block Diagram5 5
4 4
3 3
2 2
1 1
DD
CC
BB
AA
RE
VD
ATE
MO
DIF
.D
ES
.D
ATE
VE
R.
SC
ALE
1/1
RE
V.
SH
EE
T
INIT
ED
ITAA
Rev
A
2 11A
XX-X
XX-X
XPP
nXX
X
Bloc
k D
iagr
am
27-S
ep-1
3
SAM
A5D
3 Xp
lain
ed
19-F
eb-1
4Em
best
XXX
XX-X
XX-X
X
RE
VD
ATE
MO
DIF
.D
ES
.D
ATE
VE
R.
SC
ALE
1/1
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V.
SH
EE
T
INIT
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ITAA
Rev
A
2 11A
XX-X
XX-X
XPP
nXX
X
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k D
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am
27-S
ep-1
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SAM
A5D
3 Xp
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ed
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XXX
XX-X
XX-X
X
RE
VD
ATE
MO
DIF
.D
ES
.D
ATE
VE
R.
SC
ALE
1/1
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V.
SH
EE
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INIT
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ITAA
Rev
A
2 11A
XX-X
XX-X
XPP
nXX
X
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SAM
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XXX
XX-X
XX-X
X
PIO A,...E
PIO A,...E
SAMA5D36
CORTEX(R)-A5 PROCESSOR
Extension board connectors
EBI
2/4Gb
DDR2
SDRAM
2Gb
NAND
FLASH
SERIAL
DATA
FLASH
Micro SD
CARD
10/100/1000
FAST ETHERNET
ETH0
Power rails
VBAT
ANALOG Reference
10/100
FAST ETHERNET
ETH1
USB
DEVICE
USB
Host
x2
Single
PMU
Solution
5V INPUT
USB A,B,C
SD
CARD
Reset
Force PwrOn
Push
Buttons
LCD
Connector
JTAG & DBGU
JTAG
DBGU
USER
LEDS
PIO
5V & 3V3
DS50002884A-page 48 2019 Microchip Technology Inc.
SAMA5D3 XPLAINED
Figure 4-40: PIO Multiplexing Table5 5
4 4
3 3
2 2
1 1
DD
CC
BB
AA
RE
VD
ATE
MO
DIF
.D
ES
.D
ATE
VE
R.
SC
ALE
1/1
RE
V.
SH
EE
T
INIT
ED
ITAA
Rev
A
3 11A
XX-X
XX-X
XPP
nXX
X
PIO
Ass
ignm
ent
27-S
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SAM
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ed
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V.
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INIT
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A
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XX-X
XX-X
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X
PIO
Ass
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ent
27-S
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SAM
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PIO
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ent
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XX-X
X
LCD
DAT
0LC
DD
AT1
LCD
DAT
2LC
DD
AT3
LCD
DAT
4LC
DD
AT5
LCD
DAT
6LC
DD
AT7
LCD
DAT
8LC
DD
AT9
LCD
DA
T10
LCD
DA
T11
LCD
DA
T12
LCD
DA
T13
LCD
DA
T14
LCD
DA
T15
MC
I0_C
DA
MC
I0_D
A0
MC
I0_D
A1
MC
I0_D
A2
MC
I0_D
A3
MC
I0_D
A4
MC
I0_D
A5
MC
I0_D
A6
LCD
PW
MLC
DD
ISP
LCD
VS
YN
CLC
DH
SY
NC
LCD
PC
KLC
DD
EN
MC
I0_D
A7
GTX
CK
GTX
0
GR
X0
GM
DC
GM
DIO
G12
5CK
MC
I1_C
DA
MC
I1_D
A0
MC
I1_D
A1
MC
I1_D
A2
MC
I1_D
A3
MC
I1_C
KS
CK
1C
TS1
RTS
1R
XD
1TX
D1
DR
XD
DTX
D
ETX0
ETX1
ER
X0
ER
X1
ETX
EN
EC
RS
DV
LCD
DA
T17
LCD
DA
T16
LCD
DA
T21/
PC
K2
EC
RS
DV
ER
EFC
KE
MD
CE
MD
IOLC
DD
AT2
0LC
DD
AT1
9LC
DD
AT1
8
TK0
TF0
TD0
SPI1
_NPC
S2/T
WC
K1/IS
I_D
10SP
I1_N
PCS3
/ISI_
D9
UR
XD0/
ISI_
D8
UTX
D0/
ISI_
PCK
IRQ
_PM
IC
MC
I0_C
KS
PI0
_MIS
OS
PI0
_MO
SI
SP
I0_S
PC
KS
PI0
_NP
CS
0S
CK
0/C
AN
RX
0C
TS0/
CAN
TX0
SP
I0_N
PC
S3
RX
D0
TXD
0A
DTR
GA
D0
MC
I0_C
DM
CI1
_CD
PW
R_M
CI0
EN
5V_U
SB
BE
N5V
_US
BC
OV
CU
R_U
SB
RS
T_LC
DIR
Q1
IRQ
2V
BU
S_S
EN
SE
/A9
A16
/CTS
3
A22
/NA
ND
CLE
1-W
ire/U
ser l
ed1/
A23/
CTS
2Po
wer
led/
A24/
RTS
2
NC
S0/T
XD2
LCD
DA
T22
LCD
DA
T23
NW
R1/
NB
S1/
TCLK
2S
TA_P
MIC
AD
TRG
/PW
ML1
LCD
VC
CV
CC
GN
D
LCD
DIS
P
LCD
VS
YN
C
LCD
DE
N
SP
I0_M
ISO
/AD
2_Y
P
SPI0
_SPC
K/AD
0_XP
LCD
DAT
0
Res
et
IRQ
1TW
CK
1
LCD
PW
M
LCD
HS
YN
C
LCD
PC
K
SPI0
_MO
SI/A
D1_
XM
SP
I0_N
PC
S3/
AD
3_Y
M
GN
D
ISI_
D5
ISI_
D3
ISI_
D1
ISI_
D7
ISI_
HSY
NC
/UTX
D1
ISI_
VSYN
C/U
RXD
1
ISI_
D6
ISI_
D4
ISI_
D2
ISI_
D0
JUMPER DESCRIPTION
JP2
PA
RT
FUN
CTI
ON
DE
FAU
LT
JP3
JP4
JP5
JP6
JP1
SH
OR
T
CLO
SE
I_IO
M M
easu
rem
ent
CS
Ser
ial f
lash
mem
ory
CS
Nan
d fla
sh m
emor
yC
LOS
E
I_IO
P M
easu
rem
ent
I_C
OR
E M
easu
rem
ent
I_IO
DD
R M
easu
rem
ent
PD
31
PA
18P
A17
PA
16P
IOA
PA
19P
A20
PA
21
PA
26P
A27
PA
22P
A23
PA
24
PA
28P
A29
PA
30
PA
25
PA
31
PB
0P
IOB
PB
4P
B3
PB
2P
B1
PB
7P
B6
PB
5
PB
10P
B11
PB
12
PB
8
PB
13P
B14
PB
15
PB
9
PIO
B
PB
18P
B17
PB
16P
C1
PC
0P
IOC
PC
5P
C4
PC
3P
C2
PC
9P
C8
PC
7P
C6
PC
13P
C12
PC
11P
C10
PC
15P
C14
PC
17P
C16
PIO
C
PC
21P
C20
PC
19P
C18
PC
25P
C24
PC
23P
C22
PC
29P
C28
PC
27P
C26
PC
31P
C30
PD
17P
D16
PIO
D
PD
21P
D20
PD
19P
D18
PIO
MU
XIN
G
US
AG
EU
SA
GE
US
AG
EU
SA
GE
US
AG
EU
SA
GE
US
AG
EP
E0
PIO
E
PE
4P
E3
PE
2P
E1
PE
7P
E6
PE
5
PE
11P
E10
PE
9P
E8
US
AG
E
PE
15P
E14
PE
13P
E12
PIO
EU
SA
GE
PD
22
PD
26P
D25
PD
24P
D23
PD
30P
D29
PD
28P
D27
PB
21
PB
19
PB
26
PB
24P
B23
PB
22
PB
28P
B29
PB
27
PB
25
PB
31
PB
20
PB
30
PE
17P
E16
PE
21P
E20
PE
19P
E18
PE
25
PE
23P
E24
PE
22
PE
28
PE
26P
E27
PE
31
PE
29P
E30
PA
12P
A11
PA
10P
A9
PA
8P
A7
PA
6P
A5
PA
4P
A3
PA
2P
A1
PA
0P
IOA
PA
15P
A14
PA
13
RK
0R
F0R
D0
SP
I1_M
ISO
SP
I1_M
OS
IS
PI1
_SP
CK
SP
I1_N
PC
S0
SPI1
_NPC
S1/T
WD
1/IS
I_D
11
A25
/RX
D2
PD
0P
D1
PD
2
PD
8
PD
3
PD
6P
D5
PD
4
PIO
D
PD
13P
D12
PD
7
PD
10P
D9
PD
15
PD
11
PD
14
US
AG
E
GTX
1G
TX2
GTX
3
GR
X1
GR
X2
GR
X3
GTX
ENIN
T_G
ETH
GR
XC
KIN
T_ET
HG
RX
ER
CA
NR
X1
CAN
TX1
AD
1A
D2
AD
3A
D4
AD
5A
D6
AD
7A
D8
AD
9A
D10
/PC
K0
/PC
K1
A10
A11
A12
A13
A14
A15
/SC
K3
A17
/RTS
3A
18/R
XD
3A
19/T
XD
3A
20/S
CK
2A
21/N
AN
DA
LE
1 2 9 103 4 5 6 7 8 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
ID_S
YS
LCD
DAT
1LC
DD
AT2
LCD
DAT
3
LCD
DAT
4LC
DD
AT5
LCD
DAT
6LC
DD
AT7
GN
D
GN
DLC
DD
AT8
LCD
DAT
9LC
DD
AT1
0LC
DD
AT1
1G
ND
LCD
DA
T12
LCD
DA
T13
LCD
DA
T14
LCD
DA
T15
GN
D
LCD
DA
T16
LCD
DA
T17
LCD
DA
T18
LCD
DA
T19
GN
D
LCD
DA
T20
LCD
DA
T21
LCD
DA
T22
LCD
DA
T23
GN
D
IRQ
2
TWD
1
SH
OR
TS
HO
RT
SH
OR
T
2019 Microchip Technology Inc. DS50002884A-page 49
SAMA5D3 XPLAINED
Figure 4-41: Power Supplies5 5
4 4
3 3
2 2
1 1
DD
CC
BB
AA
BP2
BP1
BP1
BP2
5V_M
AIN
VDD
CO
RE
VDD
IOP1
VDD
IOP0
VDD
ANA
VDD
PLLA
VDD
OSC
VDD
IOD
DR
VDD
IOM
AVD
DL_
PLL
DVD
DL
AVD
DL
FUSE
_2V5
5V_M
AIN
3V3
3V3
VDD
UTM
IC
3V3
5V_M
AIN
TWC
K_PM
IC[7
]TW
D_P
MIC
[7]
NR
ST[5
,9,1
0,11
] SHD
N[5
]
PC31
[7]
WKU
P[5
]
Vbus
[5] 5V
_Ext
[11]
PE30
[7]
RE
VD
ATE
MO
DIF
.D
ES
.D
ATE
VE
R.
SC
ALE
1/1
RE
V.
SH
EE
T
INIT
ED
ITAA
Rev
A
4 11A
XX-X
XX-X
XPP
nXX
X
Pow
er S
uppl
y
27-S
ep-1
3
SAM
A5D
3 Xp
lain
ed
19-F
eb-1
4Em
best
XXX
XX-X
XX-X
X
RE
VD
ATE
MO
DIF
.D
ES
.D
ATE
VE
R.
SC
ALE
1/1
RE
V.
SH
EE
T
INIT
ED
ITAA
Rev
A
4 11A
XX-X
XX-X
XPP
nXX
X
Pow
er S
uppl
y
27-S
ep-1
3
SAM
A5D
3 Xp
lain
ed
19-F
eb-1
4Em
best
XXX
XX-X
XX-X
X
RE
VD
ATE
MO
DIF
.D
ES
.D
ATE
VE
R.
SC
ALE
1/1
RE
V.
SH
EE
T
INIT
ED
ITAA
Rev
A
4 11A
XX-X
XX-X
XPP
nXX
X
Pow
er S
uppl
y
27-S
ep-1
3
SAM
A5D
3 Xp
lain
ed
19-F
eb-1
4Em
best
XXX
XX-X
XX-X
X
(1V2)
(1V8)
(3V3)
(3V3)
(2V5)
RES
ETW
AK
UP
orFo
rce
Pow
er O
N
Aut
oP
WR
ON
(opt
ion)
Pla
ce T
P6
TP7
to B
otto
m
PC27
PC26
R1
R2
R3
R17
5 R
176
R17
7 0R
080
5
C10
100n
FC
1010
0nF
L92.
2uH
L92.
2uH
R14
49.9
KR
1449
.9K
C21
2.2u
FC
212.
2uF
BP2
BP2
C4
1uF
C4
1uF
C13
10uF
C13
10uF R
160R
R16
0R
C23
2.2u
FC
232.
2uF
R17
2R2
R17
2R2
C20
100n
FC
2010
0nF
MN
1AC
T886
5M
N1
ACT8
865
GNDP1 29
GNDA 2
INL4
55
VP
131
INL6
76
GNDP2 28
VP
226
GNDP3 14
EXPAD 33
VP
316
NC
225
VD
DR
EF
23
nRS
T011
nIR
Q12
nPB
STA
T13
VS
EL
20N
C1
18P
WR
HLD
10P
WR
EN
17
SC
L21
SD
A22
RE
FBP
32
nPB
IN9
SW
130
OU
T11
OU
T224
SW
227
SW
315
OU
T319
OU
T43
OU
T54
OU
T67
OU
T78
R17
50R
R17
50R
C2
4.7u
FC
24.
7uF
JP1
DN
P(JU
MPE
R)
JP1
DN
P(JU
MPE
R)
12
TP7
SMD
TP7
SMD
Q1
IRLM
L250
2
Q1
IRLM
L250
2
1
3 2
C5
1uF
C5
1uF
R19
100K
1%
R19
100K
1%
C1
4.7u
FC
14.
7uF
R15
0RR15
0RJ2 DN
P(D
C J
ACK)
J2 DN
P(D
C J
ACK)
3 12
L11
180o
hm a
t 100
MH
zL1
118
0ohm
at 1
00M
Hz
12
L818
0ohm
at 1
00M
Hz
L818
0ohm
at 1
00M
Hz
12
C18
47nF
C18
47nF
C22
2.2u
FC
222.
2uF
JP3
DN
P(JU
MPE
R)
JP3
DN
P(JU
MPE
R)
12
R11
0RR
110R
TP2
SMD
TP2
SMD
C26
4.7u
FC
264.
7uF
C6
1uF
C6
1uF
R6
1.5K
1%
R6
1.5K
1%
L52.
2uH
L52.
2uH
JP4
DN
P(JU
MPE
R)
JP4
DN
P(JU
MPE
R)
12
C25
100n
FC
2510
0nF
L6 60m
A10
uH
L6 60m
A10
uH
C3
4.7u
FC
34.
7uF
JP2
DN
P(JU
MPE
R)
JP2
DN
P(JU
MPE
R)
12
R7
1.5K
1%
R7
1.5K
1%
C11
4.7u
FC
114.
7uF
R5
2R2
R5
2R2
R8
10K
R8
10K
R4
1RR4
1R
C17
100n
FC
1710
0nF
C9
10uF
C9
10uF
L72.
2uH
L72.
2uH
C19
100n
FC
1910
0nF
R17
6D
NP(
0R)
R17
6D
NP(
0R)
TP6
SMD
TP6
SMD
L12
60m
A10
uH
L12
60m
A10
uH
C7
4.7u
FC
74.
7uF
D4
P4SM
AJ5.
0A
D4
P4SM
AJ5.
0A
12
R18
60R
R18
60R
L318
0ohm
at 1
00M
Hz
L318
0ohm
at 1
00M
Hz
12
L118
0ohm
at 1
00M
Hz
L118
0ohm
at 1
00M
Hz
12
R12
49.9
KR
1249
.9K
L10
180o
hm a
t 100
MH
zL1
018
0ohm
at 1
00M
Hz
12
C15
10uF
C15
10uF
TP1
SMD
TP1
SMD
C14
100n
FC
1410
0nF
R18
1KR
181K
R3
DN
P(0R
)R
3D
NP(
0R)
C13
010
nFC
130
10nF
C16
10uF
C16
10uF
C8
10uF
C8
10uF
R9
DN
P(0R
)R
9D
NP(
0R)
C24
2.2u
FC
242.
2uF
R13
0RR
130R
R10
2R2
R10
2R2
L4 60m
A10
uH
L4 60m
A10
uH
R1
0RR
10R
L218
0ohm
at 1
00M
Hz
L218
0ohm
at 1
00M
Hz
12
BP1
BP1
C12
10uF
C12
10uF
R2
DN
P(0R
)R
2D
NP(
0R)
R17
7D
NP(
0R)
R17
7D
NP(
0R)
DS50002884A-page 50 2019 Microchip Technology Inc.
SAMA5D3 XPLAINED
Figure 4-42: SAMA5D3 Device and USB Interfaces5 5
4 4
3 3
2 2
1 1
DD
CC
BB
AA
HH
SDPC
HH
SDM
AH
HSD
PA
HH
SDM
BH
HSD
PB
HH
SDM
C
TDI
TMS
TCK
TDO
NTR
STN
RST
SHD
NW
KUP
PE23
PE24
VDD
BU
HH
SDM
CH
HSD
PCH
HSD
MB
HH
SDPB
ADVR
EF
5V_U
SBB
5V_U
SBC
5V_U
SBB
5V_U
SBC
VDD
IOP1
VDD
IOP0
VDD
IOM
VDD
IOP0
VDD
OSC
FUSE
_2V5
3V3
GN
DU
TMI
GN
DU
TMI
GN
DU
TMI
3V3
3V3
VDD
PLLA
VDD
IOD
DR
VDD
CO
RE
VDD
UTM
IC
VDD
ANA
EAR
TH_U
SB
5V_M
AIN
EAR
TH_U
SB
EAR
TH_U
SB_A
3V3
EAR
TH_U
SB_A
WKU
P[4
]SH
DN
[4]
PE[0
..31]
[4,7
,8,1
1]
PE5
[7]
TMS
[11]
TCK
[11]
TDO
[11]
TDI
[11]
NR
ST[4
,9,1
0,11
]
AREF
[11]
NTR
ST[1
1]
VBat
[11]
Vbus
[4]
PE9
[7,1
1]
PE29
[7,1
1]
PE4
[7]
PE3
[7]
RE
VD
ATE
MO
DIF
.D
ES
.D
ATE
VE
R.
SC
ALE
1/1
RE
V.
SH
EE
T
INIT
ED
ITAA
Rev
A
5 11A
XX-X
XX-X
XPP
nXX
X
SAM
A5D
3x-I
& U
SB
27-S
ep-1
3
SAM
A5D
3 Xp
lain
ed
19-F
eb-1
4Em
best
XXX
XX-X
XX-X
X
RE
VD
ATE
MO
DIF
.D
ES
.D
ATE
VE
R.
SC
ALE
1/1
RE
V.
SH
EE
T
INIT
ED
ITAA
Rev
A
5 11A
XX-X
XX-X
XPP
nXX
X
SAM
A5D
3x-I
& U
SB
27-S
ep-1
3
SAM
A5D
3 Xp
lain
ed
19-F
eb-1
4Em
best
XXX
XX-X
XX-X
X
RE
VD
ATE
MO
DIF
.D
ES
.D
ATE
VE
R.
SC
ALE
1/1
RE
V.
SH
EE
T
INIT
ED
ITAA
Rev
A
5 11A
XX-X
XX-X
XPP
nXX
X
SAM
A5D
3x-I
& U
SB
27-S
ep-1
3
SAM
A5D
3 Xp
lain
ed
19-F
eb-1
4Em
best
XXX
XX-X
XX-X
X
LED
OV
CU
R_U
SB
USB
HO
ST B
&C
INTE
RFA
CE
USB
DEV
ICE
A IN
TER
FAC
E Max
trac
e-le
ngth
mis
mat
chbe
twee
n U
SB
sig
nals
pai
rssh
ould
be
no g
reat
er th
an 3
.8m
m
90 o
hms
diffe
rent
ial t
race
impe
danc
eR
&C
as c
lose
as
poss
ible
(Sup
er)-
Cap
acito
ren
ergy
sto
rage
Rou
ting
top
or b
otto
m
Rou
ting
US
B
A c
oppe
r pla
nfo
r GN
DU
TMI c
over
all U
SB
com
pom
ents
top/
bot
top/
bot
top/
bot
top/
bot
(VB
US
_SE
NS
E)
USE
R B
UTT
ON
J7_U
SB
_A_U
pJ7
_US
B_B
_Dow
nE
N5V
_US
BC
EN
5V_U
SB
B
Pla
ce T
P5
to B
otto
m
Pla
ce T
P4
to B
otto
m
Pop
ulat
e R
185
ifno
Sup
er C
ap (C
41)
R18
5
1.5K
1%
R18
5
1.5K
1%
R25
10K
R25
10K
BP3
BP3
C50
100n
FC
5010
0nF
C60
10pF
C60
10pF
C32
100n
F
C32
100n
F
R29
DN
P(0R
)R
29D
NP(
0R)
Y232.7
68KH
z C
L=12
.5pF
Y232.7
68KH
z C
L=12
.5pF
1
23
4
D1
BAT5
4C
D1
BAT5
4C
12
3
TP5
SMD
TP5
SMD
C40
1uF
C40
1uF
C49
20pF
C49
20pF
C52
100n
FC
5210
0nF
C54
100n
FC
5410
0nF
C48
100n
FC
4810
0nF
C53
20pF
C53
20pF
R27
200K
R27
200K
VBUS DM DP ID
GND
J6 UBA
F-10
15P
VBUS DM DP ID
GND
J6 UBA
F-10
15P
1 2 3 4 5
7 6
8
R28
0RR28
0R
MN
3
SP25
26A-
2E
MN
3
SP25
26A-
2EEN
A1
FLG
A2
EN
B4
OU
TA8
GN
G6
FLG
B3
IN7
OU
TB5
TP4
SMD
TP4
SMD
C38
100n
FC
3810
0nF
C43
100n
FC
4310
0nF
D3
REDD3
RED
C59
100n
FC
5910
0nF
C35
100n
FC
3510
0nF
C41
DN
P(0.
2F/3
V3)
C41
DN
P(0.
2F/3
V3)
C28
100n
FC
2810
0nF
R34
470R
R34
470R
R24
100K
1%
R24
100K
1%
MN
2HSA
MA5
D3x
_BG
A324
MN
2HSA
MA5
D3x
_BG
A324
GNDCORE_1 A16
VDDCORE_1C5VDDCORE_2C7
GNDCORE_2 C9
VD
DIO
DD
R_1
D13
VDDCORE_3D14
GNDIODDR_1 E14GNDIODDR_2 F10GNDIODDR_3 F13
VD
DIO
DD
R_2
F14
GNDIODDR_4 F15
VDDIOP0_1G7
VD
DIO
DD
R_3
G10
VD
DIO
DD
R_4
G13
VD
DIO
DD
R_5
H11
GNDIODDR_5 H14
GNDIOP_1 J7
GNDIOM_1 J11
GNDANA L4
AD
VR
EF
L5
VD
DA
NA
L6
VDDIOP1_1L11VDDIOP1_2M4
TDO
M11
TMS
N10
GNDIOP_2 N11
GNDCORE_3 N13
GNDFUSE P4
TCK
P9
GNDPLL P10
NTR
ST
P11
GNDUTMI_1 R12
VD
DFU
SE
R3
TDI
R8
VD
DP
LLA
R10
VB
GR
11
VD
DIO
M_1
P12
VDDCORE_4T7
GNDCORE_4 T8
JTA
GS
EL
T9
WK
UP
T10
GNDOSC T11
SH
DN
T12
GNDBU T13
GNDCORE_5 T14
VDDCORE_5T15
VD
DIO
M_2
T16
GNDIOM_2 T17
GNDIOP_3 U7
XIN
U8
BM
SU
9
VD
DO
SC
U11
VD
DU
TMII
U13
TST
U15
XIN
32U
16
VDDCORE_6U17VDDCORE_7V7
XO
UT
V8
NR
ST
V9
VDDIOP0_2V11
VD
DU
TMIC
V13
VDDBUV15
XO
UT3
2V
16
GNDCORE_6 V17
GNDIOP_4 E5
HH
SD
MA
V10
HH
SD
PA
U10
HH
SD
MC
V14
HH
SD
PC
U14
HH
SD
PB
U12
HH
SD
MB
V12
DIB
NU
6D
IBP
V6
R23
1.5K
1%
R23
1.5K
1%
L21
180o
hm a
t 100
MH
zL2
118
0ohm
at 1
00M
Hz
12
C61
100n
FC
6110
0nF
C29
100n
FC
2910
0nF
C27
10nF
C27
10nF
C56
20pF
C56
20pF
R33
100K
1%
R33
100K
1%
C44
100n
FC
4410
0nF
Y1 12M
Hz
CL=
15pF
Y1 12M
Hz
CL=
15pF
1
2 3
4
R21
100K
1%
R21
100K
1%
C30
100n
FC
3010
0nF
C37
100n
FC
3710
0nF
C47
100n
FC
4710
0nF
C42
100n
FC
4210
0nF
C34
100n
FC
3410
0nF
R22
DN
P(10
0K)
R22
DN
P(10
0K)
C64
100n
FC
6410
0nF
Q2
IRLM
L250
2Q
2IR
LML2
502
1
32
R30
5.62
K 1%
R30
5.62
K 1%
R32
470R
R32
470R
C57
100n
FC
5710
0nF
C36
100n
FC
3610
0nF
L13
180o
hm a
t 100
MH
zL1
318
0ohm
at 1
00M
Hz
12
C46
100n
FC
4610
0nF
C39
100n
FC
3910
0nF
C62
10uF
C62
10uF
C63
100n
FC
6310
0nF
C33
100n
FC
3310
0nF
C55
100n
FC
5510
0nF
L15
180o
hm a
t 100
MH
zL1
518
0ohm
at 1
00M
Hz
12
R20
100R
R20
100R
C31
100n
FC
3110
0nF
D2
BLU
E
D2
BLU
E
C58
100n
FC
5810
0nF
A B
J7U
SB8S
-AR
2HF-
NBW
-S2
A B
J7U
SB8S
-AR
2HF-
NBW
-S2
5 86 7
910
1 2 3 4
1112
C45
100n
FC
4510
0nF
R31
0RR
310R
C51
20pF
C51
20pF
L14
180o
hm a
t 100
MH
zL1
418
0ohm
at 1
00M
Hz
12
R26
100K
1%
R26
100K
1%
C65
10uF
C65
10uF
2019 Microchip Technology Inc. DS50002884A-page 51
SAMA5D3 XPLAINED
Figure 4-43: DDR2 Memory5 5
4 4
3 3
2 2
1 1
DD
CC
BB
AA
DD
R_V
REF
DD
R_A
8D
DR
_D9
DD
R_D
10D
DR
_D11
DD
R_D
12D
DR
_D13
DD
R_D
15D
DR
_D14
DD
R_A
1
DD
R_A
9
DD
R_A
2D
DR
_D2
DD
R_A
10
DD
R_A
3
DD
R_A
11
DD
R_A
4
DD
R_A
12
DD
R_A
5
DD
R_D
1
DD
R_V
REF
DD
R_D
0
DD
R_A
6
DD
R_D
4D
DR
_D3
DD
R_A
7D
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DD
R_D
5
DD
R_D
7D
DR
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DD
R_A
0
DD
R_A
8
DD
R_D
27D
DR
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DD
R_D
25
DD
R_D
31
DD
R_D
29D
DR
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DD
R_D
30
DD
R_A
1
DD
R_A
9
DD
R_A
2
DD
R_A
10
DD
R_D
18D
DR
_A3
DD
R_A
11
DD
R_A
4
DD
R_A
12
DD
R_A
5
DD
R_V
REF
DD
R_D
17D
DR
_D16
DD
R_A
6
DD
R_D
19D
DR
_D20
DD
R_D
22D
DR
_A7
DD
R_D
23
DD
R_D
21
DD
R_D
24
DD
R_A
0
DD
R_D
QM
0
DD
R_D
QS1
DD
R_D
QS0
DD
R_C
S
DD
R_B
A0D
DR
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DD
R_B
A2
DD
R_C
KE
DD
R_W
E
DD
R_C
LK
DD
R_R
AS
DD
R_C
LKN
DD
R_C
AS
DD
R_D
QM
2
DD
R_D
QS2
DD
R_D
QS3
DD
R_C
S
DD
R_B
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DR
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DD
R_B
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DD
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R_R
AS
DD
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DD
R_C
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R_C
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DD
R_A
13
DD
R_D
QM
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M3
DD
R_A
13
DD
R_A
13
DD
R_D
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2D
DR
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DD
R_D
QS1
DD
R_D
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DD
R_D
12D
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DD
R_D
0D
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DD
R_D
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DD
R_D
4D
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DD
R_D
6D
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DD
R_D
8D
DR
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DD
R_D
10D
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DD
R_A
12
DD
R_D
26D
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DD
R_D
14D
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DD
R_D
16D
DR
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DD
R_D
18D
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DD
R_D
20D
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DD
R_D
22D
DR
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DD
R_D
24D
DR
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DD
R_D
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DD
R_D
QS2
DD
R_D
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R_D
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DR
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DD
R_B
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DR
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DD
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DD
R_A
1
DD
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DR
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LKN
DD
R_A
0
DD
R_A
2D
DR
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DD
R_R
ASD
DR
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DD
R_V
REF
DD
R_A
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DR
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DD
R_A
6
DD
R_C
SD
DR
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DD
R_A
8D
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DD
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3]
DD
R_D
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1]
DD
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RE
VD
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RE
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Rev
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6 11A
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Rev
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6 11A
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SH
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Rev
A
6 11A
XX-X
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XPP
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SAM
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3
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Add
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, con
trol a
nd d
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trace
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ay n
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d 1.
3 in
ches
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m).
Add
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, con
trol a
nd d
ata
trace
s m
ust b
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ngth
-mat
ched
to w
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inch
(2.5
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ddre
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a tra
ces
mus
t mat
ch th
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ta g
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with
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inch
es (6
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m).
Kee
p ne
ts a
s sh
ort a
s po
ssib
le, t
here
fore
, DD
R2
devi
ces
have
to b
e pl
aced
clo
se a
s po
ssib
le o
f SA
MA
5D36
The
layo
ut E
BI D
DR
2 s
houl
d us
e co
ntro
lled
impe
danc
e tra
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of Z
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impe
danc
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m
Diff
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m
Diff
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100
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p/B
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m
C98
100n
FC
9810
0nF
C99
100n
FC
9910
0nF
C73
100n
FC
7310
0nF
C10
010
0nF
C10
010
0nF
R46
1.5K
1%
R46
1.5K
1%
C68
100n
FC
6810
0nF
R45
1RR45
1R
R39
4.7K
R39
4.7K
R43
200R
1%
R43
200R
1%
C93
100n
FC
9310
0nF
C90
100n
FC
9010
0nF
C69
100n
FC
6910
0nF
R41
4.7K
R41
4.7K
C91
100n
FC
9110
0nF
C70
100n
FC
7010
0nF
C97
100n
FC
9710
0nF
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AM
MN
5
MT47
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5
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TK
9
DQ
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9
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DL
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SS
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VD
DE
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CK
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QC
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1
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1
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3
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8D
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DQ
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Q11
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DQ
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1D
Q13
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DQ
14B
1D
Q15
B9
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DR
1
VD
DQ
G1
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DQ
G7
VD
DQ
G9
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9
VS
SQ
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VS
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VS
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VD
DQ
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3
LDQ
SE
8LD
QS
F7
RFU
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7
A13
R8
R40
4.7K
R40
4.7K
C79
100n
FC
7910
0nF
R36
DN
P(1K
)R
36D
NP(
1K)
C71
100n
FC
7110
0nF
R47
1.5K
1%
R47
1.5K
1%
R42
4.7K
R42
4.7K
MT47
H64M
16HR
DDR2
SDR
AM
MN
4
MT47
H64M
16HR
DDR2
SDR
AM
MN
4
A0
M8
A1
M3
A2
M7
A3
N2
A4
N8
A5
N3
A6
N7
A7
P2
A8
P8
A9
P3
A10
M2
BA
0L2
OD
TK
9
DQ
0G
8D
Q1
G2
DQ
2H
7D
Q3
H3
DQ
4H
1D
Q5
H9
DQ
6F1
DQ
7F9
UD
QS
B7
UD
QS
A8
LDM
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VD
DJ9
VD
DM
9
VD
DL
J1
VR
EF
J2
VD
DQ
E9
VS
SA
3V
SS
E3
VD
DQ
A9
VD
DE
1
RFU
1A
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FU2
E2
CK
EK
2
CK
J8C
KK
8
CA
SL7
RA
SK
7
WE
K3
CS
L8V
DD
QC
3V
DD
QC
7V
DD
QC
9
VS
SQ
D8
VS
SQ
E7
VS
SQ
F2V
SS
QF8
VD
DA
1
VS
SJ3
A11
P7
BA
1L3
A12
R2
BA
2L1
VS
SN
1
VS
SD
LJ7
VS
SQ
B2
RFU
3R
3
DQ
8C
8D
Q9
C2
DQ
10D
7D
Q11
D3
DQ
12D
1D
Q13
D9
DQ
14B
1D
Q15
B9
VD
DR
1
VD
DQ
G1
VD
DQ
G7
VD
DQ
G9
VS
SP
9
VS
SQ
D2
VS
SQ
A7
VS
SQ
B8
VS
SQ
H2
VS
SQ
H8
VD
DQ
G3
VD
DQ
C1
UD
MB
3
LDQ
SE
8LD
QS
F7
RFU
4R
7
A13
R8
C94
100n
FC
9410
0nF
C78
100n
FC
7810
0nF
C74
100n
FC
7410
0nF
C10
14.
7uF
C10
14.
7uF
R38
0RR
380R
R44
200R
1%
R44
200R
1%
C95
100n
FC
9510
0nF
C75
100n
FC
7510
0nF
TP3
SMD
TP3
SMD
L16
10uH
60m
A
L16
10uH
60m
A
C96
100n
FC
9610
0nF
R37
0RR
370R
C10
210
0nF
C10
210
0nF
MN
2FSA
MA5
D3x
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A324
MN
2FSA
MA5
D3x
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A324 DD
R_C
AS
A5
DD
R_A
13A
6
DD
R_A
11A
7
DD
R_A
7A
8
DD
R_A
2A
9
DD
R_D
30A
10
DD
R_D
27A
11
DD
R_C
LKN
A12
DD
R_D
QS
N3
A13
DD
R_D
25A
14D
DR
_D24
A15
DD
R_D
QS
N2
A17
DD
R_D
19A
18
DD
R_W
EB
5
DD
R_B
A1
B6
DD
R_C
KE
B7
DD
R_A
9B
8
DD
R_A
4B
9
DD
R_A
0B
10
DD
R_D
28B
11
DD
R_C
LKB
12
DD
R_D
QS
3B
13
DD
R_D
23B
14
DD
R_D
QM
2B
15
DD
R_D
16B
16
DD
R_D
QS
2B
17
DD
R_D
17B
18
DD
R_C
SC
8
DD
R_A
8C
10
DD
R_A
1C
11
DD
R_C
ALN
C12
DD
R_V
RE
FC
13
DD
R_B
A0
E9
DD
R_D
QS
N0
D18
DD
R_D
12D
17
DD
R_D
14D
16
DD
R_D
22D
15
DD
R_D
QM
3D
12
DD
R_A
3D
11
DD
R_A
6D
10
DD
R_A
12D
9
DD
R_D
13C
18
DD
R_D
15C
17
DD
R_D
20C
16
DD
R_D
18C
15
DD
R_D
21C
14
DD
R_A
5E
10
DD
R_D
31E
11
DD
R_D
26E
12
DD
R_C
ALP
E13
DD
R_B
A2
F9
DD
R_A
10F1
1
DD
R_D
29F1
2
DD
R_D
8F1
6
DD
R_D
6F1
7
DD
R_D
QS
N1
F18
DD
R_R
AS
G11
DD
R_D
QM
0G
12
DD
R_D
10G
14
DD
R_D
7G
15
DD
R_D
4G
16D
DR
_D3
G17
DD
R_D
QS
1G
18
DD
R_D
0H
12
DD
R_D
2H
13
DD
R_D
5H
15
DD
R_D
1H
17
DD
R_D
QM
1E
15
DD
R_D
11E
16
DD
R_D
9E
17
DD
R_D
QS
0E
18
C88
100n
FC
8810
0nF
C80
100n
FC
8010
0nF
C89
100n
FC
8910
0nF
C82
100n
FC
8210
0nF
R35
DN
P(1K
)R
35D
NP(
1K)
C66
100n
FC
6610
0nF
C83
100n
FC
8310
0nF
C81
100n
FC
8110
0nF
C84
100n
FC
8410
0nF
C76
100n
FC
7610
0nF
C10
410
0nF
C10
410
0nF
C86
100n
FC
8610
0nF
C85
100n
FC
8510
0nF
C77
100n
FC
7710
0nF
C67
100n
FC
6710
0nF
C87
100n
FC
8710
0nF
C92
100n
FC
9210
0nF
C72
100n
FC
7210
0nF
C10
34.
7uF
C10
34.
7uF
DS50002884A-page 52 2019 Microchip Technology Inc.
SAMA5D3 XPLAINED
Figure 4-44: NAND Flash and Optional Memories5 5
4 4
3 3
2 2
1 1
DD
CC
BB
AA
PE30 M
_EBI
_D2
PE21 M
_EBI
_D3
PE31 M
_EBI
_D4
NR
DN
WE
M_E
BI_D
2
M_E
BI_D
4M
_EBI
_D3
M_E
BI_D
6M
_EBI
_D7
M_E
BI_D
5
M_E
BI_D
0M
_EBI
_D1
M_E
BI_D
5
PE24 M
_EBI
_D6
M_E
BI_D
7
PE25
NR
D
PE22 M
_EBI
_D0
PE27
NW
E
PE28
PE29
NAN
DR
DY
M_E
BI_D
1
PE23
PE26
PD13
PD12
PD8
PD9
PD4
PD5
PD6
PD7
PD28
PD16
PD17
PD18
PD10
PD11
PD15
PD14
PD26
PD19
PD23
PD22
PD21
PD20
PD25
PD24
PD29
PD30
PD31
PD27
PD3
PD2
PD1
PD0
PB3
PB2
PB1
PB0
PB13
PB12
PB8
PB9
PB4
PB5
PB6
PB7
PB28
PB16
PB17
PB18
PB10
PB11
PB15
PB14
PB26
PB19
PB23
PB22
PB21
PB20
PB25
PB24
PB29
PB30
PB31
PB27
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
PA8
PA9
PA10
PA11
PA15
PA14
PA13
PA12
PA16
PA17
PA18
PA19
PA23
PA22
PA21
PA20
PA25
PA24
PA28
PA29
PA30
PA31
PA27
PA26
PC3
PC2
PC1
PC0
PC13
PC12
PC8
PC9
PC4
PC5
PC6
PC7
PC28
PC16
PC17
PC18
PC10
PC11
PC15
PC14
PC26
PC19
PC23
PC22
PC21
PC20
PC25
PC24
PC29
PC30
PC31
PC27
PE15
PE14
PE16
PE17
PE18
PE19
PE21
PE22
PE1
PE2
PE3
PE4
PE5
PE6
PE7
PE8
PE9
PE0
PE10
PE11
PE12
PE13
PE20
PC0
PC1
PC2
PC3
PC5
PC6
PC8
PC9
PE23
PD11
PD12
PD10
NC
S3
NC
S3
PD13
PC7
PC4
PC23
PC22
PC24
PA30
PA31
PC26
PC27
NAN
DR
DY
VDD
IOM
VDD
IOM
VDD
IOP1
VDD
IOP1
VDD
IOM
3V3
3V3
PE[0
..31]
[4,5
,8,1
1]
PD[0
..31]
[8,1
1]
PB[0
..31]
[8,9
,10,
11]
PA[0
..31]
[11]
PC[0
..31]
[4,1
1]
J15_
Pin5
[11]
ETH
1_PC
1[1
0]
ETH
1_PC
2[1
0]J1
5_Pi
n4[1
1]
J15_
PC3
[11]
ETH
1_PC
3[1
0]
ETH
1_PC
4[1
0]J1
5_PC
4[1
1]
J18_
PC5
[11]
ETH
1_PC
5[1
0]
ETH
1_PC
6[1
0]J1
8_PC
6[1
1]
J18_
PC7
[11]
ETH
1_PC
7[1
0]
ETH
1_PC
8[1
0]J1
8_PC
8[1
1]
J18_
PC9
[11]
ETH
1_PC
9[1
0]
ETH
1_PC
0[1
0]J1
5_Pi
n6[1
1]
J15_
TWD
[11]
J15_
TWC
K[1
1]
TWC
K_LC
D[1
1]TW
D_L
CD
[11]
TWC
K_IS
I[1
1]TW
D_I
SI[1
1]
TWC
K_PM
IC[4
]TW
D_P
MIC
[4]
RE
VD
ATE
MO
DIF
.D
ES
.D
ATE
VE
R.
SC
ALE
1/1
RE
V.
SH
EE
T
INIT
ED
ITAA
Rev
A
7 11A
XX-X
XX-X
XPP
nXX
X
SAM
A5D
3x-II
& N
AND
27-S
ep-1
3
SAM
A5D
3 Xp
lain
ed
19-F
eb-1
4Em
best
XXX
XX-X
XX-X
X
RE
VD
ATE
MO
DIF
.D
ES
.D
ATE
VE
R.
SC
ALE
1/1
RE
V.
SH
EE
T
INIT
ED
ITAA
Rev
A
7 11A
XX-X
XX-X
XPP
nXX
X
SAM
A5D
3x-II
& N
AND
27-S
ep-1
3
SAM
A5D
3 Xp
lain
ed
19-F
eb-1
4Em
best
XXX
XX-X
XX-X
X
RE
VD
ATE
MO
DIF
.D
ES
.D
ATE
VE
R.
SC
ALE
1/1
RE
V.
SH
EE
T
INIT
ED
ITAA
Rev
A
7 11A
XX-X
XX-X
XPP
nXX
X
SAM
A5D
3x-II
& N
AND
27-S
ep-1
3
SAM
A5D
3 Xp
lain
ed
19-F
eb-1
4Em
best
XXX
XX-X
XX-X
X
(NA
ND
CE)
(NAN
DCLE
)(N
ANDA
LE)
(NA
ND
CLE
)(N
AN
DA
LE)
(SPI
0_M
IS0)
(SPI
0_M
OSI
)
OPT
ION
AL
(SPI
0_SP
CK)
(SPI
0_C
S)
R15
022
RR
150
22R
R13
822
RR
138
22R
MN
2CSA
MA5
D3x
_BG
A324
MN
2CSA
MA5
D3x
_BG
A324 PC
0_E
TX0
D8
PC
1_E
TX1
A4
PC
2_E
RX
0E
8P
C3_
ER
X1
A3
PC
4_E
TXE
NA
2P
C5_
EC
RS
DV
F8P
C6_
ER
XE
RB
3P
C7_
ER
EFC
KG
8P
C8_
EM
DC
B4
PC
9_E
MD
IOF7
PC
10A
1P
C11
D7
PC
12C
6P
C13
E7
PC
14B
2P
C15
F6P
C16
B1
PC
17E
6P
C18
C3
PC
19D
6P
C20
C4
PC
21D
5P
C22
C2
PC
23G
9P
C24
C1
PC
25H
10P
C26
H9
PC
27D
4P
C28
H8
PC
29G
5P
C30
D3
PC
31E
4
C10
510
0nF
C10
510
0nF C10
710
0nF
C10
710
0nF
R15
522
RR
155
22R
R51
1.5K
1%
R51
1.5K
1%
R14
322
RR
143
22R
R18
03.
3KR
180
3.3K
MN
2ESA
MA5
D3x
_BG
A324
MN
2ESA
MA5
D3x
_BG
A324
PE
0_A
0/N
BS
0P
13P
E1_
A1
R14
PE
2_A
2R
13P
E3_
A3
V18
PE
4_A
4P
14P
E5_
A5
U18
PE
6_A
6T1
8P
E7_
A7
R15
PE
8_A
8P
17P
E9_
A9
P15
PE
10_A
10P
18P
E11
_A11
R16
PE
12_A
12N
16P
E13
_A13
R17
PE
14_A
14N
17P
E15
_A15
_SC
K3
R18
PE
16_A
16_C
TS3
N18
PE
17_A
17_R
TS3
P16
PE
18_A
18_R
XD
3M
18P
E19
_A19
_TX
D3
N15
PE
20_A
20_S
CK
2M
15P
E21
_A21
/NA
ND
ALE
N14
PE
22_A
22/N
AN
DC
LEM
17P
E23
_A23
_CTS
2M
13P
E24
_A24
_RTS
2M
16P
E25
_A25
_RX
D2
N12
PE
26_N
CS
0_TX
D2
M14
PE
27_N
CS
1_TI
OA
2M
12P
E28
_NC
S2_
TIO
B2
L13
PE
29_N
WR
1/N
BS
1_TC
LK2
L15
PE
30_N
WA
ITL1
4P
E31
_IR
Q_P
WM
L1L1
6
MN
7 DN
P(D
S243
1)
MN
7 DN
P(D
S243
1)
IO2
GND 1
NC
13
NC
24
NC
35
NC
46
R15
422
RR
154
22R
R16
022
RR
160
22R
R14
422
RR
144
22R
R18
13.
3KR
181
3.3K
MN
8
DN
P(N
25Q
032A
13ES
E40F
)
MN
8
DN
P(N
25Q
032A
13ES
E40F
)
HO
LD/D
Q3
7G
ND
4
VC
C8
S1
C6
DQ
O5
DQ
12
W/V
pp/D
Q2
3
MN
11
DN
P(D
S28E
05)
MN
11
DN
P(D
S28E
05)
NC
2
IO1
GN
D3
R15
322
RR
153
22R
JP6
JUM
PER
JP6
JUM
PER
12
R14
122
RR
141
22R
R16
122
RR
161
22R
MN
2ASA
MA5
D3x
_BG
A324
MN
2ASA
MA5
D3x
_BG
A324
PA
0_LC
DD
AT0
E3
PA
1_LC
DD
AT1
F5P
A2_
LCD
DA
T2D
2P
A3_
LCD
DA
T3F4
PA
4_LC
DD
AT4
D1
PA
5_LC
DD
AT5
J10
PA
6_LC
DD
AT6
G4
PA
7_LC
DD
AT7
J9P
A8_
LCD
DA
T8F3
PA
9_LC
DD
AT9
J8P
A10
_LC
DD
AT1
0E
2P
A11
_LC
DD
AT1
1K
8P
A12
_LC
DD
AT1
2F2
PA
13_L
CD
DA
T13
G6
PA
14_L
CD
DA
T14
E1
PA
15_L
CD
DA
T15
H5
PA
16_L
CD
DA
T16
H3
PA
17_L
CD
DA
T17
H6
PA
18_L
CD
DA
T18
H4
PA
19_L
CD
DA
T19
H7
PA
20_L
CD
DA
T20
H2
PA
21_L
CD
DA
T21
J6P
A22
_LC
DD
AT2
2G
2P
A23
_LC
DD
AT2
3J5
PA
24_L
CD
PW
MF1
PA
25_L
CD
DIS
PJ4
PA
26_L
CD
VS
YN
CG
3P
A27
_LC
DH
SY
NC
J3P
A28
_LC
DP
CK
G1
PA
29_L
CD
DE
NK
4P
A30
_TW
D0
H1
PA
31_T
WC
K0
K3
R16
722
RR
167
22R
R48
100K
1%
R48
100K
1%
R14
222
RR
142
22R
R16
622
RR
166
22R
R15
622
RR
156
22R
R14
722
RR
147
22R
R50
100K
1%
R50
100K
1%
R15
722
RR
157
22R
R16
522
RR
165
22R
R14
822
RR
148
22R
JP5
JUM
PER
JP5
JUM
PER
1 2R
164
22R
R16
422
R
R49
100K
1%
R49
100K
1%
R14
522
RR
145
22R
R17
93.
3KR
179
3.3K
R13
3D
NP(
22R
)R
133
DN
P(22
R)
R13
422
RR
134
22R
MN
2BSA
MA5
D3x
_BG
A324
MN
2BSA
MA5
D3x
_BG
A324 PB
0_G
TX0
T2P
B1_
GTX
1N
7P
B2_
GTX
2T3
PB
3_G
TX3
N6
PB
4_G
RX
0P
5P
B5_
GR
X1
T4P
B6_
GR
X2
R4
PB
7_G
RX
3U
1P
B8_
GTX
CK
R5
PB
9_G
TXE
NP
3P
B10
_GTX
ER
R6
PB
11_G
RX
CK
V3
PB
12_G
RX
DV
P6
PB
13_G
RX
ER
V1
PB
14_G
CR
SR
7P
B15
_GC
OL
U3
PB
16_G
MD
CP
7P
B17
_GM
DIO
V2
PB
18_G
125C
KV
5P
B19
_GTX
4T6
PB
20_G
TX5
N8
PB
21_G
TX6
U4
PB
22_G
TX7
M7
PB
23_G
RX
4U
5P
B24
_GR
X5
M8
PB
25_G
RX
6T5
PB
26_G
RX
7N
9P
B27
V4
PB
28M
9P
B29
P8
PB
30M
10P
B31
R9
R17
83.
3KR
178
3.3K
R14
622
RR
146
22R
R52
100K
1%
R52
100K
1%
R13
622
RR
136
22R
R16
2D
NP(
22R
)R
162
DN
P(22
R)
R15
122
RR
151
22R
R13
922
RR
139
22R
MN
2DSA
MA5
D3x
_BG
A324
MN
2DSA
MA5
D3x
_BG
A324
PD
0K
5P
D1
P1
PD
2K
6P
D3
R1
PD
4L7
PD
5P
2P
D6
L8P
D7
R2
PD
8K
7P
D9
U2
PD
10K
9P
D11
M5
PD
12K
10P
D13
N4
PD
14L9
PD
15N
3P
D16
L10
PD
17N
5P
D18
M6
PD
19T1
PD
20N
2P
D21
M3
PD
22M
2P
D23
L3P
D24
M1
PD
25N
1P
D26
L1P
D27
L2P
D28
K1
PD
29K
2P
D30
J1P
D31
J2
R16
3D
NP(
22R
)R
163
DN
P(22
R)
R15
222
RR
152
22R
R14
022
RR
140
22R
R15
8D
NP(
22R
)R
158
DN
P(22
R)
MN
2GSA
MA5
D3x
_BG
A324
MN
2GSA
MA5
D3x
_BG
A324
D14
H16
D16
H18
D6
J12
D8
J14
D9
J16
D11
J17
D13
J18
NW
E_N
WR
0K
11
D0
K12
D4
K13
D2
K14
D1
K15
D3
K16
D5
K17
D7
K18
NC
S3
L12
NR
DL1
7
NA
ND
RD
YL1
8
D10
J13
D12
J15
R14
922
RR
149
22R
MN
6M
T29F
2G08
ABAE
AWP
MN
6M
T29F
2G08
ABAE
AWP
WE
18
N.C
66
VC
C37
CE
9
RE
8
N.C
1120
WP
19
N.C
55
N.C
11
N.C
22
N.C
33
N.C
44
DN
U1
21D
NU
222
N.C
1223
N.C
1324
R/B
7
I/O8_
N.C
26I/O
9_N
.C27
I/O10
_N.C
28
I/O0
29
VC
C_N
.C34
N.C
1435
VS
S36
DN
U3
38
VC
C_N
.C39
VC
C12
VS
S13
ALE
17
N.C
811
N.C
710
N.C
914
N.C
1015
CLE
16
VS
S_N
.C25
I/O11
_N.C
33
I/O1
30
I/O3
32I/O
231
I/O15
_N.C
47I/O
14_N
.C46
I/O13
_N.C
45
I/O7
44I/O
643
I/O5
42I/O
441
I/O12
_N.C
40
VS
S_N
.C48
R13
7D
NP(
22R
)R
137
DN
P(22
R)
R13
5D
NP(
22R
)R
135
DN
P(22
R)
R15
9D
NP(
22R
)R
159
DN
P(22
R)
C10
610
0nF
C10
610
0nF
2019 Microchip Technology Inc. DS50002884A-page 53
SAMA5D3 XPLAINED
Figure 4-45: SD and Micro-SD Interfaces5 5
4 4
3 3
2 2
1 1
DD
CC
BB
AA
VDD
IOP1
VDD
_MC
I0
VDD
IOP1
VDD
IOM
VDD
IOM
VDD
IOP1
PD1
[7]
PE2
[7]
PD9
[7]
PD0
[7]
PD4
[7]
PD3
[7]PE
0[7
]
PD6
[7]
PD7
[7]
PD8
[7]
PD5
[7]
PD2
[7]
PB20
[7]
PB21
[7]
PB22
[7]
PB23
[7]
PB19
[7]
PB24
[7]
PE1
[7]
RE
VD
ATE
MO
DIF
.D
ES
.D
ATE
VE
R.
SC
ALE
1/1
RE
V.
SH
EE
T
INIT
ED
ITAA
Rev
A
8 11A
XX-X
XX-X
XPP
nXX
X
HSM
CI
27-S
ep-1
3
SAM
A5D
3 Xp
lain
ed
19-F
eb-1
4Em
best
XXX
XX-X
XX-X
X
RE
VD
ATE
MO
DIF
.D
ES
.D
ATE
VE
R.
SC
ALE
1/1
RE
V.
SH
EE
T
INIT
ED
ITAA
Rev
A
8 11A
XX-X
XX-X
XPP
nXX
X
HSM
CI
27-S
ep-1
3
SAM
A5D
3 Xp
lain
ed
19-F
eb-1
4Em
best
XXX
XX-X
XX-X
X
RE
VD
ATE
MO
DIF
.D
ES
.D
ATE
VE
R.
SC
ALE
1/1
RE
V.
SH
EE
T
INIT
ED
ITAA
Rev
A
8 11A
XX-X
XX-X
XPP
nXX
X
HSM
CI
27-S
ep-1
3
SAM
A5D
3 Xp
lain
ed
19-F
eb-1
4Em
best
XXX
XX-X
XX-X
X
(MC
I0_C
D)
(MC
I0_W
P)
SD/M
MC
Plus
CA
RD
INTE
RFA
CE
- MC
I0
(MC
I0_D
A1)
(MC
I0_D
A0)
(MC
I0_C
K)
(MC
I0_C
DA)
(MC
I0_D
A3)
(MC
I0_D
A2)
(MC
I0_D
A4)
(MC
I0_D
A5)
(MC
I0_D
A7)
(MC
I0_D
A6)
(MC
I1_D
A1)
(MC
I1_C
K)(M
CI1
_CD
A)
(MC
I1_D
A3)
(MC
I1_D
A2)
(MC
I1_C
D)
(MC
I1_D
A0)
Mic
ro S
D C
AR
D IN
TER
FAC
E - M
CI1
C10
810
uFC
108
10uF
C11
010
uFC
110
10uF
R55
DN
P(4.
7K)
R55
DN
P(4.
7K)
R122 68KR122 68K
R18
222
RR
182
22R
R127 68KR127 68K
R18
322
RR
183
22R
J10
7SD
MM
-B0-
2211
J10
7SD
MM
-B0-
2211
8 57 6 4 3 2 1 9
141516 13 12 11 10
R54 10KR54 10K
R124 68KR124 68K
J11 DN
P(M
CTF
-040
3)
J11 DN
P(M
CTF
-040
3)
DA
T07
DA
T18
DA
T21
DA
T32
VD
D4
VS
S6
CD
9P
GN
D10
PG
ND
11P
GN
D12
PG
ND
13N
C14
NC
15
CM
D3
CLK
5
R53
100K
1%
R53
100K
1%
R129 68KR129 68KR
5910
KR
5910
K
R58 10KR58 10K
R130 68KR130 68K
R112 DNP(68K)R112 DNP(68K)
R57
0RR
570R
R126 68KR126 68K
R131 68KR131 68K
R132 68KR132 68K
R121 68KR121 68K
Q3
IRLM
L640
2Q
3IR
LML6
402
1
32
R123 68KR123 68K
R56
10K
R56
10K
R128 68KR128 68K
C11
110
0nF
C11
110
0nF
C10
910
0nF
C10
910
0nF
R125 68KR125 68K
DS50002884A-page 54 2019 Microchip Technology Inc.
SAMA5D3 XPLAINED
Figure 4-46: Gigabit Ethernet5 5
4 4
3 3
2 2
1 1
DD
CC
BB
AA
PB3
PB2
PB1
PB0
PB4
PB5
PB6
PB7
ETH
0_A+
ETH
0_A-
ETH
0_B-
ETH
0_C
+ET
H0_
C-
ETH
0_D
+ET
H0_
D-
PB16
PB11
PB13
PB9
PB17
PB10
ETH
0_LE
D2
XIXO
ETH
0_LE
D1
XI XOPB
18
PB8
ETH
0_B+
ETH
0_B-
ETH
0_D
+ET
H0_
D-
ETH
0_A+
ETH
0_A-
ETH
0_C
+ET
H0_
C-
ETH
0_LE
D1
ETH
0_LE
D2
ETH
0_B+
VDD
IOP1
DVD
DL
AVD
DL
AVD
DH
AVD
DL_
PLL
VDD
IOP1
VDD
IOP1
VDD
IOP1
VDD
IOP1
EAR
TH_E
TH0
ETH
0_G
ND
AVD
DH
VDD
IOP1
EAR
TH_E
TH0
ETH
0_G
ND
PB[0
..31]
[7,8
,10,
11]
NR
ST[4
,5,1
0,11
]
RE
VD
ATE
MO
DIF
.D
ES
.D
ATE
VE
R.
SC
ALE
1/1
RE
V.
SH
EE
T
INIT
ED
ITAA
Rev
A
9 11A
XX-X
XX-X
XPP
nXX
X
Ethe
rnet
_ETH
0_10
/100
/100
0
27-S
ep-1
3
SAM
A5D
3 Xp
lain
ed
19-F
eb-1
4Em
best
XXX
XX-X
XX-X
X
RE
VD
ATE
MO
DIF
.D
ES
.D
ATE
VE
R.
SC
ALE
1/1
RE
V.
SH
EE
T
INIT
ED
ITAA
Rev
A
9 11A
XX-X
XX-X
XPP
nXX
X
Ethe
rnet
_ETH
0_10
/100
/100
0
27-S
ep-1
3
SAM
A5D
3 Xp
lain
ed
19-F
eb-1
4Em
best
XXX
XX-X
XX-X
X
RE
VD
ATE
MO
DIF
.D
ES
.D
ATE
VE
R.
SC
ALE
1/1
RE
V.
SH
EE
T
INIT
ED
ITAA
Rev
A
9 11A
XX-X
XX-X
XPP
nXX
X
Ethe
rnet
_ETH
0_10
/100
/100
0
27-S
ep-1
3
SAM
A5D
3 Xp
lain
ed
19-F
eb-1
4Em
best
XXX
XX-X
XX-X
X
G12
5CK
GTX
0G
TX1
GTX
2G
TX3
GR
X0G
RX1
GR
X2G
RX3
GTX
CK
GTX
_CTL
GR
XCK
GR
X_C
TL
GM
DC
GM
DIO
INT_
GET
HR
ETH
010
Bas
e-T/
100B
ase-
TX/1
000B
ASE
-T
top/
bot
RG
MII
Rou
ting
Con
stra
ints
(Red
uced
Gig
abit
Med
ia In
depe
nden
t Int
erfa
ce):
The
RG
MII
sign
als
mus
t be
leng
th-m
atch
ed b
y TX
and
RX
gro
ups.
That
is, t
he T
X g
roup
sho
uld
be m
atch
ed w
ithin
0.2
5 in
ch (6
.35
mm
),an
d th
e R
X g
roup
sho
uld
be m
atch
ed w
ithin
0.2
5 in
ch (6
.35
mm
).To
tal l
engt
h sh
ould
not
exc
eed
1.75
inch
(44.
5 m
m).
Ther
e is
no
requ
irem
ent t
o m
atch
the
TX a
nd R
X g
roup
sbe
caus
e th
eir c
lock
s ar
e no
t rel
ated
.
top/
bot
top/
bot
top/
bot
top/
bot
top/
bot
top/
bot
top/
bot
top/
bot
top/
bot
top/
bot
LINK
ACT
Left
Gre
en L
ED
Righ
t Ye
llow
LED
R64
4.7K
R64
4.7K R68
22R
R68
22R
+C
127
10uF
+C
127
10uF
C11
220
pFC
112
20pF
R73
0RR
730R
R61
1KR
611K
C12
010
nFC
120
10nF
R67
4.7K
R67
4.7K
C13
610
nFC
136
10nF
+C
113
10uF
+C
113
10uF
Y3 25M
Hz
Y3 25M
Hz
1
2 3
4
C12
110
nFC
121
10nF
C13
510
nFC
135
10nF
C12
910
nFC
129
10nF
C12
4
100n
F
C12
4
100n
F
+C
126
10uF
+C
126
10uF
C11
620
pFC
116
20pF
R69
4.7K
R69
4.7K
C11
910
nFC
119
10nF
L17
180o
hm a
t 100
MH
zL1
718
0ohm
at 1
00M
Hz
12
C12
210
nFC
122
10nF
C11
510
nFC
115
10nF
R65
4.7K
R65
4.7K
C13
410
nFC
134
10nF
R71 470RR71 470R
C12
810
nFC
128
10nF
J12
48F-
01G
Y2D
PL2N
L
J12
48F-
01G
Y2D
PL2N
L
TD2+
3
TD1+
1TD
1-2
TD3+
7TD
3-8
RC
T6
TD2-
4
GR
LA11
GR
LC12
TD4+
9TD
4-10
TCT
5
YE
LC13
YE
LA14
GN
D15
GN
D16
GN
D17
GN
D18
C11
810
nFC
118
10nF
C11
410
nFC
114
10nF
C13
310
nFC
133
10nF
L18
180o
hm a
t 100
MH
zL1
818
0ohm
at 1
00M
Hz
12
R72 470RR72 470R
C12
310
nFC
123
10nF
KSZ9
031R
NI
48-p
in Q
FN
MN
10KS
Z903
1RN
KSZ9
031R
NI
48-p
in Q
FN
MN
10KS
Z903
1RN
VSS_PS 13
LED2 15DVDDH 16LED1 17
DVDDL 14
TXD0 19TXD1 20TXD2 21TXD3 22
DVDDL 18
DVDDL 23GTX_CLK 24
TX_E
N25
DV
DD
L26
RX
D3
27
VS
S29
DV
DD
L30
RX
D1
31R
XD
032
RX
_DV
33D
VD
DH
34R
X_C
LK35
MD
C36
MDIO37 INT_N38 DVDDL39 DVDDH40 CLK125_NDO41 RESET_N42 LDO_O43
XO45 XI46 AVDDH47 ISET48
AV
DD
H1
TXR
XP
_A2
TXR
XM
_A3
TXR
XP
_B5
TXR
XM
_B6
TXR
XP
_C7
TXR
XM
_C8
TXR
XP
_D10
TXR
XM
_D11
AV
DD
H12
RX
D2
28
AVDDL_PLL44
P_GND49
AV
DD
L4
AV
DD
L9
R66
4.7K
R66
4.7K
R63
12.1
K 1%
R63
12.1
K 1%
R11
1D
NP(
0R)
R11
1D
NP(
0R)
C13
810
nFC
138
10nF
C12
5
DN
P(10
uF 0
805)
C12
5
DN
P(10
uF 0
805)
R60
4.7K
R60
4.7K
+C
117
10uF
+C
117
10uF
C13
710
nFC
137
10nF
R70
22R
R70
22R
+C
132
10uF
+C
132
10uF
R62
22R
R62
22R
2019 Microchip Technology Inc. DS50002884A-page 55
SAMA5D3 XPLAINED
Figure 4-47: Ethernet 10/1005 5
4 4
3 3
2 2
1 1
DD
CC
BB
AA
ETH
1_XO
ETH
1_XI
ETH
1_XO
ETH
1_XI
ETH
1_LE
D0
ETH
1_LE
D0
TX+
TX+
TX-
RX+
RX-
RX-
RX+
TX-
ETH
1_LE
D1
ETH
1_LE
D1
VDD
IOP1
VDD
IOP0
VDD
IOP0
E1_A
VDD
T
VDD
IOP0
EAR
TH_E
TH1
EAR
TH_E
TH1
GN
D_E
TH1
VDD
IOP0
EAR
TH_E
TH1
GN
D_E
TH1
VDD
IOP0
NR
ST[4
,5,9
,11]
ETH
1_PC
2[7
]ET
H1_
PC3
[7]
ETH
1_PC
0[7
]
ETH
1_PC
5[7
]ET
H1_
PC6
[7]
ETH
1_PC
7[7
]
ETH
1_PC
4[7
]
ETH
1_PC
8[7
]ET
H1_
PC9
[7]
PB12
[7]
ETH
1_PC
1[7
]
RE
VD
ATE
MO
DIF
.D
ES
.D
ATE
VE
R.
SC
ALE
1/1
RE
V.
SH
EE
T
INIT
ED
ITAA
Rev
A
10 11A
XX-X
XX-X
XPP
nXX
X
Ethe
rnet
_ETH
1_10
/100
27-S
ep-1
3
SAM
A5D
3 Xp
lain
ed
19-F
eb-1
4Em
best
XXX
XX-X
XX-X
X
RE
VD
ATE
MO
DIF
.D
ES
.D
ATE
VE
R.
SC
ALE
1/1
RE
V.
SH
EE
T
INIT
ED
ITAA
Rev
A
10 11A
XX-X
XX-X
XPP
nXX
X
Ethe
rnet
_ETH
1_10
/100
27-S
ep-1
3
SAM
A5D
3 Xp
lain
ed
19-F
eb-1
4Em
best
XXX
XX-X
XX-X
X
RE
VD
ATE
MO
DIF
.D
ES
.D
ATE
VE
R.
SC
ALE
1/1
RE
V.
SH
EE
T
INIT
ED
ITAA
Rev
A
10 11A
XX-X
XX-X
XPP
nXX
X
Ethe
rnet
_ETH
1_10
/100
27-S
ep-1
3
SAM
A5D
3 Xp
lain
ed
19-F
eb-1
4Em
best
XXX
XX-X
XX-X
X
10B
ase-
T/10
0Bas
e-TX
ETH
1
top/
bot
top/
bot
top/
bot
top/
bot
ACT
LINK
+C
148
10uF
+C
148
10uF
L19
180o
hm a
t 100
MH
zL1
918
0ohm
at 1
00M
Hz
12
MN
9
KSZ8
081R
NB
MN
9
KSZ8
081R
NBR
XC
/B-C
AS
T_O
FF19
CR
S/C
ON
FIG
129
CO
L/C
ON
FIG
028
TXD
125
TXD
024
TXE
N23
RX
D3/
PH
YA
D0
13R
XD
2/P
HY
AD
114
RX
D1/
PH
YA
D2
15R
XD
0/D
UP
LEX
16R
XD
V/C
ON
FIG
218
RX
ER
/ISO
20
MD
C12
MD
IO11
INTR
P/N
AN
D21
VD
DA
_3V
33
VD
DIO
17
RE
SE
T32
TXP
7
TXM
6
RX
P5
RX
M4
VD
D_1
V2
2
GN
D1
PA
DD
LE33
TXC
22TX
D2
26TX
D3
27R
EX
T10
XO
8
XI
9
LED
0/N
WA
YE
N30
LED
1/S
PE
ED
31
R116 10KR116 10K
+C
146
10uF
+C
146
10uF
R120 10KR120 10K
+C
144
10uF
+C
144
10uF
C13
910
0nF
C13
910
0nF
R114 10KR114 10K
R115 10KR115 10K
C14
720
pFC
147
20pF
C14
010
0nF
C14
010
0nF
C14
12.
2uF
C14
12.
2uF
R79
470R
R79
470R
Y4 25M
Hz
Y4 25M
Hz
1
2 3
4
C14
210
0nF
C14
210
0nF
R80
470R
R80
470R
C14
9 20pF
C14
9 20pF
R76
6.49
K 1%
R76
6.49
K 1%
C14
310
0nF
C14
310
0nF
R75
1KR75
1K
C14
510
0nF
C14
510
0nF
R74
1KR74
1K
R113 10KR113 10K
R81
0RR
810R
R78
10K
R78
10K
L20
180o
hm a
t 100
MH
zL2
018
0ohm
at 1
00M
Hz
12
R117 10KR117 10K
R77
10K
R77
10K
R118 10KR118 10K
R119 10KR119 10K
1 2 3 6 4 5 7 8
75 75
7575
1nF
TD+
TD-CT NCRD-CT
TX+
TX-
RX+
RX-
RD+
Left
Gre
en L
ED
Righ
t ye
llow
LED
J13
13F-
64G
YD2P
L2N
L
1 2 3 6 4 5 7 8
75 75
7575
1nF
TD+
TD-CT NCRD-CT
TX+
TX-
RX+
RX-
RD+
Left
Gre
en L
ED
Righ
t ye
llow
LED
J13
13F-
64G
YD2P
L2N
L
1 2 7 83 654
9
10
11
12
13 14 15 16
DS50002884A-page 56 2019 Microchip Technology Inc.
SAMA5D3 XPLAINED
Figure 4-48: LCD, JTAG, DEBUG and Extended Connectors5 5
4 4
3 3
2 2
1 1
DD
CC
BB
AA
AREF
PC25
PC28
PC30
PC29
PE19
PE18
PB29
PB28
PD18
PD17
PC18
PD20
PD21
PD22
PD23
PD24
PD25
PD26
PD27
PC20
PD28
PC21
PD29
PD30
PC19
PB3
PB2
PB1
PB0
PB13
PB12
PB8
PB9
PB4
PB5
PB6
PB7
PB28
PB16
PB17
PB18
PB10
PB11
PB15
PB14
PB26
PB19
PB23
PB22
PB21
PB20
PB25
PB24
PB29
PB30
PB31
PB27
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
PA8
PA9
PA10
PA11
PA15
PA14
PA13
PA12
PA16
PA17
PA18
PA19
PA23
PA22
PA21
PA20
PA25
PA24
PA28
PA29
PA30
PA31
PA27
PA26
PC3
PC2
PC1
PC0
PC13
PC12
PC8
PC9
PC4
PC5
PC6
PC7
PC28
PC16
PC17
PC18
PC10
PC11
PC15
PC14
PC26
PC19
PC23
PC22
PC21
PC20
PC25
PC24
PC29
PC30
PC31
PC27
PD13
PD12
PD8
PD9
PD4
PD5
PD6
PD7
PD28
PD16
PD17
PD18
PD10
PD11
PD15
PD14
PD26
PD19
PD23
PD22
PD21
PD20
PD25
PD24
PD29
PD30
PD31
PD27
PD3
PD2
PD1
PD0
PD31
PB14
PD14
PD15
PD30PC17PB26
PC16
PB27PB25
PE9PA17PA19PA21PA23
PE11PE17PE15
PE23
PE13PE29
PE25
PE10
PA20PA18PA16
PE16PE20PE12
PA22
PB15PE31PE14
PE24PE26
PE30
PE21
PE31
PE24
PE25
PE22
PE27
PE28
PE29
PE15
PE23
PE26
PE1
PE2
PE3
PE4
PE5
PE6
PE14
PE7
PE8
PE9
PE0
PE10
PE11
PE12
PE13
PE20
PE16
PE17
PE18
PE19
5V_E
xt
5V_E
xt
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
PA8
PA9
PA10
PA11
PA15
PA14
PA13
PA12
PA25
PA24
PC13
PC12
PC11
PC14
PC10
PC15
PE27
PE28
PA29
PA27
PA26
PE8
PE7
TWD
_LC
DTW
CK_
LCD
PE23
PD10
PD11
PD12
PD16
PD20
PD21
PD22
PD23
PE6
NR
ST
TCK
TMS
RTC
K
TDI
TDO
PC15
PC26
TWC
K_LC
DTW
D_L
CD
PC22PC24 PC23
5V_E
xt
PE13
PE14
PA28
NR
ST
PD19
PB15
3V3
3V3
5V_M
AIN
3V3
VDD
IOP0
5V_M
AIN
3V3
3V3
3V3
PB[0
..31]
[7,8
,9,1
0]
PA[0
..31]
[7]
PC[0
..31]
[4,7
]
PD[0
..31]
[7,8
]
PE[0
..31]
[4,5
,7,8
]
NR
ST[4
,5,9
,10]
J15_
Pin6
[7]
J15_
Pin5
[7]
J15_
Pin4
[7]
J15_
PC3
[7]
J15_
PC4
[7]
J18_
PC5
[7]
J18_
PC6
[7]
J18_
PC7
[7]
J18_
PC8
[7]
J18_
PC9
[7]
AREF
[5]
PB31
[7]
PB30
[7]
VBat
[5]
5V_E
xt[4
]
NR
ST[4
,5,9
,10]
TDO
[5]
TDI
[5]
TCK
[5]
TMS
[5]
NTR
ST[5
]
J15_
TWC
K[7
]J1
5_TW
D[7
]
TWD
_ISI
[7]
TWC
K_IS
I[7
]
TWC
K_LC
D[7
]TW
D_L
CD
[7]
RE
VD
ATE
MO
DIF
.D
ES
.D
ATE
VE
R.
SC
ALE
1/1
RE
V.
SH
EE
T
INIT
ED
ITAA
Rev
A
11 11A
XX-X
XX-X
XPP
nXX
X
Con
nect
ors
27-S
ep-1
3
SAM
A5D
3 Xp
lain
ed
19-F
eb-1
4Em
best
XXX
XX-X
XX-X
X
RE
VD
ATE
MO
DIF
.D
ES
.D
ATE
VE
R.
SC
ALE
1/1
RE
V.
SH
EE
T
INIT
ED
ITAA
Rev
A
11 11A
XX-X
XX-X
XPP
nXX
X
Con
nect
ors
27-S
ep-1
3
SAM
A5D
3 Xp
lain
ed
19-F
eb-1
4Em
best
XXX
XX-X
XX-X
X
RE
VD
ATE
MO
DIF
.D
ES
.D
ATE
VE
R.
SC
ALE
1/1
RE
V.
SH
EE
T
INIT
ED
ITAA
Rev
A
11 11A
XX-X
XX-X
XPP
nXX
X
Con
nect
ors
27-S
ep-1
3
SAM
A5D
3 Xp
lain
ed
19-F
eb-1
4Em
best
XXX
XX-X
XX-X
X
LCD
Con
nect
or
DEB
UG
JTA
G
(ID_S
YS)
(SPI
0_SP
CK)
(SPI
0_M
OSI
)
(SPI
0_M
ISO
)
(SPI
0_N
PCS3
)
(AD
0)
(AD
1)
(AD
2)
(AD
3)
(TXD
)
(RST
_LC
D)
(LC
DD
AT0)
(LC
DD
AT1)
(LC
DD
AT2)
(LC
DD
AT3)
(LC
DD
AT4)
(LC
DD
AT5)
(LC
DD
AT6)
(LC
DD
AT7)
(LC
DD
AT8)
(LC
DD
AT9)
(LC
DD
AT10
)(L
CD
DAT
11)
(LC
DD
AT12
)(L
CD
DAT
13)
(LC
DD
AT14
)(L
CD
DAT
15)
(LC
DD
AT16
)(L
CD
DAT
17)
(LC
DD
AT18
)(L
CD
DAT
19)
(LC
DD
AT20
)(L
CD
DAT
21)
(LC
DD
AT22
)(L
CD
DAT
23)
(LC
DPC
K)
(LC
DVS
YNC
)(L
CD
HSY
NC
)(L
CD
DEN
)
(LC
DD
ISP)
(LC
DPW
M)
(IRQ
2)IR
Q1)
Exte
nsio
nbo
ard
conn
ecto
rs
(RXD
)
TXD3
RXD3
RXD1
TWCK
1
TXD1
RXD0
TXD0
TWD1
AD8
CANR
X0
AD9
AD10
CANR
X1
CANT
X0
URXD
0UT
XD0
AD0
AD1
AD4
AD2
AD3
AD6
AD5
AD7
SPI1
_MOS
I
SPI1
_MIS
OSP
I1_S
PCK
PA31
PA30
PC26
PC27
TWCK
0TW
D0
ETX0
ETX1
ERX0
SPI1
_NPC
S0ER
X1ET
XEN
SPI1
_NPC
S3
R10
122
RR
101
22R
J14
FH25
43-0
8GT1
0
J14
FH25
43-0
8GT1
0
1 2 3 4 5 6 7 8
R190 68KR190 68K
R10
322
RR
103
22RR
168
DN
P(0R
)
R16
8
DN
P(0R
)
R93
0RR
930R
R10
610
0K 1
%R
106
100K
1%
R169 DNP(0R)R169 DNP(0R)
J23
P101
-1*0
6SG
F-11
6A-N
X
J23
P101
-1*0
6SG
F-11
6A-N
X
1 2 3 4 5 6
R170 DNP(0R)R170 DNP(0R)
R89
DN
P(0R
)R
89D
NP(
0R)
J24
P101
-2*1
0SG
F-11
6A-N
X
J24
P101
-2*1
0SG
F-11
6A-N
X
12
34
56
78
910
1112
13 15 17 19
14 16 18 20
J18
FH25
43-0
8GT1
0
J18
FH25
43-0
8GT1
0
1 2 3 4 5 6 7 8
J19
JT25
4-D
S180
-850
-218
-001
J19
JT25
4-D
S180
-850
-218
-001
1 23 45 67 89 1011 1213151719
14161820
21 2223 2425 2627 2829 3031 3233 3435 36
R17
30R
R17
30R
R10
510
0K 1
%R
105
100K
1%
R10
2D
NP(
0R)
R10
2D
NP(
0R)
R85
DN
P(0R
)R
85D
NP(
0R)
R171 DNP(0R)R171 DNP(0R)
R10
0D
NP(
0R)
R10
0D
NP(
0R)
R18
422
RR
184
22R
R99
DN
P(0R
)R
99D
NP(
0R)
J21
FH25
43-0
8GT1
0
J21
FH25
43-0
8GT1
0
1 2 3 4 5 6 7 8
R91
0RR
910R
R18
70R
R18
70R
R17
40R
R17
40R
J15
FH25
43-1
0GT1
0
J15
FH25
43-1
0GT1
0
12345678910
J16
P101
-2*0
3SG
F-11
6A-N
X
J16
P101
-2*0
3SG
F-11
6A-N
X
1 23 45 6
R10
80R
R10
80R
R189 68KR189 68K
R84
DN
P(0R
)
R84
DN
P(0R
)
J22
FP52
0T1-
50SR
04
J22
FP52
0T1-
50SR
04
1234567891011121314151617181920212223242526272829303132333435363738394041424344454647484950
52 51
R10
410
0K 1
%R
104
100K
1%
R88
0RR
880R
J20
FH25
43-0
8GT1
0
J20
FH25
43-0
8GT1
0
1 2 3 4 5 6 7 8
R92
DN
P(0R
)R
92D
NP(
0R)
R90
DN
P(0R
)R
90D
NP(
0R)
R10
90R
R10
90R
R94
0RR
940R
R86
0RR
860R
R87
DN
P(0R
)R
87D
NP(
0R)
J17
FH25
43-0
8GT1
0
J17
FH25
43-0
8GT1
0
1 2 3 4 5 6 7 8
R96
22R
R96
22R
R172 DNP(0R)R172 DNP(0R)
R83 0RR83 0R
R10
7
100K
1%
R10
7
100K
1%
R98
DN
P(0R
)R
98D
NP(
0R)
R97
22R
R97
22R
R11
00R
R11
00R
R82
0RR
820R
R95
DN
P(0R
)R
95D
NP(
0R)
R18
8D
NP(
0R)
R18
8D
NP(
0R)
See
Err
ata
sect
ion
2019 Microchip Technology Inc. DS50002884A-page 57
SAMA5D3 XPLAINED
5. Errata
5.1 The SPI lines available on the LCD connector J22 have been swapped.
Current implementation (wrong):
• Pin 37 = SPI0_NPCS3• Pin 38 = SPI0_MISO• Pin 39 = SPI0_MOSI• Pin 40 = SPI0_SPCK
Correct implementation:
• Pin 37 = SPI0_SPCK• Pin 38 = SPI0_MOSI• Pin 39 = SPI0_MISO• Pin 40 = SPI0_NPCS3
To date, there is no impact because no LCD screen available on the market uses the SPI bus on this connector, in particular the PDA Inc.TM430x and TM700x product series recommended by Microchip.
A potential problem exists only if the future "Xplained Pro" series LCD extensions are used because these extensions could require theSPI bus on this LCD connector.
Also, for customers or third parties planning to develop their own extensions using a connection to J22, we strongly recommend followingthe correct implementation so as to ensure future consistency and compatibility with all Microchip tools.
Workaround:
1. Unsolder and remove resistors R96, R97, R101 andR103 located here:
2. Solder isolated pieces of wire as follows.Resin coated wires were used below. Make sure not to create any short-circuits between thewires and the other components.
DS50002884A-page 58 2019 Microchip Technology Inc.
SAMA5D3 XPLAINED
5.2 JP1 routing is incorrect and results in inaccurate VDDCORE current measurement
The jumper JP1 was incorrectly routed on the SAMA5D3 Xplained board. As a result, the on-board connections on the left and right sidesof the jumper do not match the schematics and VDDCORE current measurement is incorrect.
Workaround:
1. Locate C13, L7 and JP1 on the SAMA5D3 Xplained board.
2. On the top side, cut the track between pins 1 and 2 of JP1.
3. On the top side, solder a 2-pin header in the JP1 footprint.
C13, L7 and JP1 located on the bottom side JP1 located on the top side
Before After
2019 Microchip Technology Inc. DS50002884A-page 59
SAMA5D3 XPLAINED
4. On the bottom side, cut the large track between C13 and L7.
5. Unsolder C13 and re-solder it across the cut made in Step 3, directly to L7.
Before After
Zoom
C13 Removed C13 Re-soldered
DS50002884A-page 60 2019 Microchip Technology Inc.
SAMA5D3 XPLAINED
6. Solder a wire between the top pad of L7 and pin 1 of JP1.
7. To complete the procedure, either:
a) install a jumper across both JP1 pins for normal operation,
or
b) remove the jumper and connect an ammeter across both JP1 pins to measure VDDCORE current.
5.3 The TWI1 pull-up charge is excessive.
The pull-up charge on TWI1 data and clock lines is a bit too high and out of I²C specification.
Workaround:
Although the board proves to be functional as is, we recommend fixing this excessive pull-up charge by removing resistors R178 andR179. These are located near the J17 connector and an Atmel logo, as shown in the following figure:
Figure 5-1: Position of R178 and R179
2019 Microchip Technology Inc. DS50002884A-page 61
SAMA5D3 XPLAINED
DS50002884A-page 62 2019 Microchip Technology Inc.
6. Revision History
Table 6-1: SAMA5D3 Xplained User Guide Revision History
Doc. Rev. Changes
DS50002884A
Section 4.2.3 “Power Supplies”: added Warning on engineering version.
General- Template update: Moved from Atmel to Microchip template.- The user’s guide is assigned a new document number (DS50002884) and revision letter is reset to A.--- Document number DS50002884 revision A corresponds to what would have been 11269 revision E- ISBN number assigned.
11269D “Errata” section: added Section 5.3 “The TWI1 pull-up charge is excessive.”
11269C
Inserted Table 4-1 “SAMA5D3 Xplained Board Interface Connectors”.
Section 4.3.1 “Power Supply”: added WARNING on known error on ACT8865 I²C implementation.
Added Section 5.2 “JP1 routing is incorrect and results in inaccurate VDDCORE current measurement”
11269B
Added “Errata” .
Added references to “Errata” in Figure 4-17 on page 19 and Figure 4-48 on page 57 and in Table 4-22, “LCD Socket J22 Signal Descriptions,” on page 39 (added note 1)
11269A First issue.
2019 Microchip Technology Inc. DS50002884A-page 63
SAMA5D3 XPLAINED
The Microchip Web Site
Microchip provides online support via our web site at www.microchip.com. This web site is used as a means to makefiles and information easily available to customers. Accessible by using your favorite Internet browser, the web sitecontains the following information:
• Product Support – Data sheets and errata, application notes and sample programs, design resources, user’s guides and hardware support documents, latest software releases and archived software
• General Technical Support – Frequently Asked Questions (FAQ), technical support requests, online discussion groups, Microchip consultant program member listing
• Business of Microchip – Product selector and ordering guides, latest Microchip press releases, listing of seminars and events, listings of Microchip sales offices, distributors and factory representatives
Customer Change Notification Service
Microchip’s customer notification service helps keep customers current on Microchip products. Subscribers will receivee-mail notification whenever there are changes, updates, revisions or errata related to a specified product family ordevelopment tool of interest.
To register, access the Microchip web site at www.microchip.com. Under “Design Support”, click on “Customer ChangeNotification” and follow the registration instructions.
Customer Support
Users of Microchip products can receive assistance through several channels:
• Distributor or Representative
• Local Sales Office
• Field Application Engineer (FAE)
• Technical Support
Customers should contact their distributor, representative or Field Application Engineer (FAE) for support. Local salesoffices are also available to help customers. A listing of sales offices and locations is included in the back of thisdocument.
Technical support is available through the web site at: http://microchip.com/support
SAMA5D3 XPLAINED
Microchip Devices Code Protection Feature
Note the following details of the code protection feature on Microchip devices:
• Microchip products meet the specification contained in their particular Microchip Data Sheet.
• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions.
• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
• Microchip is willing to work with the customer who is concerned about the integrity of their code.
• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of ourproducts. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such actsallow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Legal Notice
Information contained in this publication regarding device applications and the like is provided only for your convenience and may besuperseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NOREPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OROTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE,MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use ofMicrochip devices in life support and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend, indemnify andhold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implic-itly or otherwise, under any Microchip intellectual property rights unless otherwise stated.
Trademarks
The Microchip name and logo, the Microchip logo, AnyRate, AVR, AVR logo, AVR Freaks, BitCloud, chipKIT, chipKIT logo, CryptoMemory, CryptoRF, dsPIC, FlashFlex, flexPWR, Heldo, JukeBlox, KeeLoq, Kleer, LANCheck, LINK MD, maXStylus, maXTouch, MediaLB, megaAVR, MOST, MOST logo, MPLAB, OptoLyzer, PIC, picoPower, PICSTART, PIC32 logo, Prochip Designer, QTouch, SAM-BA, SpyNIC, SST, SST Logo, SuperFlash, tinyAVR, UNI/O, and XMEGA are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.
ClockWorks, The Embedded Control Solutions Company, EtherSynch, Hyper Speed Control, HyperLight Load, IntelliMOS, mTouch, Precision Edge, and Quiet-Wire are registered trademarks of Microchip Technology Incorporated in the U.S.A.
Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Any Capacitor, AnyIn, AnyOut, BodyCom, CodeGuard, CryptoAuthentication, CryptoAutomotive, CryptoCompanion, CryptoController, dsPICDEM, dsPICDEM.net, Dynamic Average Matching, DAM, ECAN, EtherGREEN, In-Circuit Serial Programming, ICSP, INICnet, Inter-Chip Connectivity, JitterBlocker, KleerNet, KleerNet logo, memBrain, Mindi, MiWi, motorBench, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient Code Generation, PICDEM, PICDEM.net, PICkit, PICtail, PowerSmart, PureSilicon, QMatrix, REAL ICE, Ripple Blocker, SAM-ICE, Serial Quad I/O, SMART-I.S., SQI, SuperSwitcher, SuperSwitcher II, Total Endurance, TSHARC, USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated in the U.S.A.
Silicon Storage Technology is a registered trademark of Microchip Technology Inc. in other countries.
GestIC is a registered trademark of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., inother countries.
All other trademarks mentioned herein are property of their respective companies.
© 2019, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved.
ISBN: 978-1-5224-4471-8
AMBA, Arm, Arm7, Arm7TDMI, Arm9, Arm11, Artisan, big.LITTLE, Cordio, CoreLink, CoreSight, Cortex, DesignStart, DynamIQ,Jazelle, Keil, Mali, Mbed, Mbed Enabled, NEON, POP, RealView, SecurCore, Socrates, Thumb, TrustZone, ULINK, ULINK2, ULINK-ME, ULINK-PLUS, ULINKpro, µVision, Versatile are trademarks or registered trademarks of Arm Limited (or its subsidiaries) in the USand/or elsewhere.
2019 Microchip Technology Inc. DS50002884A-page 64
SAMA5D3 XPLAINED
Quality Management System Certified by DNV
ISO/TS 16949
Microchip received ISO/TS-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandlerand Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and pro-cedures are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatilememory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO9001:2000 certified.
DS50002884A-page 65 2019 Microchip Technology Inc.
DS50002884A-page 66 2019 Microchip Technology Inc.
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