Running OPAL-RT’s eHS on National Instruments cRIO: … ·  · 2018-01-31Running OPAL-RT’s eHS...

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The 7th International Conference on Real-Time Simulation Technologies Montreal | 9-12 June, 2014 1 Ben Black Market Development Manager, Real-Time Test & Power Systems National Instruments [email protected] Running OPAL-RT’s eHS on National Instruments cRIO: Sub-microsecond power-electronic simulation Pierre-Yves Robert FPGA Specialist, OPAL-RT TECHNOLOGIES Inc. [email protected]

Transcript of Running OPAL-RT’s eHS on National Instruments cRIO: … ·  · 2018-01-31Running OPAL-RT’s eHS...

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Ben Black Market Development Manager, Real-Time Test & Power Systems National Instruments [email protected]

Running OPAL-RT’s eHS on National Instruments cRIO: Sub-microsecond power-electronic simulation

Pierre-Yves Robert FPGA Specialist, OPAL-RT TECHNOLOGIES Inc. [email protected]

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National Instruments | Our Mission

We equip engineers and scientists with tools that accelerate productivity, innovation, and discovery.

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Our Stability Annual Revenue: $1.17 billion

Global Operations: Approximately 7,100 employees; operations in almost 50 countries

Broad Customer Base: More than 35,000 companies served annually

Diversity: No industry >15% of revenue

Culture: Ranked among the top 25 companies to work worldwide by the Great Place to Work Institute

Strong Cash Position: Cash and short-term investments of $393 million at December 31, 2013

R&D Investment: Roughly 16% of revenue invested back in R&D

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The Benefits of Off-the-Shelf Technology With the Flexibility of Custom Design

Why compromise? The NI approach delivers the benefits of custom design with quality off-the-shelf products so you can focus on INNOVATION not IMPLEMENTATION

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The Benefits of Off-the-Shelf Technology With the Flexibility of Custom Design

High-Level Software

Flexible Hardware

Integrated Hardware and Software Platform

Benefits

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Graphical System Design A platform-based approach for measurement and control

Applications

Deployable Targets

Commercial Technology

Models of Computation, User Interface

Math and Analysis

Measurement and Control I/O

Timing

Connectivity With Third-Party I/O

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Graphical System Design A platform-based approach for measurement and control

Applications

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Project Explorer Manage and organize all

system resources, including I/O and deployment targets

Front Panel Create event-driven user

interfaces to control systems and display measurements

Block Diagram Define and customize the behavior of your system using graphical programming

Instant Compilation See the state of

your application at all times, instantly

Parallel Programming Create independent loops that automatically execute in parallel

Analysis Libraries Use high-performance analysis libraries designed for engineering and science

Hardware Connectivity Bring real-world signals into LabVIEW from any I/O on any instrument

Timing Define explicit execution order and timing with sequential data flow

Deployment Targets Deploy LabVIEW code to the

leading desktop, real-time, and FPGA hardware targets

Models of Computation Combine and reuse .m files, C code, and HDL with graphical

code

LabVIEW System Design Software

Accelerates Your Success By abstracting low-level complexity and integrating all of the tools you need to build any measurement or control system

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The NI Approach to Flexible Hardware

We call this the LabVIEW RIO Architecture.

Commercial Technology

Highly Productive LabVIEW Graphical Programming Environment for Programming Host, FPGA, I/O, and Bus Interfaces

Processor Real-Time or

PC-Based FPGA Modular I/O

for Any Signal

Processor

Real-time OS Application software Networking and

peripheral I/O drivers DMA, interrupt, and

bus control drivers

FPGA Application IP Control IP DSP IP Specialized I/O drivers

and interface DMA controller

Analog I/O

Digital I/O

Specialized I/O

Custom I/O

Bus Protocols

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NI CompactRIO

Processor Modular I/O

FPGA

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NI CompactRIO

Processor Modular I/O

Highly Productive LabVIEW Graphical Programming Environment for Programming Host, FPGA, I/O, and Bus Interfaces

Extreme Ruggedness: -40 to 70 °C temperature range; 50 g shock, 5 g vibration High Performance: Up to 1.33 GHz, dual-core i7 processor Comprehensive I/O: Analog, digital, custom, specialty, bus communication

FPGA

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667 MHz Dual-Core ARM Cortex-A9 processor 28K Logic Cells (Artix-7) 80 DSP slices, 16 DMA channels 92 Billion calculations per second

Xilinx ZYNQ

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NI myRIO – Control Platform All programmable SoC

Express VIs for ease-of-use

Rich, Known I/O

Extensive Ecosystem

WiFi & Tablet Ready

LabVIEW unleashed

C/C++ Programmable

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NI myRIO | Courseware

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OPAL-RT IP + LabVIEW + CompactRIO for HIL

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OPAL-RT + CompactRIO for HIL

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Design “V” Teaching Platform

myRIO for control paired with: • Inverter research board (real plant) • NI / Opal-RT HIL Trainer (simulated plant)

Inverter Research Board

6 DIO Vabc PWM

Feedback

NI / Opal-RT HIL Trainer

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First demonstration: Diode-Bridge Rectifier This circuit simulates a three-phase voltage rectifier with various loads.

Teaching objectives: • To introduce the student with the

simulation tools • To understand the operating principles of

a diode-bridge rectifier • To highlight the effect of the load type

and value on the output voltage ripple

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Second demonstration: Boost Converter This circuit simulates a DC-DC Boost converter with various loads.

Teaching objectives: • To understand the operating principles of a

boost converter • To observe and understand the effect of the

load type and value on the boost output voltage

• To find the S1 switching duty cycle marking the delimitation between continuous and discontinuous operation modes.

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Third demo: Boost with external controller We connect the Boost converter to an external controller.

Teaching objectives: • To introduce the student with

closed-loop control, including wire connections

• To design from scratch a PI controller adapted for a boost converter

• To find the suited controller parameters according to load characteristics

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What is eHS ? • This approach uses the modified nodal

analysis.

• It solves the conductance matrix of the network to find the voltage at each node and the current from each sources.

• The conductance matrix is loaded into the solver when the model is deployed.

• The simulated model can be modified without recompiling the bitfile.

Graphical circuit design and offline simulation

Automatic analysis of the circuit netlist and generation

of the conductance matrix

FPGA-based simulation on circuit-independent

firmware

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Integration of eHS into the LabVIEW environment • The eHS tool will be included as a

module of LabVIEW.

• Exercises will be provided with pre-compiled bitfiles for the FPGA firmware.

• To accommodate different I/O configurations, custom bitfiles can be generated using LabVIEW FPGA.

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Modifying the simulated circuit To modify the component values in a circuit, the student generally chooses from a list of pre-defined scenarios. eHS matrices are pre-generated to match these scenarios.

• In general, this is done in a LabVIEW control panel provided him by the teaching assistant.

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Modifying the simulated circuit Alternatively, the student could use a standard schematic editor, and re-compile the corresponding conductance matrix.

• At the time being, this is done within the Matlab environment.

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Creating new exercises A professor may want to modify scenarios, create new ones, or even create exercises based on completely different circuit topologies

• The new circuit can be designed with his favorite schematic editor

• LabVIEW provides full access to the control panel for scenario control.

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eHS: Computation time On the cRIO, the eHS feature uses a 160-MHz clock.

• This enables very small computation step sizes, in general between 125 ~ 500 ns. • Computation step sizes depends on the circuit complexity and the number of scenarios implemented. • Loop rate of the Boost Converter model is 3.33 MHz (300 ns). • Loop rate of the Diode-Bridge Rectifier model is 2.16 MHz (460 ns). • Loop rate of the Buck Converter model is 7.27 MHz (140 ns). • Loop rate of the 3-Phase Inverter model is 2.38 MHz (420 ns).

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eHS: Hardware-in-the-Loop simulation timing

When eHS is connected to an external plant or controller, the total loop time must include I/O latency

In this case, the loop time is not critical, but the Boost model and digital lines still need to run fast to accommodate fast-switching PWM controls.

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eHS: Supported Circuit editors

As of today, the eHS circuit can be described with one of the following tools:

• SimPowerSystem Toolbox for Simulink • PLECS • PSIM

Development is planned for the following tools:

• Multisim • EMTP-RV

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RUNNING OPAL-RT’S eHS ON NATIONAL INSTRUMENTS cRIO: SUB-MICROSECOND POWER-ELECTRONIC SIMULATION

• By running Opal-RT’s eHS on a National Instruments cRIO platform, the simulation of power-electronic circuits can be performed at sub-microsecond sample times.

• The low cost of the eHS-cRIO solution makes it suitable as a model-based test bench in an undergraduate educational lab equipment.

• The flexibility of the eHS-cRIO solution enables a full hardware-in-the-loop solution with loop times in the order of tens of microseconds.

• Opal-RT can provide a variety of models suited for educational purposes, such as DC-DC converters, Inverters, Rectifiers, etc.

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The 7th International Conference on Real-Time Simulation Technologies Montreal | 9-12 June, 2014

Appendices

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The 7th International Conference on Real-Time Simulation Technologies Montreal | 9-12 June, 2014 eHS: PEJOVIC METHOD

• The Pejovic method models switches by either an inductor when conducting or a capacitor when blocking in the nodal matrix.

• This method is called the fix-Y because the conductance matrix does not change when a switch changes state.

• When using the modified nodal analysis the main difference between an inductance and a capacitor is in their discretization and in their historical term. Once discretized, the equivalent circuit is a current source with a shunt resistance.