© 2013 VARIAN MEDICAL SYSTEMS. ALL RIGHTS RESERVED.

PLEXIGLAS PROJECTRohit L. GawaliMS Electrical and Computer Engg.University of Utah

08/05/2015

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• Legos FCT glass testing is an improvement for the testing systems.

• Varian will receive a greater proportion of defect-free glass from vendors.

• Improved panel quality.• Reduced scrap.• Lower cost per panel.

Project Background

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Legos Full Contact Tester

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• To be able to test the tester board electronics without the glass sample being there.

• This will help in reducing the lead time on testing the glass.

• To understand the different noise components on the tester circuit and try and reduce it down

• In turn try to increase the quality of the image.

Problem Definition

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• Phase 1:• Firstly be able to write a user specified value to the

DAC on the ADI board.• Phase 2:• Control the data sent to the each of the column.• Phase 3:• Send specific data to each pixel by reading in the

necessary signals that produce the image.

Phases of the project

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Current Project Setup

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Results

Offset DAC Value Average of Pixels Standard Deviation Gain

0x1000 0x0000 5.313 20.407 0

0x1000 0x1000 296 165 0

0x1000 0x2000 1117 165 0

0x1000 0x3000 2290 157 0

0x1000 0x4000 3892 118 0

0x1000 0x5000 5750 53 0

0x1000 0x6000 7503 11 0

0x1000 0x7000 9246 25 0

0x1000 0x8000 11009 69 0

0x1000 0x9000 12886 136 0

0x1000 0xA000 14347 159 0

0x1000 0xB000 15412 165 0

0x1000 0xC000 16237 164 0

0x1000 0xD000 16383 0 0

0x1000 0xE000 16383 0 0

0x1000 0xF000 16383 0 0

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Offset DAC Value Average of Pixels Standard Deviation Gain

0x3000 0x0000 512 6 0

0x3000 0x1000 2262 4 0

0x3000 0x2000 4011 3 0

0x3000 0x3000 5759 3 0

0x3000 0x4000 7505 2 0

0x3000 0x5000 9250 3 0

0x3000 0x6000 10989 3 0

0x3000 0x7000 12746 4 0

0x3000 0x8000 14495 6 0

0x3000 0x9000 16246 11 0

0x3000 0xA000 16383 0 0

0x3000 0xB000 16383 0 0

0x3000 0xC000 16383 0 0

0x3000 0xD000 16383 0 0

0x3000 0xE000 16383 0 0

0x3000 0xF000 16383 0 0

Results

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• Vivado being a new software, I started building the design form scratch without using the reference design.

• designed the schematic and the layout for the final testing board specific to the P1AS tester board.

• That board would be interfaced with the Kintex705 board and the P1AS tester to test the electronics on the tester circuit.

My Contribution to the project

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• The new tester board will be read in all the signals required to control the Gate Driver and the Readout board.

• With the use of a CPLD, the signals will be level shifted from 5V to 2.5V and also converted into differential signals.

• To reduce the noise on the overall circuit, the signals are converted into differential signals.

Board Design

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Learned new software's:• Vivado, SDK by Xilinx.• PADS Layout by Mentor Graphics.• Basics of FPGA.• Basics of CPLD.• Basic working of the Flat Panels.Other skills acquired• Working and coordinating with a team.• In case of doubts always ask.• Think it through before trying something new.

Skills learned

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Questions???

Thank you for the opportunity

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