ROHAIL EEE440 Computer Architecture. Program Concept Hardwired systems are inflexible General...
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Transcript of ROHAIL EEE440 Computer Architecture. Program Concept Hardwired systems are inflexible General...
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ROHAIL
EEE440 Computer Architecture
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Program Concept
Hardwired systems are inflexibleGeneral purpose hardware can do different
tasks, given correct control signalsInstead of re-wiring, supply a new set of
control signals
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What is a program?
A sequence of stepsFor each step, an arithmetic or logical
operation is doneFor each operation, a different set of control
signals is needed
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Function of Control Unit
For each operation a unique code is provided e.g. ADD, MOVE
A hardware segment accepts the code and issues the control signals
We have a computer!
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Components
The Control Unit and the Arithmetic and Logic Unit constitute the Central Processing Unit
Data and instructions need to get into the system and results out Input/output
Temporary storage of code and results is needed Main memory
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Computer Components:Top Level View
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Instruction Cycle
Two steps: Fetch Execute
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Fetch Cycle
Program Counter (PC) holds address of next instruction to fetch
Processor fetches instruction from memory location pointed to by PC
Increment PC Unless told otherwise
Instruction loaded into Instruction Register (IR)
Processor interprets instruction and performs required actions
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Execute Cycle
Processor-memory data transfer between CPU and main memory
Processor I/O Data transfer between CPU and I/O module
Data processing Some arithmetic or logical operation on data
Control Alteration of sequence of operations e.g. jump
Combination of above
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Example of Program Execution
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Instruction Cycle - State Diagram
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Interrupts
Mechanism by which other modules (e.g. I/O) may interrupt normal sequence of processing
Program e.g. overflow, division by zero
Timer Generated by internal processor timer Used in pre-emptive multi-tasking
I/O from I/O controller
Hardware failure e.g. memory parity error
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Program Flow Control
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Interrupt Cycle
Added to instruction cycleProcessor checks for interrupt
Indicated by an interrupt signal
If no interrupt, fetch next instructionIf interrupt pending:
Suspend execution of current program Save context Set PC to start address of interrupt handler routine Process interrupt Restore context and continue interrupted program
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Transfer of Control via Interrupts
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Instruction Cycle with Interrupts
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Program TimingShort I/O Wait
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Program TimingLong I/O Wait
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Instruction Cycle (with Interrupts) - State Diagram
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Multiple Interrupts
Disable interrupts Processor will ignore further interrupts whilst
processing one interrupt Interrupts remain pending and are checked after first
interrupt has been processed Interrupts handled in sequence as they occur
Define priorities Low priority interrupts can be interrupted by higher
priority interrupts When higher priority interrupt has been processed,
processor returns to previous interrupt
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Multiple Interrupts - Sequential
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Multiple Interrupts – Nested
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Time Sequence of Multiple Interrupts
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Connecting
All the units must be connectedDifferent type of connection for different type
of unit Memory Input/Output CPU
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Computer Modules
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Memory Connection
Receives and sends dataReceives addresses (of locations)Receives control signals
Read Write Timing
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Input/Output Connection(1)
Similar to memory from computer’s viewpoint
Output Receive data from computer Send data to peripheral
Input Receive data from peripheral Send data to computer
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Input/Output Connection(2)
Receive control signals from computerSend control signals to peripherals
e.g. spin disk
Receive addresses from computer e.g. port number to identify peripheral
Send interrupt signals (control)
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CPU Connection
Reads instruction and dataWrites out data (after processing)Sends control signals to other unitsReceives (& acts on) interrupts
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Buses
There are a number of possible interconnection systems
Single and multiple BUS structures are most common
e.g. Control/Address/Data bus (PC)e.g. Unibus (DEC-PDP)
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What is a Bus?
A communication pathway connecting two or more devices
Usually broadcast Often grouped
A number of channels in one bus e.g. 32 bit data bus is 32 separate single bit channels
Power lines may not be shown
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Data Bus
Carries data Remember that there is no difference between “data”
and “instruction” at this level
Width is a key determinant of performance 8, 16, 32, 64 bit
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Address bus
Identify the source or destination of datae.g. CPU needs to read an instruction (data)
from a given location in memoryBus width determines maximum memory
capacity of system e.g. 8080 has 16 bit address bus giving 64k address
space
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Control Bus
Control and timing information Memory read/write signal Interrupt request Clock signals
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Bus Interconnection Scheme
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Big and Yellow?
What do buses look like? Parallel lines on circuit boards Ribbon cables Strip connectors on mother boards
e.g. PCI Sets of wires
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Single Bus Problems
Lots of devices on one bus leads to: Propagation delays
Long data paths mean that co-ordination of bus use can adversely affect performance
If aggregate data transfer approaches bus capacity
Most systems use multiple buses to overcome these problems
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Traditional (ISA)(with cache)
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High Performance Bus
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Bus Types
Dedicated Separate data & address lines
Multiplexed Shared lines Address valid or data valid control line Advantage - fewer lines Disadvantages
More complex control Ultimate performance
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Bus Arbitration
More than one module controlling the buse.g. CPU controllerOnly one module may control bus at one timeArbitration may be centralised or distributed
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Centralised Arbitration
Single hardware device controlling bus access Bus Controller Arbiter
May be part of CPU or separate
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Distributed Arbitration
Each module may claim the busControl logic on all modules
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Timing
Co-ordination of events on busSynchronous
Events determined by clock signals Control Bus includes clock line A single 1-0 is a bus cycle All devices can read clock line Usually sync on leading edge Usually a single cycle for an event
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Synchronous Timing Diagram
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Asynchronous Timing – Read Diagram
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Asynchronous Timing – Write Diagram
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PCI Bus
Peripheral Component InterconnectionIntel released to public domain32 or 64 bit50 lines
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PCI Bus Lines (required)
Systems lines Including clock and reset
Address & Data 32 time mux lines for address/data Interrupt & validate lines
Interface ControlArbitration
Not shared Direct connection to PCI bus arbiter
Error lines
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PCI Bus Lines (Optional)
Interrupt lines Not shared
Cache support64-bit Bus Extension
Additional 32 lines Time multiplexed 2 lines to enable devices to agree to use 64-bit
transfer
JTAG/Boundary Scan For testing procedures
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PCI Commands
Transaction between initiator (master) and target
Master claims busDetermine type of transaction
e.g. I/O read/write
Address phaseOne or more data phases
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Referennces
William Stallings Computer Organization and Architecture7th Edition Chapter 3