RFNoC: RF Network on Chip - files.meetup.com · Before RFNoC –Short FPGA Primer Field...

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RFNoC: RF Network on Chip Jonathon Pendlum 12/17/2014

Transcript of RFNoC: RF Network on Chip - files.meetup.com · Before RFNoC –Short FPGA Primer Field...

Page 1: RFNoC: RF Network on Chip - files.meetup.com · Before RFNoC –Short FPGA Primer Field Programmable Gate Array Xilinx, Altera, & Microsemi Sea of logic blocks with programmable interconnect

RFNoC: RF Network on ChipJonathon Pendlum

12/17/2014

Page 2: RFNoC: RF Network on Chip - files.meetup.com · Before RFNoC –Short FPGA Primer Field Programmable Gate Array Xilinx, Altera, & Microsemi Sea of logic blocks with programmable interconnect

Introduction

R&D Engineer at Ettus

Graduated Northeastern University with MS in CompE

Active in SDR since 2007

SDR Research Group at Purdue University

GNU Radio Google Summer of Code 2013

http://gnuradio.org/redmine/projects/gnuradio/wiki/Zynq

Page 3: RFNoC: RF Network on Chip - files.meetup.com · Before RFNoC –Short FPGA Primer Field Programmable Gate Array Xilinx, Altera, & Microsemi Sea of logic blocks with programmable interconnect

Before RFNoC – Short FPGA Primer

Field Programmable Gate Array

Xilinx, Altera, & Microsemi

Sea of logic blocks with programmable interconnect

Lookup Tables, Registers, Block RAMs, Multipliers

Page 4: RFNoC: RF Network on Chip - files.meetup.com · Before RFNoC –Short FPGA Primer Field Programmable Gate Array Xilinx, Altera, & Microsemi Sea of logic blocks with programmable interconnect

Why are FPGAs useful?

Extreme Parallelism

1000s of Multipliers

Highly Deterministic

Flexible I/O

System glue / Interface many devices

Reprogrammable

Programming Language Support

Low level: Verilog, SystemVerilog, VHDL

High level: SystemC, MyHDL, Chisel, Vivado HLS

Page 5: RFNoC: RF Network on Chip - files.meetup.com · Before RFNoC –Short FPGA Primer Field Programmable Gate Array Xilinx, Altera, & Microsemi Sea of logic blocks with programmable interconnect

FPGAs & SDR

Extreme Parallelism Example: Fast Fourier Transform

Page 6: RFNoC: RF Network on Chip - files.meetup.com · Before RFNoC –Short FPGA Primer Field Programmable Gate Array Xilinx, Altera, & Microsemi Sea of logic blocks with programmable interconnect

FPGAs & SDR

Serial Processing

Page 7: RFNoC: RF Network on Chip - files.meetup.com · Before RFNoC –Short FPGA Primer Field Programmable Gate Array Xilinx, Altera, & Microsemi Sea of logic blocks with programmable interconnect

FPGAs & SDR

Parallel Processing

Page 8: RFNoC: RF Network on Chip - files.meetup.com · Before RFNoC –Short FPGA Primer Field Programmable Gate Array Xilinx, Altera, & Microsemi Sea of logic blocks with programmable interconnect

Big FPGAs in Ettus Third Gen Devices

X300 / X310

Xilinx Kintex 7

406K Logic Cells; 3840 kB Memory; 1540 Multipliers

Free Space ~85%

200 MHz of instantaneous bandwidth

Page 9: RFNoC: RF Network on Chip - files.meetup.com · Before RFNoC –Short FPGA Primer Field Programmable Gate Array Xilinx, Altera, & Microsemi Sea of logic blocks with programmable interconnect

The Goal

Heterogeneous processing

Composable & modular both on GPP and FPGA

Move blocks to the platform that makes most sense

Reuse and rearrange blocks

Page 10: RFNoC: RF Network on Chip - files.meetup.com · Before RFNoC –Short FPGA Primer Field Programmable Gate Array Xilinx, Altera, & Microsemi Sea of logic blocks with programmable interconnect

RF Network-on-Chip

Page 11: RFNoC: RF Network on Chip - files.meetup.com · Before RFNoC –Short FPGA Primer Field Programmable Gate Array Xilinx, Altera, & Microsemi Sea of logic blocks with programmable interconnect

What does RFNoC do?

Makes FPGA acceleration more accessible Dedicated FPGA space for computation engines

FIR filter, FFT, Polyphase filter, Correlator

OFDM Sync, Costas Loop, Bit Sync, Crypto

Low latency protocol processing

Handles Data Transport

Packetization and routing

Flow control

No host is necessary

Simple data and control interfaces

AXI Stream connections (industry standard)

Large library of existing IP

Each computation engine in its own clock domain

Software API to configure crossbar and transfer data

computation engines

Supported in GNU Radio

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Traditional Flowgraph

Page 13: RFNoC: RF Network on Chip - files.meetup.com · Before RFNoC –Short FPGA Primer Field Programmable Gate Array Xilinx, Altera, & Microsemi Sea of logic blocks with programmable interconnect

Traditional Flowgraph

Page 14: RFNoC: RF Network on Chip - files.meetup.com · Before RFNoC –Short FPGA Primer Field Programmable Gate Array Xilinx, Altera, & Microsemi Sea of logic blocks with programmable interconnect

RFNoC Flowgraph

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RFNoC Flowgraph

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RFNoC Flowgraph

Page 17: RFNoC: RF Network on Chip - files.meetup.com · Before RFNoC –Short FPGA Primer Field Programmable Gate Array Xilinx, Altera, & Microsemi Sea of logic blocks with programmable interconnect

RFNoC Flowgraph

Page 18: RFNoC: RF Network on Chip - files.meetup.com · Before RFNoC –Short FPGA Primer Field Programmable Gate Array Xilinx, Altera, & Microsemi Sea of logic blocks with programmable interconnect

DEMO

Page 19: RFNoC: RF Network on Chip - files.meetup.com · Before RFNoC –Short FPGA Primer Field Programmable Gate Array Xilinx, Altera, & Microsemi Sea of logic blocks with programmable interconnect

Beta Release Available Now!

See RFNoC Getting Started Wiki to install:

github.com/EttusResearch/uhd/wiki/RFNoC:-Getting-Started

EttusResearch UHD / GNU Radio repos – rfnoc-devel branch

X300/X310 supported, E310 coming soon

Rapid development – check USRP mailing list

Questions: [email protected]

Jonathon Pendlum – [email protected]

Matt Ettus – [email protected]

Martin Braun – [email protected]