RFID Based ATM System

8/11/2019 RFID Based ATM System

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INTRODUCTION

1.1 OBJECTIVE

The main aim of this project to provide secure banking system, by taking ids as

authorized identity at ATM/banks. The purpose of the project is to provide a secured and

reliable environment to the customers for their banking transactions by providing a unique

identity to every user using the ! identification technology.

The main objective of this system is to develop an embedded system, "hich is used

for ATM security applications. n these system, #ankers "ill collect the customer id s "hileopening the accounts then customer "ill only access ATM machine. The "orking of these

ATM machine is "hen customer place id on the id module it displays the name of the

customer on the $%! connected to the micro controller. f the user does not have a account

activated by a &'!initially it does not allo" the user to do transactions.

(o"adays, using the ATM )Automatic Teller Machine* "hich provides customers

"ith the convenient banknote trading is very common. +o"ever, the financial crime case

rises repeatedly in recent years a lot of criminals tamper "ith the ATM terminal and steal

user-s credit card and pass"ord by illegal means. nce user-s bank card is lost and the

pass"ord is stolen, the criminal "ill dra" all cash in the shortest time, "hich "ill bring

enormous financial losses to customer. +o" to carry on the valid identity to the customer

becomes the focus in current financial circle. Traditional ATM systems authenticate generally

by using the credit card and the pass"ord, the method has some defects. sing credit card

and pass"ord cannot verify the client-s identity e0actly. n recent years, the algorithm that the

&'!recognition continuously updated, "hich has offered ne" verification means for us, theoriginal pass"ord authentication method combined "ith the biometric identification

technology verify the clients- identity better and achieve the purpose that use of ATM

machines improve the safety effectively. This project can be e0tended to be operated "ith

pass"ord i.e., sending a unique pass"ord to the customer1s mobile every time the customer

places a id to do transactions, then the customer must enter the code and proceed further .

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1.2 BACK GROUND OF BIOMETRICS

This invention relates to the field of biometrics. ATM makes the human life very

comfort. n olden days suppose "ant to dra" the money have to go to the bank, and have

to "ait until get my turn. #ut using these e0isting ATMs there is no time "aste. n the

e0isting system "e are dealing "ith a card and "e have an individual pass"ord to protect our

money. #ut anybody can kno" our pass"ord and steal our card. 2o there is no security to our

money.

n order to overcome that problem here is the &'! #A23! ATM 23%&T4

242T3M.+ere card system doesn1t e0ist. 'irst of all "e have to give our id to the data base.

5henever "e "ant money "e have to go to the ATM machine and should give our id. f it

matches "ith the data base it displays our name, means it is another security to our system.

Then only further transaction "ill be done. f the date base is not matched no further

transaction "ill be done. 2o there is no need to "orry about our money. (obody can steal our

money.

1.3ADVANTAGES:

More secured as it is operated through id

%an be operated through picture as pass"ord

%ost effective

1.4APPLICATIONS:

%ell phones.

%omputers.

&obots.

nterfacing to t"o pc1s

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BLOCK DIAGRAM

2.1 DESCRIPTION:

The block diagram sho"n in the 'ig 6.7 consists of A&M8, d Module, po"er

supply, &2696, 33:&M, Touch :ad, and $%!. (o"adays, using the ATM )Automatic

Teller Machine* "hich provide customers "ith the convenient banknote trading is very

common.

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Fig 2.1 RFID ba!" ATM !#$%i&' S'&!(

+o"ever, the financial crime case rises repeatedly in recent years a lot of criminals

tamper "ith the ATM terminal and steal user-s credit card and pass"ord by illegal means.

nce user-s bank card is lost and the pass"ord is stolen, the criminal "ill dra" all cash in the

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shortest time, "hich "ill bring enormous financial losses to customer. +o" to carry on the

valid identity to the customer becomes the focus in current financial circle.

Traditional ATM systems authenticate generally by using the credit card and the

pass"ord, the method has some defects. sing credit card and pass"ord cannot verify the

client-s identity e0actly. n recent years, the algorithm that the &'!recognition continuously

updated, "hich has offered ne" verification means for us, the original pass"ord

authentication method combined "ith the biometric identification technology verify the

clients- identity better and achieve the purpose that use of ATM machines improve the safety

effectively.

The embedded ATM client authentication system is based on &'!recognition "hich

is designed after analyzed e0isted ATM system. The 29%6;;< chip is used as the core of this

embedded system "hich is associated "ith the technologies of &'!recognition and current

high speed net"ork communication. The primary functions are sho"n as follo"s=

CIRCUIT DIAGRAM

3.1 DESCRIPTION OF T)E CIRCUIT

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The %ircuit !iagram is sho"n in 'ig 9.7.+ere "e are using serial id scanner. t has

&2696 for serial communication. t has ; outputs.

7.76> :o"er supply,

6. &eception of data,

9. Transmission of data,

;. ?round.

5e are using MA@696 for >oltage and %urrent balance. 2canner 6 outputs

Transmission and &eception of data are given as inputs to its 79, 7; pins respectively. utput

is taken from 76, 77 pins. These are given to 7.

%oming to 7DE6 $%! it has 7D pins.

7.7D pin is connected to ?round,

6.7C pin are :o"er supply.

9.9 pin is for adjustment of brightness of screen.

5hen ne" user is using he has to press this push s"itch in order to enter into this

mode. 'irst the user should register his id . +e gets a message as &3?2T3&3! for his

registration. All id s are stored n the F%.

ld user should use this s"itch. (o" he should keep his id on scanner for verification

process.

f id is matched he is the AT+&23! person. Then he is asked for pass"ord if it

is also correct then he has to enter the money. f it is not matched he gets a message as

(AT+&23! person. 'urther transactions "ill not be done.

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)ARD*ARE COMPONENTS

4.1 PO*ER SUPPL+ UNIT:

Ci%#$i& Diag%a(

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Fig 4.1P,-!% S$/'

P,-!% $/' $0i& #,0i& , ,//,-i0g $0i&

i* 2tep do"n transformer

ii* &ectifier unit

iii* nput filter

iv* &egulator unit

v* utput filter

4.1.1 STEPDO*N TRANSFORMER:

The 2tep do"n Transformer is used to step do"n the main supply voltage from 69

A% to lo"er value. This 69< A% voltage cannot be used directly, thus it is stepped do"n. The

Transformer consists of primary and secondary coils. To reduce or step do"n the voltage, the

transformer is designed to contain less number of turns in its secondary core. The output

from the secondary coil is also A% "aveform. Thus the conversion from A% to !% is

essential. This conversion is achieved by using the &ectifier %ircuit/nit.

The secondary induced voltage >2, of an ideal transformer, is scaled from the primary

>:by a factor equal to the ratio of the number of turns of "ire in their respective "indings=

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4.1.1.1 Bai# P%i0#i/!

The transformer is based on t"o principles= firstly, that an electric current can

produce a magnetic field )electromagnetism* and secondly that a changing magnetic field

"ithin a coil of "ire induces a voltage across the ends of the coil )electromagnetic induction*.

#y changing the current in the primary coil, it changes the strength of its magnetic field

since the changing magnetic field e0tends into the secondary coil, a voltage is induced across

the secondary.

A simplified transformer design is sho"n belo". A current passing through the

primary coil creates a magnetic field. The primary and secondary coils are "rapped around a

core of very high magnetic permeability, such as iron this ensures that most of the magnetic

field lines produced by the primary current are "ithin the iron and pass through the

secondary coil as "ell as the primary coil.

4.1.1.2 I0"$#&i,0 /a-

The voltage induced across the secondary coil may be calculated from 'araday-s la"

of induction, "hich states that=

5here >2is the instantaneous voltage, (2is the number of turns in the secondary coil

and G equals the magnetic flu0 through one turn of the coil. f the turns of the coil are

oriented perpendicular to the magnetic field lines, the flu0 is the product of the magnetic field

strength # and the area A through "hich it cuts. The area is constant, being equal to the

crossHsectional area of the transformer core, "hereas the magnetic field varies "ith time

according to the e0citation of the primary. 2ince the same magnetic flu0 passes through both

the primary and secondary coils in an ideal transformer, the instantaneous voltage across the

primary "inding equals

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Taking the ratio of the t"o equations for VS and VP gives the basic equation for

stepping up or stepping do"n the voltage

4.1.1.3 I"!a/ P,-!% E$a&i,0

f the secondary coil is attached to a load that allo"s current to flo", electrical po"er

is transmitted from the primary circuit to the secondary circuit. deally, the transformer is

perfectly efficient all the incoming energy is transformed from the primary circuit to the

magnetic field and into the secondary circuit. f this condition is met, the incoming electric

po"er must equal the outgoing po"er.

:incomingI :>:I :outgoingI 2>2

?iving the ideal transformer equation

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Fig 4.2 T%a0,%(!%

:inHcomingI :>:I :outHgoingI 2>2

?iving the ideal transformer equation

f the voltage is increased )stepped up* )VS J VP*, then the current is decreased

)stepped do"n* )ISK IP* by the same factor. Transformers are efficient so this formula is a

reasonable appro0imation.

f the voltage is increased )stepped up* )VS J VP*, then the current is decreased

)stepped do"n* )ISK IP* by the same factor. Transformers are efficient so this formula is areasonable appro0imation.

The impedance in one circuit is transformed by the square of the turns ratio. 'or

e0ample, if an impedanceZSis attached across the terminals of the secondary coil, it appears

to the primary circuit to have an impedance of

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http://en.wikipedia.org/wiki/Image:Transformer_under_load.svg


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This relationship is reciprocal, so that the impedanceZPof the primary circuit appears

to the secondary to be

4.1.2. R!#&ii!% U0i&:

The &ectifier circuit is used to convert the A% voltage into its corresponding !%

voltage. The most important and simple device used in &ectifier circuit is the diode. The

simple function of the diode is to conduct "hen for"ard biased and not to conduct in reverse

bias. (o" "e are using three types of rectifiers. They are

7. +alfH"ave rectifier

6. 'ullH"ave rectifier

9. #ridge rectifier

F$//-a! %!#&ii!%

A fullH"ave rectifier converts the "hole of the input "aveform to one of constant

polarity )positive or negative* at its output. 'ullH"ave rectification converts both polarities of

the input "aveform to !% )direct current*, and is more efficient.

B%i"g! %!#&ii!%

12

)a/-a! %!#&ii!%

n half "ave rectification, either the positive or negative half of the A% "ave is

passed, "hile the other half is blocked. #ecause only one half of the input "aveform

reaches the output, it is very inefficient if used for po"er transfer. +alfH"ave

rectification can be achieved "ith a single diode in a one phase supply, or "ith three

diodes in a threeHphase supply.


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A bridge rectifier makes use of four diodes in a bridge arrangement to achieve fullH

"ave rectification. This is a "idely used configuration, both "ith individual diodes "ired as

sho"n and "ith single component bridges "here the diode bridge is "ired internally.

Fig 4.3 B%i"g! R!#&ii!%

A "i,"! b%i"g! or b%i"g! %!#&ii!% is an arrangement of four diodes in a bridge

configuration that provides the samepolarityof output voltagefor either polarity of input

voltage. 5hen used in its most common application, for conversion of alternating current

)A%* input into direct current )!%* output, it is kno"n as a bridge rectifier.A bridge rectifier

providesfullH"ave rectificationfrom a t"oH"ire A% input, resulting in lo"er cost and "eight

as compared to a centerHtappedtransformerdesign.

13
http://en.wikipedia.org/wiki/Diodehttp://en.wikipedia.org/wiki/Bridge_circuithttp://en.wikipedia.org/wiki/Polarity_(physics)http://en.wikipedia.org/wiki/Volthttp://en.wikipedia.org/wiki/Alternating_currenthttp://en.wikipedia.org/wiki/Direct_currenthttp://en.wikipedia.org/wiki/Rectifierhttp://en.wikipedia.org/wiki/Rectifierhttp://en.wikipedia.org/wiki/Center_taphttp://en.wikipedia.org/wiki/Transformerhttp://en.wikipedia.org/wiki/Diodehttp://en.wikipedia.org/wiki/Bridge_circuithttp://en.wikipedia.org/wiki/Polarity_(physics)http://en.wikipedia.org/wiki/Volthttp://en.wikipedia.org/wiki/Alternating_currenthttp://en.wikipedia.org/wiki/Direct_currenthttp://en.wikipedia.org/wiki/Rectifierhttp://en.wikipedia.org/wiki/Rectifierhttp://en.wikipedia.org/wiki/Center_taphttp://en.wikipedia.org/wiki/Transformer


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Fig.4.4. R!#&ii!% *a!,%(

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4.1.3 I0$& Fi/&!%:

%apacitors are used as filter. The ripples from the !% voltage are removed and pure

!% voltage is obtained. And also these capacitors are used to reduce the harmonics of the

input voltage. The primary action performed by capacitor is charging and discharging. t

charges in positive half cycle of the A% voltage and it "ill discharge in negative half cycle.

2o it allo"s only A% voltage and does not allo" the !% voltage. This filter is fi0ed before

the regulator. Thus the output is free from ripples.

There are t"o types of filters. They are

7. $o" pass filter

6. +igh pass filter

L,- a i/&!%:

Fig.4.5. L,- a Fi/&!%

ne simple electrical circuitthat "ill serve as a lo"Hpass filter consists of a resistorin

series "ith a load, and a capacitorin parallel "ith the load. The capacitor e0hibits reactance,

and blocks lo"Hfrequency signals, causing them to go through the load instead. At higher

frequencies the reactance drops, and the capacitor effectively functions as a short circuit. The

combination of resistance and capacitance gives you the time constantof the filter L IRC

)represented by the ?reek letter tau*. The break frequency, also called the turnover frequency

orcutoff frequency)in hertz*, is determined by the time constant= or equivalently )in radians

per second*=

15
http://en.wikipedia.org/wiki/Electrical_circuithttp://en.wikipedia.org/wiki/Resistorhttp://en.wikipedia.org/wiki/External_electric_loadhttp://en.wikipedia.org/wiki/Capacitorhttp://en.wikipedia.org/wiki/Reactance_(electronics)http://en.wikipedia.org/wiki/Time_constanthttp://en.wikipedia.org/wiki/Tauhttp://en.wikipedia.org/wiki/Cutoff_frequencyhttp://en.wikipedia.org/wiki/Cutoff_frequencyhttp://en.wikipedia.org/wiki/Cutoff_frequencyhttp://en.wikipedia.org/wiki/Radianshttp://en.wikipedia.org/wiki/Electrical_circuithttp://en.wikipedia.org/wiki/Resistorhttp://en.wikipedia.org/wiki/External_electric_loadhttp://en.wikipedia.org/wiki/Capacitorhttp://en.wikipedia.org/wiki/Reactance_(electronics)http://en.wikipedia.org/wiki/Time_constanthttp://en.wikipedia.org/wiki/Tauhttp://en.wikipedia.org/wiki/Cutoff_frequencyhttp://en.wikipedia.org/wiki/Radians


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)ig6 a i/&!%:

Fig.4.7 )ig6 a i/&!%

The above circuit diagram illustrates a simple 'RC'highHpass filter. "e should find

that the circuit passes -high- frequencies fairly "ell, but attenuates -lo"- frequencies.

+ence it is useful as a filter to block any un"anted lo" frequency components of a

comple0 signal "hilst passing higher frequencies. %ircuits like this are used quite a lot in

electronics as a -!.%. #lock- H i.e. to pass a.c. signals but prevent any !.%. voltages from

getting through.

4.1.4 R!g$/a&,% U0i&:

Fig.4.8 895 R!g$/a&,%

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&egulator regulates the output voltage to be al"ays constant. The output voltage is

maintained irrespective of the fluctuations in the input A% voltage. As and then the A%

voltage changes, the !% voltage also changes. Thus to avoid this &egulators are used. Also

"hen the internal resistance of the po"er supply is greater than 9< ohms, the output gets

affected. Thus this can be successfully reduced here. The regulators are mainly classified for

lo" voltage and for high voltage. 'urther they can also be classified as=

i* :ositive regulator

7* nput pin

6* ?round pin

9* utput pin

t regulates the positive voltage.

ii* (egative regulator

7* ?round pin

6* nput pin

9* utput pin

t regulates the negative voltage.

Fig.4.9 B/,#; "iag%a( , %!g$/a&,%

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4.1.5 O$&$& Fi/&!%:

The 'ilter circuit is often fi0ed after the &egulator circuit. %apacitor is most often

used as filter. The principle of the capacitor is to charge and discharge. t charges during the

positive half cycle of the A% voltage and discharges during the negative half cycle. 2o it

allo"s only A% voltage and does not allo" the !% voltage. This filter is fi0ed after the

&egulator circuit to filter any of the possibly found ripples in the output received finally.

+ere "e used


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Tab/! 4.1 PIN D!#%i&i,0 , MA :o"er 2upply

#i%M2 :rocess Technology

T"o !rivers and T"o &eceivers.9 nput $evels

$o" 2upply %urrent. mA Typical

Meets or 30ceeds TA/3AH696H' and T

!esigned to be nterchangeable 5ith

Ma0im MA@696

19

Pi0

N,. F$0#&i,0 Na(!

7

%apacitor connection pins

%apacitor 7 N

6 %apacitor 9 N

9 %apacitor 7 H

; %apacitor 6 N

C %apacitor 6 H

D %apacitor ; H

8 utput pin outputs the serially transmitted data at &2696 logic

level connected to receiver pin of :% serial port

T6 ut

nput pin receives serially transmitted data at &2 696 logic level

connected to transmitter pin of :% serial port

&6n

B utput pin outputs the serially transmitted data at TT$ logic

level connected to receiver pin of controller.

&6ut

7< nput pins receive the serial data at TT$ logic level connected to

serial transmitter pin of controller.

T6n

77H T7n

76 utput pin outputs the serially transmitted data at TT$ logic

level connected to receiver pin of controller.

&7ut

79 nput pin receives serially transmitted data at &2 696 logic level

connected to transmitter pin of :% serial port

&7n

7; utput pin outputs the serially transmitted data at &2696 logic

level connected to receiver pin of :% serial port

T7ut

7C ?round )* ?round

7D 2upply voltage C> );.C> O C.C>* >cc


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Applications

o TA/3AH696H'

o #atteryH:o"ered 2ystems

o Terminals

o Modems

o %omputers 32! :rotection 30ceeds 6 )roughly ... N referred to as lowfor binary -

... NC> for highbinary -7- *. Modern lo"Hpo"er logic operates in the range of ... N9.9> or

even lo"er.

2o, the ma0imum &2H696 signal levels are far too high for today-s computer logic

electronics, and the negative &2H696 voltage can-t be grokked at all by the computer logic.

Therefore, to receive serial data from an &2H696 interface the voltage has to be reduced, and

the 0and 1voltage levels inverted.

n the other direction )sending data from some logic over &2H696* the lo" logic

voltage has to be Pbumped upP, and a negative voltage has to be generated, too.

&2H696 TT$ $ogic

HHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHH

H7C> ... H9> KHJ N6> ... NC> KHJ 7

N9> ... N7C> KHJ ... N KHJ ee. Trimmer potentiometer is usually used for that purpose. 2ome versions

of displays have built in backlight )blue or green diodes*. 5hen used during operating, a

resistor for current limitation should be used )like "ith any $3 diode*.

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'ig= ;.9 :in !iagram of $%!

4.4.2 LCD Bai# C,((a0"

All data transferred to $%! through outputs !


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Tab/! 4.4 LCD C,((a0"

A /i$i" #%'&a/ "i/a' LCDis a thin, flat display device made up of any number

of color or monochrome pi0els arrayed in front of a light source or reflector. 3ach i!/

consists of a column of liquid crystal molecules suspended bet"een t"o transparent

electrodes, and t"o polarizing filters, the a0es of polarity of "hich are perpendicular to each

other. 5ithout the liquid crystals bet"een them, light passing through one "ould be blocked

by the other. The liquid crystal t"ists the polarization of light entering one filter to allo" it to

pass through the other.

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A program must interact "ith the outside "orld using input and output devices that

communicate directly "ith a human being. ne of the most common devices attached to an

controller is an $%! display. 2ome of the most common $%!s connected to the controllers

are 17


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Many microcontroller devices use -smart $%!- displays to output visual information.

$%! displays designed around $%! (TH%7D77 module, are ine0pensive, easy to use, and it

is even possible to produce a readout using the C@8 dots plus cursor of the display. They

have a standard A2% set of characters and mathematical symbols. 'or an Hbit data bus, the

display requires a 5V $/'plus 7< / lines )&2 &5 !8 !D !C !; !9 !6 !7 !


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4.4.3 S)APES AND SIES:

;.6.7)a* 2+A:32 A(! 2S32 ' $%!

3ven limited to character based modules, there is still a "ide variety of shapes and

sizes available. $ine lengths of9 1722432 a0" 4characters are all standard, in one, t"o

and four line versions. 2everal different $% technologies e0ists. $!%&-i&H types, for

e0ample, offer mproved contrast and vie"ing angle over the older Qt"isted nematiR types.

2ome modules are available "ith back lighting, so that they can be vie"ed in dimlyHlit

conditions. The back lighting may be either !/!#&%,/$(i0!#!0&H, requiring a high voltage

inverter circuit, or simple $3! illumination.

4.4.4 E/!#&%i#a/ b/,#; "iag%a(:

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'? ;.6.6)a* 3$3%T&%A$ #$% !A?&AM ' $%!

4.4.5 P,-!% $/' ,% LCD "%ii0g:

'? ;.6.9)a*= :53& 2::$4 '& $%! !&>(?

4.4.7 Pi0 D!#%i&i,0:

Most $%!s "ith 7 controller has 7; :ins and $%!s "ith 6 controller has 7D :ins

)t"o pins are e0tra in both for backHlight $3! connections*.

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'?&3;.6.; )a* :( !A?&AM ' 7@7D $(32 $%!

CONTROL LINES

EN= $ine is called P3nable.P This control line is used to tell the $%! that you are sending it

data. To send data to the $%!, your program should make sure this line is lo" )


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lines )depending on the mode of operation selected by the user*. n the case of an Hbit data

bus, the lines are referred to as !#


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All the available characters that are built into the module are sho"n in Table 9.

2tudying the table, you "ill see that codes associated "ith the characters are quoted in binary

and he0adecimal, most significant bits )QleftHhandR four bits* across the top, and least

significant bits )QrightHhandR four bits* do"n the left.

Most of the characters conform to the A2% standard, although the Uapanese and

?reek characters )and a fe" other things* are obvious e0ceptions. 2ince these intelligent

modules "ere designed in the Q$and of the &ising 2un,R it seems only fair that their atakana

phonetic symbols should also be incorporated. The more e0tensive anji character set, "hich

the Uapanese share "ith the %hinese, consisting of several thousand different characters, is not

included.

sing the s"itches, of "hatever type, and referring to Table 9, enter a fe" characters

onto the display, both letters and numbers. The &2 s"itch )27


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The A2% code to be displayed is eight bits long and is sent to the $%! either four or eight

bits at a time. f ;Hbit mode is used, t"o nibbles of data )'irst high four bits and then lo" four

bits "ith an 3 %lock pulse "ith each nibble* are sent to complete a full eightHbit transfer. The

3 %lock is used to initiate the data transfer "ithin the $%!.Hbit mode is best used "hen

speed is required in an application and at least ten / pins are available. ;Hbit mode requires

a minimum of si0 bits. n ;Hbit mode, only the top ; data bits )!#;H8* are used. The &/2 pin

is used to select "hether data or an instruction is being transferred bet"een the

microcontroller and the $%!. f the pin is high, then the byte at the current $%! %ursor

:osition can be read or "ritten.

'?.;.6.C (T3&'A%(? ' M%&%(T&$$3& 5T+ $%!

4.5 MICROCONTROLLER

CHAPTER 2

ARM Architecture

35

MC

E

R/W

WR

SDB7DB0

LCD

co!"o#

co$$%&c'!

&o( )%(

Microcontroller

8


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ARM Architecture

ARM History

Architecture

ARM register fle & modes o operation

Instruction et

ARM History

36


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To' !*+ ARM '$ 'cco%!( o" '"o&$'!+# 75: o '##

+$)++ 32)&! RISC CP( $'& &! !*+ $o(! &+# %(+ 32)&! '"c*&!+c!%"+.

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+&c+( ,PDA( $o)+ *o+( &Po( ' o!*+" &&!'# $+&' ' $%(&c #'+"(

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$'%'c!%"+"( !o &!+"'!+ !*+$ &!o !*+&" o ((!+$

ARM architecture

RIC"

RISC o" Reduced Instruction Set Computer. &( ' !+ o $&c"o"oc+((o"

'"c*&!+c!%"+ !*'! %!&;+( ' ($'## *&*#o!&$&;+ (+! o &(!"%c!&o( "'!*+" !*'

' $o"+ (+c&'#&;+ (+! o &(!"%c!&o( o!+ o% & o!*+" !+( o '"c*&!+c!%"+(.

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History "

T*+


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!esign rules are simple thus core operates

at higher clock frequencies

MemoryHtoHmemory addressing modes.

A microcode control unit.

2pend fe"er transistors on registers.

instructions correspond to mic

instructions on a %2% machine.

!esign rules are more comple0 and o

at lo"er clock frequencies

2imple addressing modes that allo"

$A! and 2T&3 to access memo

operations are registerHtoHregister.

direct e0ecution control unit.

spend more transistors on multiple ba

registers.

use pipelined e0ecution to lo"er %:.

B'(+ %o RISC A"c*&!+c!%"+ &!* +*'c+$+!( !o $++! "+?%&"+$+!( o

+$)++ '#&c'!&o( ARM &( *'&

7. A large uniform register file

6. $oadHstore architecture ,"here data processing operations operate on register

contents only

9. niform and fi0ed length instructions

;. 96 Hbit processor

C. nstructions are 96Hbit long

D. ?ood 2peed/:o"er %onsumption &atio

8. +igh %ode !ensity

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Har!ard architecture *'( (+'"'!+ '!' ' &(!"%c!&o )%((+( '##o&

!"'(+"( !o )+ +"o"$+ (&$%#!'+o%(# o )o!* )%((+( . "+'!+" '$o%! o

&(!"%c!&o '"'##+#&($ &( o((&)#+ & !*&( '"c*&!+c!%"+. Mo(! DSP( %(+ '"'"

'"c*&!+c!%"+ o" (!"+'$& '!'. T*+ o# &+"+c+ & '"'" '"c*&!+c!%"+ !o

!*'! o #on $eumann architecture &( !*'! !*+ "o"'$ ' '!' $+$o"&+(

'"+ (+'"'!+ ' %(+ *(&c'## (+'"'!+ !"'($&((&o '!*( . E')#+( !*+

$'c*&+ !o !"'(+" &(!"%c!&o( ' '!' (&$%#!'+o%(# +*'c+(

+"o"$'c+. '"'" '"c*&!+c!%"+ &( $o"+ co$$o# %(+ & (+c&'#&;+

$&c"o"oc+((o"( o" "+'#!&$+ ' +$)++ '#&c'!&o. o++" o# !*+

+'"# DSP c*&( %(+ !*+ '"'" '"c*&!+c!%"+ )+c'%(+ o !*+ co(!. T*+ "+'!+(!

&(''!'+ o !*+ '"'" '"c*&!+c!%"+ &( *&c* ++( !&c+ '( $' '"+((

' '!' &( o !*+ c*&(

A #on $eumann architecture(!o"+ "o"'$ ' '!' & !*+ ('$+ $+$o"

'"+' &!* ' (+ )%(. So !*&( )%( o# &( %(+ o" )o!* '!' !"'(+"( '

&(!"%c!&o +!c*+( ' !*+"+o"+ '!' !"'(+"( ' &(!"%c!&o +!c*+( $%(! )+

(c*+%#+ !*+ c' o! )+ +"o"$+ '! !*+ ('$+ !&$+. Mo(! o !*+ ++"'#

%"o(+ $&c"o"oc+((o"( (%c* '( Mo!o"o#' 68000 ' I!+# 8086 %(+ !*&(

'"c*&!+c!%"+. I! &( (&$#+ & *'"'"+ &$#+$+!'!&o )%! !*+ '!' ' "o"'$

'"+ "+?%&"+ !o (*'"+ ' (+ )%(.

ARM Processor Core "

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T*+ ARM co"+ '!'o $o+#

I !*+ ')o+


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T*+ instruction decoder !"'(#'!+( &(!"%c!&o( )+o"+ !*+ '"+

++c%!+. E'c* &(!"%c!&o ++c%!+ )+#o( !o ' '"!&c%#'" &(!"%c!&o (+!.

T*+ ARM "oc+((o" #&+ '## RISC "oc+((o"( %(+ ' load-store architecture.

T*&( $+'( &! *'( !o &(!"%c!&o !+( o" !"'(+""& '!' & ' o%! o !*+

"oc+((o" > #o' &(!"%c!&o( co '!' "o$ $+$o" !o "+&(!+"( & !*+ co"+ '

co+"(+# !*+ (!o"+ &(!"%c!&o( co '!' "o$ "+&(!+"( !o $+$o". T*+"+ '"+

o '!' "oc+((& &(!"%c!&o( !*'! &"+c!# $'&%#'!+ '!' & $+$o". T*%(

'!' "oc+((& &( c'""&+ o%! (o#+# & "+&(!+"(.

D'!' &!+$( '"+ #'c+ & !*+ register fle ' (!o"'+ )' $'+ % o

32)&! "+&(!+"(. S&c+ !*+ ARM co"+ &( ' 32 )&! "oc+((o" $o(! &(!"%c!&o( !"+'!

!*+ "+&(!+"( '( *o#& (&+ o" %(&+ 32)&! '#%+(.

T*+ sign etend *'"'"+ co+"!( (&+ 8)&! ' 16)&! %$)+"( !o

32)&! '#%+( '( !*+ '"+ "+' "o$ $+$o" ' #'c+ & ' "+&(!+".

T*+ AL , '"&!*$+!&c #o&c %&! - o" MAC , $%#! 'cc%$%#'!+ %&! -

!'+( !*+ "+&(!+" '#%+( Rn ' Rm "o$ !*+ A ' B )%(+( ' co$%!+( '

"+(%#!. D'!' "oc+((& &(!"%c!&o( "&!+ !*+ "+(%#! & Rd &"+c!# !o !*+ "+&(!+"


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E$)++ ((!+$( %(+ &+"+! )%( !+c*o#o&+(. Mo(! co$$o PC )%(

!+c*o#o &( !*+ P+"&*+"'# Co$o+! I!+"co+c! , PCI - )%(. W*&c* co+c!(

+&c+( (%c* '( &+o c'" ' &( co!"o##+"( !o !*+ G86 "oc+((o" )%(. T*&(

!+ o !+c*o#o &( c'##+ E!+"'# o" O c*& )%( !+c*o#o.

E$)++ +&c+( %(+ ' oc*& )%( !*'! &( &!+"'# !o !*+ c*& '

'##o( &+"+! +"&*+"'# +&c+( !o )+ &!+" co+c!+ &!* ' ARM co"+.

T*+"+ '"+ !o &+"+! !+( o +&c+( co+c!+ !o !*+ )%(

1. B%( M'(!+"

2. B%( S#'+

1. (us Master " A #o&c'# +&c+ c'')#+ o &&!&'!& ' '!' !"'(+" &!*

'o!*+" +&c+ 'c"o(( !*+ ('$+ )%( ,ARM "oc+((o" co"+ &( ' )%(

M'(!+" -.

2. (us la!e " A #o&c'# +&c+ c'')#+ o# o "+(o& !o ' !"'(+"

"+?%+(! "o$ ' )%( $'(!+" +&c+ , P+"&*+"'#( '"+ )%( (#'+( -

++"'## A B%( *'( !o '"c*&!+c!%"+ #++#(

Physical le!er " W*&c* co+"( +#+c!"&c'# c*'"'c!+"&(!&c( ' )%( &!* ,163264

)%(-.

Protocol le!el " *&c* +'#( &!* "o!oco#

NOTE > ARM &( "&$'" ' +(& co$' . I! (+#o$ &$#+$+!( !*+ +#+c!"&c'#

c*'"'c!+"&(!&c( o !*+ )%( )%! &! "o%!&+# (+c&


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although an 2A revision may have more than one processor implementation

The 2A has evolved to keep up "ith the demands of the embedded market. This

evolution has been carefully managed by A&M , so that code "ritten to e0ecute on an earlier

architecture revision "ill also e0ecute on a later revision of the architecture.

The nomenclature identifies individual processors and provides basic information

about the feature set.

NOMENCLATURE=

A&M uses the nomenclature sho"n belo" is to describe the processor

implementations.The letters and numbers after the "ord QA&MR indicate the features a

processor may have.

ARM ' T D M I E J F S

0 V family

y V memory management / protection unit

z V cache

T V Thumb 7D bit decoder

! V UTA? debug

M V fast multiplier

V 3mbedded%3 macrocell

3 V enhanced instruction ) assumes T!M *

U V Uazelle

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' V vector floatingHpoint unit

2 V synthesizible version

All A&M cores after the A&M8T!M include the T!M features even though they

may not include those letters after the Q A&M R label

The processor family is a group of processor implementations that share the same

hard"are characteristics. 'or e0ample, the A&M8T!M, A&M8;


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T*"++(!'+ &+#&+

32)&! AL

H+" ($'## &+ (&;+ ' #o o+" co(%$!&o

F%## (!'!&c o+"'!&o

Co"oc+((o" &!+"'c+

E!+(&+ +)% 'c&!&+( ,E$)++ICE +)% %&! 'cc+((&)#+ &' TA

&!+"'c+ %&!-

(enefts

++"&c #'o%! c' )+ o"!+ !o (+c&


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2./ ARM Register fle & modes o operation

R!gi&!% :?eneral :urpose registers hold either data or address they are identified "ith the

letter rprefi0ed to the register number. All registers are of 96 bits.

ARM 6a 38 %!gi&!% i0 &,&a/ a// , -6i#6 a%! 32bi& /,0g.

7 dedicated program counter

7 dedicated current program status register

C dedicated saved program status register,9< general purpose registers.

+o"ever these are arranged into several banks, "ith the accessible bank being

governed by the processor mode. 3ach mode can access a particular set of r


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&egister r1 is called the link register ) lr (and is "here the core puts the return

address "henever it calls a subroutine.

&egister r1) is the program counter ) &c * and contains the address of the ne0t

instruction to be fetched by the processorThe register file contains all the registers available to a programmer. 5hich registers are

visible to the programmer depend upon the current mode of the processor.

C$%%!0& %,g%a( &a&$ %!gi&!% :

The A&M core uses the cpsr to monitor and control internal operations. The cpsr is a

dedicated 96Hbit register and resides in the register file. The follo"ing figure sho"s the

generic program status register.

'ig= :rogram 2tatus &egister'ig= :rogram 2tatus &egister

The control bit field contains the processor mode, state , and interrupt mask bits ),'*.

&eserved bits are allocated for the future versions purpose.

The (, S, % and > are condition code flags "ill be changed as a result of arithmetic

and logical operations in the processor

( = (egative. S = Sero. % = %arry. > = verflo"

The and ' bits are the interrupt disable bits

The M


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%:2& register itself. 3ach processor mode is either :rivileged or (onHprivileged. A&M has

seven modes. These 8 modes are divided into t"o types.

P%ii/!g!" :'ull readH"rite access to the %:2&. nder this "e are having Ab,%& Fa&

i0&!%%$& %!$!& I0&!%%$& %!$!& S$!%i,%S'&!( a0" U0"!i0!"

Ab,%& 1111 :

"hen there is a failed attempt to access memory

Fa& i0&!%%$& R!$!& FI@11 > i0&!%%$& %!$!&11:

correspond to interrupt levels available on A&M

S$!%i,% (,"!111 :state after reset and generally the mode in "hich 2 kernel

e0ecutes

S'&!( (,"!11111 :

special version of user mode that allo"s full readH"rite access of %:2&

U0"!i0!"1111 :

"hen processor encounters an undefined instruction

N,0%ii/!g!" : nly read access to the control filed of %:2& but readH"rite access to

the condition flags.

U!%1: ser mode is user for programs and applications. And this the normal

mode

Ba0;!" R!gi&!% :

&egister file contains in all 98 registers. 6< registers are hidden from program at different

times. These registers are called banked registers. #anked registers are available only

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"hen the processor is in a particular mode. :rocessor modes )other than system mode* have

a set of associated banked registers that are subset of 7D register

SPSR:SPSR:

3ach privileged mode )e0cept system mode* has associated "ith it a 2ave :rogram 2tatus

&egister, or 2:2&. This 2:2& is used to save the state of %:2& )%urrent program status

&egister* "hen the privileged mode is entered in order that the user state can be fully

restored "hen the user processor is resumed

Mode %hanging =

Mode changes by "riting directly to %:2& or by hard"are "hen the processor responds to

e0ception or interrupt

51

R+&(!+" B'

I&c'!+( !*'! !*+ o"$'# "+&(!+" %(+ ) (+" o" S(!+$ $o+

*'( )++ "+#'c+ ) ' '#!+"'!&+ "+&(!+" (+c&


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To return to user mode a special return instruction is used that instructs the core to restore the

original %:2& and banked registers

ARM I0&%$#&i,0 S!&

n this chapter "e are going to discuss about the most commonly used nstruction 2et

of A&M. !ifferent A&M architectures revisions support different instructions. +o"ever ne"

revisions usually add instructions and remain back"ardly compatible. The follo"ing sho"s

the type of instructions that A&M support.

. !ata :rocessing nstructions

. #ranch nstructions

. $oadHstore nstructions

>. 2oft"are nterrupt nstruction

>. :rogram 2tatus &egister nstructions

I. Da&a P%,#!i0g I0&%$#&i,0 :

The data processing instructions manipulate data "ithin registers. Most data

processing instructions can process one of their operands using the barrel shifter. f "e use

the S suffi0 on a data processing instruction, then it updates the flags in the c&sr* Move and

logical operations update the carry flag %, negative flag (, and Sero flag S. The carry flag is

set from the result of the barrel shift as the last bit shifted out. The ( flag is set to bit 97 of

the result. The S flag is set if the result is zero. The follo"ing instructions are !ata

processing instructions.

i. M,! i0&%$#&i,0: This instruction is used to move the content of one register to another

register. The belo" instructions are the Move instructions

MOV : move a 96Hbit value into a register &dI&2

MOVN : move the (T of the 96 bit value into a register &dI W&2

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ii. Ba%%!/ S6i&!% : A unique and po"erful feature of A&M processor is ability to shift the

96Hbit binary pattern in one of the source registers left or right by a specific number of

positions before it enters the A$. This is done by using the #arrel shifter. This

preprocessing or shift occurs "ithin the cycle time of the instruction. The five different shift

operations that "e can use "ithin the barrel shifter given belo".

$2$ = logical shift left

$2& = logical shift right

A2& = arithmetic right shift

&& = rotate right

&&@ = rotate right e0tended

iii. A%i&6(!&i# I0&%$#&i,0 : The arithmetic instructions implement and subtraction of 96H

bit signed and unsigned values. 2ome of the instructions of Arithmetic instructions are given

belo".

A!! =add t"o 96Hbit values.

A!% =add t"o 96Hbit values and carry

2# =subtract t"o 96Hbit values

2#% = subtract "ith carry of t"o 96Hbit values

&2# = reverse subtract of t"o 96Hbit values

&2% = reverse subtract "ith carry of t"o 96Hbit values

i. L,gi#a/ I0&%$#&i,0 : :erforms the logical operations on t"o source registers

A(! = logical bit"ise A(! of t"o 96Hbit values

&& = logical bit"ise & of t"o 96Hbit values

3& = logical e0clusive & of t"o 96Hbit vlaues.

#% = $ogical bit clear )A(! (T*

. C,(a%i,0 I0&%$#&i,0 : The comparison instructions are used to compare or test a

register "ith a 96 bit value. They update the c&sr flag bits )(, S, %, >* according to the

result, but do not affect other registers. After the bits have been set, the information can then

be used to change program flo" by using conditional e0ecution. 5e do not need to apply the

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S suffi0 for comparison instructions to update the flag. The follo"ing instructions are belong

%omparison instructions

%M: )compare* = flags set as a result of &7H&6

%M( )compare negated* = flags set as a result of &7N&6

T2T )test for equality of t"o 96Hbit values* = flags set as a result of &7X&6

T3Y )test for equality of t"o 96Hbit values* = flags set as a result of &7Z&6

i. M$/&i/' I0&%$#&i,0 : The multiply instructions multiply the content of a pair of

registers and , depending upon the instruction, accumulate the results in "ith another register.

The long multiplies accumulate onto a pair of registers representing a D; bit value. The final

result is placed in a destination register or a pair of registers.

M$ = multiply

M$A = multiply and accumulate

$ong Multiply nstructions =):roduce D; bit values,result "ill be placed in t"o 96 bit values*

2M$A$ = signed multiply accumulate long

2M$$ = signed multiply accumulate

M$A$ = unsigned multiply accumulate long

M$$ = unsigned multiply long

II. B%a0#6 I0&%$#&i,0 : A branch instruction changes the flo" of e0ecution or is used to

call a routine. This type of instruction allo"s programs to have subroutines, i+,then,else

structures, and loops. The change of e0ecution flo" forces the program counter &c to point to

ne" address. The belo" sho"n instructions are #ranch instructions.

# = branch

#$ = branch "ith link

#@ = branch e0change

#$@ = branch e0change "ith link

III. L,a"&,%! I0&%$#&i,0 : $oadHstore instructions transfer data bet"een memory and

processor registers.

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There are three types of loadHstore instructions =

i. single register transferring

ii. Multiple register transfer

iii. 2"ap

Si0g/! %!gi&!% &%a0!%%i0g :These instructions are used for moving a single data item in

and out of a register. The data types supported are signed and unsigned "ords)96Hbit*,

half"ords)7DHbit*, and bytes. The follo"ing instructions are various loadHstore singleHregister

transfer instructions.

$!& = load "ord into a register

2T& = save byte or "ord from a register

$! = load byte into a register

2T = save byte from a register

$!&+ = load half"ord into a register

2T&+ = save half"ord into a register

$!&2# = load signed byte into a register

$!&2+ = load signed half"ord into a register

M$/&i/! %!gi&!% &%a0!% : $oadHstore multiple instructions can transfer multiple registers

bet"een memory and the processor in a single instruction. The transfer occurs from a base

address register Rn pointing into memory. MultipleHregister transfer instructions are more

efficient from singleHregister transfers for moving blocks of data around memory and saving

and restoring conte0t and stacks. f an interrupt has been raised, then it has no effect until the

loadHstore multiple instruction is complete.

$!M = load multiple registers

2TM = save multiple registers

S-a : The s"ap instruction is a special case of a loadHstore instruction. t s"aps the

contents of memory "ith the contents of a register. This instruction is an atoic o&erationH it

reads and "rites a location in the same bus operation, preventing any other instruction from

reading or "riting to that location until it completes.

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IV. S,&-a%! I0&!%%$& I0&%$#&i,0 : A soft"are interrupt instruction ) S-I * causes a

soft"are interrupt e0ception, "hich provides a mechanism for applications to call operating

system routines. The follo"ing instruction comes under soft"are interrupt instruction.

25 = soft"are interrupt

V. P%,g%a( S&a&$ R!gi&!% I0&%$#&i,0 : The A&M instruction set provides t"o

instructions to directly control a program status )&sr *.

M&2 = This instruction transfers the contents of either the c&srors&srinto a register

M2& = This instruction transfers the content of a register into the c&srors&sr

Together the above t"o instructions are used to read and "rite the c&srors&sr

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CHAPTER /

0PC213 MICR4C4$TR400ER

57


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0PC 213 MICR4C4$TR400ER

G!0!%a/ "!#%i&i,0 , LPC 2149:

T*+ LPC2148 $&c"oco!"o##+"( &( )'(+ o ' 32)&! ARM7TDMIS

CP &!* "+'#!&$+ +$%#'!&o ' +$)++ !"'c+ (%o"! !*'! co$)&+

$&c"oco!"o##+"( &!* +$)++ *&*(++ '(* $+$o" "'& "o$ 32 B !o

512 B. A 128)&! &+ $+$o" &!+"'c+ ' %&?%+ 'cc+#+"'!o" '"c*&!+c!%"+

+')#+ 32)&! co+ ++c%!&o '! !*+ $'&$%$ c#oc "'!+. Fo" c"&!&c'# co+ (&;+

'#&c'!&o( !*+ '#!+"'!&+ 16)&! T*%$)

$o+ "+%c+( co+ ) $o"+ !*' 30 : &!* $&&$'# +"o"$'c+ +'#!.

D%+ !o !*+&" !& (&;+ ' #o o+" co(%$!&o

LPC2141/42/44/46/48 '"+ &+'# o" '#&c'!&o( *+"+ $&&'!%"&;'!&o &( ' +

"+?%&"+$+! (%c* '( 'cc+(( co!"o# ' o&!o('#+. S+"&'# co$$%&c'!&o(

&!+"'c+( "'& "o$ ' SB 2.0 F%##(++ +&c+ $%#!+ ART( SPI SSP !o

I2C)%( ' oc*& SRAM o 8 B % !o 40 B $'+ !*+(+ +&c+( +" +##

(%&!+ o" co$$%&c'!&o '!+'( ' "o!oco# co+"!+"( (o! $o+$( o&c+

"+co&!&o ' #o + &$'& "o&& )o!* #'"+ )%+" (&;+ ' *&*

"oc+((& o+". H'"&o%( 32)&! !&$+"( (+ o" %'# 10)&! ADC( 10)&! DAC

PWM c*'+#( ' 45 '(! PIO #&+( &!* % !o &+ ++ o" #++# (+(&!&+

+!+"'# &!+""%! &( $'+ !*+(+ $&c"oco!"o##+"( (%&!')#+ o" &%(!"&'# co!"o#

' $+&c'# ((!+$(.

58


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5eneral o!er!ie6 o in system programming )IP*"

IS(!+$ P"o"'$$& ,ISP- &( ' "oc+(( *+"+) ' )#' +&c+ $o%!+ !o '

c&"c%&! )o'" c' )+ "o"'$$+ &!* !*+ +%(+" co+ &!*o%! !*+ ++ !o

"+$o+ !*+ +&c+ "o$ !*+ c&"c%&! )o'". A#(o ' "+&o%(# "o"'$$+ +&c+

c' )+ +"'(+ ' R+ "o"'$$+ &!*o%! "+$o'# "o$ !*+ c&"c%&! )o'". I

o"+" !o +"o"$ ISP o+"'!&o( !*+ $&c"oco!"o##+" &( o+"+ % & ' (+c&'#

KISP $o+. ISP $o+ '##o( !*+ $&c"oco!"o##+" !o co$$%&c'!+ &!* '

+!+"'# *o(! +&c+ !*"o%* !*+ (+"&'# o"! (%c* '( ' PC o" !+"$&'#. T*+

$&c"oco!"o##+" "+c+&+( co$$'( ' '!' "o$ !*+ *o(! +"'(+( '"+"o"'$( co+ $+$o" +!c. Oc+ !*+ ISP o+"'!&o( *'+ )++ co$#+!+

!*+ +&c+ &( "+co


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So$+ '#&c'!&o( $' *'+ ' ++ !o )+ ')#+ !o +"'(+ ' "o"'$ co+

$+$o" %+" !*+ co!"o# o !*+ '#&c'!&o. Fo" +'$#+ ' '#&c'!&o $'

*'+ ' ++ !o (!o"+ c'#&)"'!&o &o"$'!&o o" +"*'( ++ !o )+ ')#+ !o

o#o' + co+ o"!&o(. T*&( ')&! !o +"'(+ ' "o"'$ co+ $+$o" &

!*+ +%(+" '#&c'!&o &( KIA#&c'!&o P"o"'$$& ,IAP-. T*+ Boo!"o$

"o%!&+( *&c* +"o"$ %c!&o( o !*+ F#'(* $+$o" %"& ISP $o+ (%c* '(

"o"'$$& +"'(& ' "+'& '"+ '#(o ''')#+ !o +%(+" "o"'$(.

T*%( &! &( o((&)#+ o" ' +%(+" '#&c'!&o !o +"o"$ o+"'!&o( o !*+ F#'(*

$+$o". A co$$o +!" o&! ,FFF0*- !o !*+(+ "o%!&+( *'( )++ "o&+ !o

(&$#& &!+"'c& !o !*+ +%(+"( '#&c'!&o. F%c!&o( '"+ +"o"$+ )

(+!!& % (+c&


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-EAT+RE 4- 0PC213)ARM,* ARCHITECT+RE

7ey eatures"

16)&!/32)&! ARM7TDMIS $&c"oco!"o##+" & ' !& LFP64 'c'+

8 B !o 40 B o oc*& (!'!&c RAM ' 32 B !o 512 B o oc*& '(*

$+$o"@ 128)&! &+ &!+"'c+/'cc+#+"'!o" +')#+( *&*(++ 60 M;

o+"'!&o

IS(!+$ P"o"'$$&/IA#&c'!&o P"o"'$$& ,ISP/IAP- &' oc*&)oo! #o'+" (o!'"+ (+ '(* (+c!o" o" %## c*& +"'(+ & 400 $( '

"o"'$$& o 256 B & 1 $(.

E$)++ ICE RT ' E$)++ T"'c+ &!+"'c+( o+" "+'#!&$+

+)%& &!* !*+ oc*& R+'# Mo&!o" (o!'"+ ' *&*(++ !"'c&

o &(!"%c!&o ++c%!&o

SB 2.0 F%##(++ co$#&'! +&c+ co!"o##+" &!* 2 B o +o&! RAM

I '&!&o !*+ LPC2146/48 "o&+( 8 B o oc*& RAM 'cc+((&)#+ !o

SB ) DMA

O+ o" !o ,LPC2141/42 ( LPC2144/46/48- 10)&! ADC( "o&+ ' !o!'# o

6/14 ''#o &%!( &!* co+"(&o !&$+( '( #o '( 2.44 $( +" c*'+#

S+ 10)&! DAC "o&+( '"&')#+ ''#o o%!%! ,LPC2142/44/46/48

o#-

To 32)&! !&$+"(/+!+"'# ++! co%!+"( ,&!* o%" c'!%"+ ' o%"

co$'"+

c*'+#( +'c*- PWM %&! ,(& o%!%!(- ' '!c*o.

Lo o+" R+'#T&$+ C#oc ,RTC- &!* &+++! o+" ' 32 ;

c#oc &%!

M%#!+ (+"&'# &!+"'c+( &c#%& !o ART( ,16C550- !o F'(! I2C)%(

,400 )&!/(-

SPI ' SSP &!* )%+"& ' '"&')#+ '!' #+!* c'')&!&+(

61


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H+c!o"+ I!+""%! Co!"o##+" ,HIC- &!* co

CP o+"'!& o#!'+ "'+ o 3.0 H !o 3.6 H ,3.3 H 10 :- &!* 5 H !o#+"'!

I/O '(.

(04C7 %IA5RAM"

62


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PI$ C4$-I5+RATI4$"

63


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64


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65


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67/119

EI$T8 < E!+"'# &!+""%! 0 &%!

P8.29C089 CAP8.8"

P8.2 < ++"'# %"o(+ &%!/o%!%! &&!'# & ,PIO-

C08 < I2C0 c#oc &%!/o%!%! o+"'& o%!%! ,o" I2C)%( co$#&'c+-

CAP8.8 < C'!%"+ &%! o" T&$+" 0 c*'+# 0

P8./9%A89 MAT8.89EI$T1>

P8./ < ++"'# %"o(+ &%!/o%!%! &&!'# & ,PIO-

%A8 < I2C0 '!' &%!/o%!%! o+"'& o%!%! ,o" I2C)%( co$#&'c+-

MAT8.8 < M'!c* o%!%! o" T&$+" 0 c*'+# 0

EI$T1 < E!+"'# &!+""%! 1 &%!

P8.9C789 CAP8.19A%8.=

P8. < ++"'# %"o(+ &%!/o%!%! &&!'# & ,PIO-

C78 < S+"&'# c#oc o" SPI0 SPI c#oc o%!%! "o$ $'(!+" o" &%! !o (#'+

67


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CAP8.1 < C'!%"+ &%! o" T&$+" 0 c*'+# 0

A%8.= < ADC 0 &%! 6.

P8.>9MI489 MAT8.19A%8.,

P8.> < ++"'# %"o(+ &%!/o%!%! &&!'# & ,PIO-

MI48 < M'(!+" I S#'+ OT o" SPI0 '!' &%! !o SPI $'(!+" o" '!' o%!%!

"o$

SPI (#'+.

MAT8.1 < M'!c* o%!%! o" T&$+" 0 c*'+# 1

A%8., < ADC 0 &%! 7

P8.=9M4I89 CAP8.29A%1.8

P8.= < ++"'# %"o(+ &%!/o%!%! &&!'# & ,PIO-

M4I8 < M'(!+" o%! S#'+ I o" SPI0 '!' o%!%! "o$ SPI $'(!+" o" '!'

I%! !o SPI (#'+

CAP8.2 < C'!%"+ &%! o" T&$+" 0 c*'+# 2

A%1.8 < ADC 1 &%! 0 ''')#+ & LPC2144/46/48 o#

P8.,9E089P;M29EI$T2

68


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P8., < ++"'# %"o(+ &%!/o%!%! &&!'# & ,PIO-

E08 < S#'+ S+#+c! o" SPI0 (+#+c!( !*+ SPI &!+"'c+ '( ' (#'+

P;M2 < P%#(+ W&!* Mo%#'!o" o%!%! 2

EI$T2 < E!+"'# &!+""%! 2 &%!

P8.39T:%19P;M9A%1.1

P8.3 < ++"'# %"o(+ &%!/o%!%! &&!'# & ,PIO-

T:%1


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P8.18 < ++"'# %"o(+ &%!/o%!%! &&!'# & ,PIO-

RT1 < R+?%+(! !o (+ o%!%! o" ART1 LPC2144/46/48 o#

CAP1.8 < C'!%"+ &%! o" T&$+" 1 c*'+# 0

A%1.2 < ADC 1 &%! 2 ''')#+ & LPC2144/46/48 o#

P8.119CT19 CAP1.19C01"

P8.11 < ++"'# %"o(+ &%!/o%!%! &&!'# & ,PIO-

CT1 < C#+'" !o (+ &%! o" ART1 ''')#+ & LPC2144/46/48 o#

CAP1.1 < C'!%"+ &%! o" T&$+" 1 c*'+# 1

C01 < I2C1 c#oc &%!/o%!%! o+"'& o%!%! ,o" I2C)%( co$#&'c+-

P8.129%R19MAT1.89A%1./"

P8.12 < ++"'# %"o(+ &%!/o%!%! &&!'# & ,PIO-

%R1 < D'!' S+! R+' &%! o" ART1 ''')#+ & LPC2144/46/48 o#

MAT1.8 < M'!c* o%!%! o" T&$+" 1 c*'+# 0

A%1./ < ADC &%! 3 ''')#+ & LPC2144/46/48 o#

P8.1/9%TR19 MAT1.19A%1."

70


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P8.1/ < ++"'# %"o(+ &%!/o%!%! &&!'# & ,PIO-

%TR1 < D'!' T+"$&'# R+' o%!%! o" ART1 LPC2144/46/48 o#

MAT1.1 < M'!c* o%!%! o" T&$+" 1 c*'+# 1

A%1. < ADC &%! 4 ''')#+ & LPC2144/46/48 o#

P8.19%C%19EI$T19%A1"

P8.1 < ++"'# %"o(+ &%!/o%!%! &&!'# & ,PIO-

%C%1 < D'!' C'""&+" D+!+c! &%! o" ART1 LPC2144/46/48 o#

EI$T1 < E!+"'# &!+""%! 1 &%!

%A1 < I2C1 '!' &%!/o%!%! o+"'& o%!%! ,o" I2C)%( co$#&'c+ LOW

o !*&( & *+ RESET &( LOW o"c+( oc*& )oo! #o'+" !o !'+ o+" co!"o# o

!*+ '"! '!+" "+(+!

P8.1>9RI19 EI$T29A%1.>"

P8.1> < ++"'# %"o(+ &%!/o%!%! &&!'# & ,PIO-

RI1 < R& I&c'!o" &%! o" ART1 ''')#+ & LPC2144/46/48 o#

EI$T2 < E!+"'# &!+""%! 2 &%!

A%1.> < ADC 1 &%! 5 ''')#+ & LPC2144/46/48 o#

P8.1=9EI$T89MAT8.29CAP8.2"

71


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P8.1= < ++"'# %"o(+ &%!/o%!%! &&!'# & ,PIO-

EI$T8 < E!+"'# &!+""%! 0 &%!

MAT8.2 < M'!c* o%!%! o" T&$+" 0 c*'+# 2

CAP8.2 < C'!%"+ &%! o" T&$+" 0 c*'+# 2

P8.1,9CAP1.29 C719MAT1.2"

P8.1, < ++"'# %"o(+ &%!/o%!%! &&!'# & ,PIO-

CAP1.2 < C'!%"+ &%! o" T&$+" 1 c*'+# 2

C71 < S+"&'# C#oc o" SSP c#oc o%!%! "o$ $'(!+" o" &%! !o (#'+

MAT1.2 < M'!c* o%!%! o" T&$+" 1 c*'+# 2

P8.139CAP1./9MI419MAT1./"

P8.13 < ++"'# %"o(+ &%!/o%!%! &&!'# & ,PIO-

CAP1./ < C'!%"+ &%! o" T&$+" 1 c*'+# 3

MI41 < M'(!+" I S#'+ O%! o" SSP '!' &%! !o SPI $'(!+" o" '!' o%!%!

"o$ SSP (#'+

MAT1./ < M'!c* o%!%! o" T&$+" 1 c*'+# 3

72


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P8.1?9MAT1.29M4I19CAP1.2"

P8.1? < ++"'# %"o(+ &%!/o%!%! &&!'# & ,PIO-

MAT1.2 < M'!c* o%!%! o" T&$+" 1 c*'+# 2

M4I1 < M'(!+" o%! S#'+ I o" SSP '!' o%!%! "o$ SSP $'(!+" o" '!' I%!

!o SSP (#'+

CAP1.2 < C'!%"+ &%! o" T&$+" 1 c*'+# 2

P8.289MAT1./9E019EI$T/"

P8.28 < ++"'# %"o(+ &%!/o%!%! &&!'# & ,PIO-

MAT1./ < M'!c* o%!%! o" T&$+" 1 c*'+# 3

E01 < S#'+ S+#+c! o" SSP (+#+c!( !*+ SSP &!+"'c+ '( ' (#'+

EI$T/ < E!+"'# &!+""%! 3 &%!

P8.219P;M>9A%1.=9CAP1./"

P8.21 < ++"'# %"o(+ &%!/o%!%! &&!'# & ,PIO-

P;M> < P%#(+ W&!* Mo%#'!o" o%!%! 5

A%1.= < ADC 1 &%! 6 ''')#+ & LPC2144/46/48 o#

CAP1./ < C'!%"+ &%! o" T&$+" 1 c*'+# 3

P8.229A%1.,9CAP8.89MAT8.8"

73


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P8.22 < ++"'# %"o(+ &%!/o%!%! &&!'# & ,PIO-

A%1., < ADC 1 &%! 7 ''')#+ & LPC2144/46/48 o#

CAP8.8 < C'!%"+ &%! o" T&$+" 0 c*'+# 0

MAT8.8 < M'!c* o%!%! o" T&$+" 0 c*'+# 0

P8.2/9#(+"

P8.2/ < ++"'# %"o(+ &%!/o%!%! &&!'# & ,PIO-

#(+ < I&c'!+( !*+ "+(+c+ o SB )%( o+"

T*&( (&'# $%(! )+ I o" SB "+(+! !o occ%"

P8.2>9A%8.9A4+T"

P8.2> < ++"'# %"o(+ &%!/o%!%! &&!'# & ,PIO-

A%8. < ADC 0 &%! 4

A4+T < DAC o%!%! ''')#+ & LPC2142/44/46/48 o#

P8.239A%8.19CAP8.29MAT8.2"

74


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P8.23 < ++"'# %"o(+ &%!/o%!%! &&!'# & ,PIO-

A%8.1 < ADC 0 &%! 1

CAP8.2 < C'!%"+ &%! o" T&$+" 0 c*'+# 2

MAT8.2 < M'!c* o%!%! o" T&$+" 0 c*'+# 2

P8.2?9A%8.29CAP8./9MAT8./"

P8.2? < ++"'# %"o(+ &%!/o%!%! &&!'# & ,PIO-

A%8.2 < ADC 0 &%! 2

CAP8./ < C'!%"+ &%! o" T&$+" 0 C*'+# 3

MAT8./ < M'!c* o%!%! o" T&$+" 0 c*'+# 3

P8./89A%8./9EI$T/9CAP8.8"

P8./8 < ++"'# %"o(+ &%!/o%!%! &&!'# & ,PIO-

A%8./ < ADC 0 &%! 3

EI$T/ < E!+"'# &!+""%! 3 &%!

CAP8.8 < C'!%"+ &%! o" T&$+" 0 c*'+# 0

P8./19+P@0E%9C4$$ECT

P8./1 < ++"'# %"o(+ o%!%! o# &&!'# & ,PO-

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+P@0E% < SB oo L& LED &&c'!o" &! &( LOW *+ +&c+ &( co


77/119

P1.13 < ++"'# %"o(+ &%!/o%!%! &&!'# & ,PIO-

TRACEP7T2


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PIPETAT1 < P&+#&+ S!'!%( )&! 1 (!''" I/O o"! &!* &!+"'# %##%

P1.2/9PIPETAT2

P1.2/ < ++"'# %"o(+ &%!/o%!%! &&!'# & ,PIO-

PIPETAT2 < P&+#&+ S!'!%( )&! 2 (!''" I/O o"! &!* &!+"'# %##%

P1.29TRACEC07

P1.2 < ++"'# %"o(+ &%!/o%!%! &&!'# & ,PIO-

TRACEC07


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$ote" LOW o RTCQ *+ RESET &( LOW +')#+( &( P1.31>26 !o o+"'!+ '

D+)% o"! '!+" "+(+!

P1.2,9T%4

P1.2, < ++"'# %"o(+ &%!/o%!%! &&!'# & ,PIO-

T%4


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P1.31/TRST

P1./1 < ++"'# %"o(+ &%!/o%!%! &&!'# & ,PIO-

TRT SB )&&"+c!&o'# D #&+

REET Eternal reset input" A LOW o !*&( & "+(+!( !*+ +&c+ c'%(& I/O

o"!( ' +"&*+"'#( !o !'+ o !*+&" +'%#! (!'!+( ' "oc+((o" ++c%!&o !o

)+& '! '"+(( 0 TTL &!* *(!+"+!&c 5 H !o#+"'!

:TA01> I%! !o !*+ o(c#'!o" c&"c%&! ' &!+"'# c#oc ++"'!o" c&"c%&!(

:TA02> O%!%! "o$ !*+ o(c#'!o" '$#&


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#A Analog ground" 0 H "++"+c+ !*&( (*o%# o$&'## )+ !*+ ('$+

o#!'+ '(

HSS )%! (*o%# )+ &(o#'!+ !o $&&$&;+ o&(+ ' +""o"

#%% 2/D /D >1 I /./ # po6er supply"T*&( &( !*+ o+" (%# o#!'+ o" !*+

co"+ ' I/O o"!(.

#%%A , I Analog /./ # po6er supply" T*&( (*o%# )+ o$&'## !*+ ('$+

o#!'+ '(

HDD )%! (*o%# )+ &(o#'!+ !o $&&$&;+ o&(+ ' +""o" !*&( o#!'+ &( o# %(+

!o o+" !*+ oc*& ADC,(- ' DAC

#RE- A%C reerence !oltage"T*&( (*o%# )+ o$&'## #+(( !*' o" +?%'# !o

!*+

HDD o#!'+ )%! (*o%# )+ &(o#'!+ !o $&&$&;+ o&(+ ' +""o" #++# o !*&(

P& &( %(+ '( ' "++"+c+ o" ADC,(- ' DAC

#(AT RTC po6er supply !oltage" 3.3 H o !*&( & (%#&+( !*+ o+" !o !*+

RTC.

-unctional %escription"

Architectural 4!er!ie6"

T*+ ARM7TDMIS &( ' ++"'# %"o(+ 32)&! $&c"o"oc+((o" *&c*

o+"( *&* +"o"$'c+ ' +" #o o+" co(%$!&o. T*+ ARM '"c*&!+c!%"+

81


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&( )'(+ o R+%c+ I(!"%c!&o S+! Co$%!+" ,RISC- "&c+( ' !*+

&(!"%c!&o (+! ' "+#'!+ +co+ $+c*'&($ '"+ $%c* (&$#+" !*' !*o(+ o

$&c"o "o"'$$+ Co$#+ I(!"%c!&o S+! Co$%!+"( ,CISC-. T*&( (&$#&c&!

"+(%#!( & ' *&* &(!"%c!&o !*"o%*%!

A &$"+((&+ "+'#!&$+ &!+""%! "+(o(+ "o$ ' ($'## ' co(!++c!&+

"oc+((o" co"+. P&+#&+ !+c*&?%+( '"+ +$#o+ (o !*'! '## '"!( o !*+

"oc+((& ' $+$o" ((!+$( c' o+"'!+ co!&%o%(#. T&c'## *+ o+

&(!"%c!&o &( )+& ++c%!+ &!( (%cc+((o" &( )+& +co+ ' ' !*&"

&(!"%c!&o &( )+& +!c*+ "o$ $+$o". T*+ ARM7TDMIS "oc+((o" '#(o

+$#o( ' %&?%+ '"c*&!+c!%"'# (!"'!+ o '( T*%$) *&c* $'+( &! &+'##

(%&!+ !o *&*o#%$+ '#&c'!&o( &!* $+$o" "+(!"&c!&o( o" '#&c'!&o(

*+"+ co+ +(&! &( ' &((%+. T*+ + &+' )+*& T*%$) &( !*'! o ' (%+""+%c+ &(!"%c!&o (+!.

E((+!&'## !*+ ARM7TDMIS "oc+((o" *'( !o &(!"%c!&o (+!(>

T*+ (!''" 32)&! ARM (+!

A 16)&! T*%$) (+!

T*+ T*%$) (+!( 16)&! &(!"%c!&o #+!* '##o( &! !o '"o'c* !&c+ !*+

+(&! o (!''" ARM co+ *+ "+!'&& $o(! o !*+ ARM( +"o"$'c+

''!'+ o+" ' !"'&!&o'# 16)&! "oc+((o" %(& 16)&! "+&(!+"(. T*&( &(

o((&)#+ )+c'%(+ T*%$) co+ o+"'!+( o !*+ ('$+ 32)&! "+&(!+" (+! '(

ARM co+. T*%$) co+ &( ')#+ !o "o&+ % !o 65 : o !*+ co+ (&;+ o ARM

' 160 : o !*+ +"o"$'c+ o ' +?%&'#+! ARM "oc+((o" co+c!+ !o

' 16)&! $+$o" ((!+$. T*+ '"!&c%#'" '(* &$#+$+!'!&o & !*+LPC2141/42/44/46/48 '##o( o" %## (++ ++c%!&o '#(o & ARM $o+. I! &(

"+co$$++ !o "o"'$ +"o"$'c+ c"&!&c'# ' (*o"! co+ (+c!&o( ,(%c*

'( &!+""%! (+"&c+ "o%!&+( ' DSP '#o"&!*$(- & ARM $o+. T*+ &$'c!

o !*+ o+"'## co+ (&;+ # )+ $&&$'# )%! !*+ (++ c' )+ &c"+'(+ ) 30

: o+" T*%$) $o+.

82


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4nChip -lash Program memory"

T*+ LPC2141/42/44/46/48 &co"o"'!+ ' 32 B 64 B 128 B 256 B

' 512 B '(* $+$o" ((!+$ "+(+c!&+#. T*&( $+$o" $' )+ %(+ o")o!* co+ ' '!' (!o"'+. P"o"'$$& o !*+ '(* $+$o" $' )+

'cco$#&(*+ & (++"'# '(. I! $' )+ "o"'$$+ I S(!+$ &' !*+ (+"&'#

o"!. T*+ '#&c'!&o "o"'$ $' '#(o +"'(+ '/o" "o"'$ !*+ '(* *+ !*+

'#&c'!&o &( "%& '##o& ' "+'! +"++ o +&)&! o" '!' (!o"'+


84/119

T*+ LPC2141/42/44/46/48 $+$o" $' &co"o"'!+( (++"'# &(!&c!

"+&o( '( (*o )+#o.

84


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Interrupt controller"

T*+ H+c!o"+ I!+""%! Co!"o##+" ,HIC- 'cc+!( '## o !*+

&!+""%! "+?%+(! &%!( ' c'!+o"&;+( !*+$ '( F'(! I!+""%! R+?%+(! ,FI-+c!o"+ I!+""%! R+?%+(! ,IR- ' o+c!o"+ IR '( +


86/119

Interrupt ources"

E'c* +"&*+"'# +&c+ *'( o+ &!+""%! #&+ co+c!+ !o !*+

H+c!o"+ I!+""%! Co!"o##+" )%! $' *'+ (++"'# &!+"'# &!+""%! '(.I&&%'# &!+""%! '( $' '#(o "+"+(+! $o"+ !*' o+ &!+""%! (o%"c+.

Pin Connect (locF"

T*+ & co+c! )#oc '##o( (+#+c!+ &( o !*+ $&c"oco!"o##+" !o

*'+ $o"+ !*' o+ %c!&o. Co


87/119

PIO "+&(!+"( '"+ "+#oc'!+ !o !*+ ARM #oc'# )%( o" !*+ '(!+(! o((&)#+ I/O

!&$&

M'( "+&(!+"( '##o !"+'!& (+!( o o"! )&!( '( ' "o% #+'& o!*+" )&!(

%c*'+

A## PIO "+&(!+"( '"+ )!+ '"+((')#+

E!&"+ o"! '#%+ c' )+ "&!!+ & o+ &(!"%c!&o

B&!#++# (+! ' c#+'" "+&(!+"( '##o ' (+ &(!"%c!&o !o (+! o" c#+'" '

%$)+" o )&!( & o+ o"!

D&"+c!&o co!"o# o &&&%'# )&!(

S+'"'!+ co!"o# o o%!%! (+! ' c#+'"

A## I/O +'%#! !o &%!( '!+" "+(+!

18 Git A%C"

T*+ LPC2141/42 co!'& o+ ' !*+ LPC2144/46/48 co!'& !o ''#o

!o &&!'# co+"!+"(. T*+(+ co+"!+"( '"+ (+ 10)&! (%cc+((&+

'"o&$'!&o ''#o !o &&!'# co+"!+"(. W*+ ADC0 *'( (& c*'+#( ADC1

*'( +&*! c*'+#(. T*+"+o"+ !o!'# %$)+" o ''')#+ ADC &%!( o"

LPC2141/42 &( 6 ' o" LPC2144/46/48 &( 14.

18 Git %AC"

T*+ DAC +')#+( !*+ LPC2141/42/44/46/48 !o ++"'!+ ' '"&')#+

''#o o%!%!. T*+ $'&$%$ DAC o%!%! o#!'+ &( !*+ HREF o#!'+.

87


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+( 2.8 %e!ice controller"

T*+ SB &( ' 4&"+ (+"&'# )%( !*'! (%o"!( co$$%&c'!&o )+!++ '

*o(! ' ' %$)+" ,127 $'- o +"&*+"'#(. T*+ *o(! co!"o##+" '##oc'!+( !*+

SB )'&!* !o

A!!'c*+ +&c+( !*"o%* ' !o+ )'(+ "o!oco#. T*+ )%( (%o"!( *o! #%&

%#%& ' '$&c co


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'%!oCTS/RTS oco!"o# %c!&o( '"+ %## &$#+$+!+ & *'"'"+ ,ART1 &

LPC2144/46/48 o#-.

I2C (us erial I94 Controller

T*+ LPC2141/42/44/46/48 +'c* co!'&( !o I2C)%( co!"o##+"(.

T*+ I2C)%( &( )&&"+c!&o'# o" &!+"IC co!"o# %(& o# !o &"+(> ' (+"&'#

c#oc #&+ ,SCL- ' ' (+"&'# '!' #&+ ,SDA-. E'c* +&c+ &( "+co&;+ ) '

%&?%+ '"+(( ' c' o+"'!+ '( +&!*+" ' "+c+&+"o# +&c+ ,+.. ' LCD

"&+" o" ' !"'($&!!+" &!* !*+ c'')&! !o )o!* "+c+&+ ' (+ &o"$'!&o

,(%c* '( $+$o"--. T"'($&!!+"( '/o" "+c+&+"( c' o+"'!+ & +&!*+" $'(!+" o"

(#'+ $o+ ++& o *+!*+" !*+ c*& *'( !o &&!&'!+ ' '!' !"'(+" o" &(

o# '"+((+. T*+ I2C)%( &( ' $%#!&$'(!+" )%(@ &! c' )+ co!"o##+ ) $o"+

!*' o+ )%( $'(!+" co+c!+ !o &!. T*+ I2C)%( &$#+$+!+ &LPC2141/42/44/46/48 (%o"!( )&! "'!+( % !o 400 )&!/( ,F'(! I2C)%(-.

PI erial I94 Controller"

T*+ LPC2141/42/44/46/48 +'c* co!'& o+ SPI co!"o##+". T*+ SPI &(

' %## %#+ (+"&'# &!+"'c+ +(&+ !o *'#+ $%#!+ $'(!+"( ' (#'+(

co+c!+ !o ' &+ )%(. O# ' (+ $'(!+" ' ' (+ (#'+ c'

co$$%&c'!+ o !*+ &!+"'c+ %"& ' &+ '!' !"'(+". D%"& ' '!'

!"'(+" !*+ $'(!+" '#'( (+( ' )!+ o '!' !o !*+ (#'+ ' !*+ (#'+

'#'( (+( ' )!+ o '!' !o !*+ $'(!+".

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P erial I94 Controller

T*+ LPC2141/42/44/46/48 +'c* co!'&( o+ SSP. T*+ SSP

co!"o##+" &( c'')#+ o o+"'!&o o ' SPI 4&"+ SSI o" M&c"o &"+ )%(. I! c'&!+"'c! &!* $%#!+ $'(!+"( ' (#'+( o !*+ )%(. o++" o# ' (+

$'(!+" ' ' (+ (#'+ c' co$$%&c'!+ o !*+ )%( %"& ' &+ '!'

!"'(+". T*+ SSP (%o"!( %## %#+ !"'(+"( &!* '!' "'$+( o 4 )&!( !o 16

)&!( o '!' o& "o$ !*+ $'(!+" !o !*+ (#'+ ' "o$ !*+ (#'+ !o !*+

$'(!+". O!+ o# o+ o !*+(+ '!' o( c'""&+( $+'&%# '!'.

5eneral Purpose timers9eternal e!ent counters

T*+ T&$+"/Co%!+" &( +(&+ !o co%! cc#+( o !*+ +"&*+"'#

c#oc ,PCLQ- o" ' +!+"'## (%#&+ c#oc ' o!&o'## ++"'!+ &!+""%!( o"

+"o"$ o!*+" 'c!&o( '! (+c&


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Real Time ClocF"

T*+ RTC &( +(&+ !o "o&+ ' (+! o co%!+"( !o $+'(%"+ !&$+

*+ o"$'# o" + o+"'!& $o+ &( (+#+c!+. T*+ RTC *'( )++ +(&+ !o

%(+ #&!!#+ o+" $'& &! (%&!')#+ o" )'!!+" o+"+ ((!+$( *+"+ !*+ CP

&( o! "%& co!&%o%(# ,I#+ $o+-.

Pulse 6idth modulator

T*+ PWM &( )'(+ o !*+ (!''" !&$+" )#oc ' &*+"&!( '## o &!(

+'!%"+( '#!*o%* o# !*+ PWM %c!&o &( &+ o%! o !*+

LPC2141/42/44/46/48. T*+ !&$+" &( +(&+ !o co%! cc#+( o !*+ +"&*+"'#

c#oc ,PCLQ- ' o!&o'## ++"'!+ &!+""%!( o" +"o"$ o!*+" 'c!&o( *+

(+c&


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(&c+ !*+ "++!&!&o "'!+ &( !*+ ('$+ o" '## PWM o%!%!(. W&!* o%)#+ ++

co!"o##+ PWM o%!%!( (+c&

Oc*& &!+"'!+ o(c#'!o" o+"'!+( &!* +!+"'# c"(!'# &

"'+ o 1 M; !o 25 M;. T*+ o(c#'!o" o%!%! "+?%+c &( c'##+ o(c ' !*+

ARM "oc+((o" c#oc "+?%+c &( "++""+ !o '( CCLQ o" %"o(+( o "'!+

+?%'!&o( +!c. o(c ' CCLQ '"+ !*+ ('$+ '#%+ %#+(( !*+ PLL &( "%& '

co+c!+.

2. P00"

T*+ PLL 'cc+!( ' &%! c#oc "+?%+c & !*+ "'+ o 10

M; !o 25 M;. T*+ &%! "+?%+c &( $%#!&+ % &!o !*+ "'+ o 10 M; !o

60 M; &!* ' C%""+! Co!"o##+ O(c#'!o" ,CCO-. T*+ $%#!&+" c' )+ '

&!++" '#%+ "o$ 1 !o 32 ,& "'c!&c+ !*+ $%#!&+" '#%+ c'o! )+ *&*+"

!*' 6 o !*&( '$ o $&c"oco!"o##+"( %+ !o !*+ %+" "+?%+c #&$&! o !*+

CP-. T*+ CCO o+"'!+( & !*+ "'+ o 156 M; !o 320 M; (o !*+"+ &( '

'&!&o'# &&+" & !*+ #oo !o ++ !*+ CCO &!*& &!( "+?%+c "'+ *+

!*+ PLL &( "o&& !*+ +(&"+ o%!%! "+?%+c. T*+ o%!%! &&+" $' )+ (+!

!o &&+ ) 2 4 8 o" 16 !o "o%c+ !*+ o%!%! c#oc. S&c+ !*+ $&&$%$ o%!%!

&&+" '#%+ &( 2 &! &( &(%"+ !*'! !*+ PLL o%!%! *'( ' 50 : %! cc#+. T*+ PLL

&( !%"+ o ' )'((+ o##o& ' c*& "+(+! ' $' )+ +')#+ )

(o!'"+. T*+ "o"'$ $%(! co


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/. Reset and ;aFe up Timer"

R+(+! *'( !o (o%"c+( o !*+ LPC2141/42/44/46/48> !*+

RESET & ' '!c*o "+(+!. T*+ RESET & &( ' Sc*$&!! !"&+" &%! & &!*

' '&!&o'# #&!c*


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=. Eternal Interrupt Inputs"

T*+ LPC2141/42/44/46/48 &c#%+ % !o &+ ++ o" #++#

(+(&!&+ E!+"'# I!+""%! I%!( '( (+#+c!')#+ & %c!&o(. W*+ !*+ &( '"+

co$)&+ +!+"'# ++!( c' )+ "oc+((+ '( o%" &+++! &!+""%!

(&'#(. T*+ E!+"'# I!+""%! I%!( c' o!&o'## )+ %(+ !o '+% !*+

"oc+((o" "o$ Po+"o $o+. A&!&o'## c'!%"+ &%! &( c' '#(o )+

%(+ '( +!+"'# &!+""%!( &!*o%! !*+ o!&o !o '+ !*+ +&c+ % "o$ Po+"

o $o+.

,. Memory Mapping Control

T*+ M+$o" M'& Co!"o# '#!+"( !*+ $'& o !*+ &!+""%!

+c!o"( !*'! '+'" )+&& '! '"+(( 00000 0000. H+c!o"( $' )+ $'+

!o !*+ )o!!o$ o !*+ oc*& '(* $+$o" o" !o !*+ oc*& (!'!&c RAM. T*&(

'##o( co+ "%& & &+"+! $+$o" ('c+( !o *'+ co!"o# o !*+ &!+""%!(.

3. Po6er Control

T*+ LPC2141/42/44/46/48 (%o"!( !o "+%c+ o+" $o+(> I#+

$o+ '

Po+"o $o+.

I I#+ $o+ ++c%!&o o &(!"%c!&o( &( (%(++ %! +&!*+" '

"+(+! o" &!+""%! occ%"(. P+"&*+"'# %c!&o( co!&%+ o+"'!&o %"& +

$o+ ' $' ++"'!+ &!+""%!( !o c'%(+ !*+ "oc+((o" !o "+(%$+ ++c%!&o.

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I#+ $o+ +#&$&'!+( o+" %(+ ) !*+ "oc+((o" &!(+# $+$o" ((!+$( '

"+#'!+ co!"o##+"( ' &!+"'# )%(+(.

I Po+"o $o+ !*+ o(c#'!o" &( (*%! o ' !*+ c*&

"+c+&+( o &!+"'# c#oc(. T*+ "oc+((o" (!'!+ ' "+&(!+"( +"&*+"'#

"+&(!+"( ' &!+"'# SRAM '#%+( '"+ "+(+"+ !*"o%*o%! Po+"o $o+

' !*+ #o&c #++#( o c*& o%!%! &( "+$'& (!'!&c. T*+ Po+"o $o+ c'

)+ !+"$&'!+ ' o"$'# o+"'!&o "+(%$+ ) +&!*+" ' "+(+! o" c+"!'& (+c&


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18. Emulation and %eGugging"

T*+ LPC2141/42/44/46/48 (%o"! +$%#'!&o ' +)%& &' '

TA (+"&'# o"!. A !"'c+ o"! '##o( !"'c& "o"'$ ++c%!&o. D+)%& '

!"'c+ %c!&o( '"+ $%#!++ o# &!* PIO( o Po"! 1. T*&( $+'( !*'! '##

co$$%&c'!&o !&$+" ' &!+"'c+ +"&*+"'#( "+(&& o Po"!0 '"+ ''')#+

%"& !*+ ++#o$+! ' +)%& *'(+ '( !*+ '"+ *+ !*+ '#&c'!&o

&( "% & !*+ +$)++ ((!+$

11. EmGedded ICE

S!''" ARM E$)++ ICE #o&c "o&+( oc*& +)%

(%o"!. T*+ +)%& o !*+ !'"+! ((!+$ "+?%&"+( ' *o(! co$%!+" "%&

!*+ +)%+" (o!'"+ ' ' E$)++ ICE "o!oco# co+"!+". E$)++ ICE

"o!oco# co+"!+" co+"!( !*+ "+$o!+ +)% "o!oco# co$$'( !o !*+ TA

'!' +++ !o 'cc+(( !*+ ARM co"+.

T*+ ARM co"+ *'( ' D+)% Co$$%&c'!&o C*'+# ,DCC- %c!&o)%!&. T*+ DCC '##o( ' "o"'$ "%& o !*+ !'"+! !o co$$%&c'!+ &!*

!*+ *o(! +)%+" o" 'o!*+" (+'"'!+ *o(! &!*o%! (!o& !*+ "o"'$ o

o" ++ +!+"& !*+ +)% (!'!+. T*+ DCC &( 'cc+((+ '( ' co"oc+((o" 14 )

!*+ "o"'$ "%& o !*+ ARM7TDMIS co"+. T*+ DCC '##o( !*+ TA o"! !o

)+ %(+ o" (+& ' "+c+&& '!' &!*o%! '+c!& !*+ o"$'# "o"'$

o. T*+ DCC '!' ' co!"o# "+&(!+"( '"+ $'+ & !o '"+((+( & !*+

E$)++ ICE #o&c.

12. EmGedded Trace"

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S&c+ !*+ LPC2141/42/44/46/48 *'+ (&&


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&'! is an acronym for Ra"io .requenc# I"enti+ication* n

general terms, &'! is a means of identifying a person or object using a radio frequency

transmission. n other "ords &'! is an electronic method of e0changing data over radio

frequency "aves. The technology can be used to identify, track, sort or detect a "ide variety

of objects.

There are three major components to a &'! system: T%a0,0"!%)Tag*, A0&!00a

and a C,0&%,//!%. %ommunication takes place bet"een a &eader )some times called

interrogator* and a Transponder /Silicon Chi& connecte" to an antenna(often called a Tag*

RFID SYSTEM

n a typical &'! system tags are attached to objects. 3ach tag has a

certain amount of internal memory )33:&M* in "hich it stores information about the

object, such as its $0i$! ID )serial* number, or in some cases more details including

manufacture date and product composition. 5hen these tags pass through a field generated

by a reader, they transmit this information back to the reader, thereby identifying the object.

ntil recently the focus of &'! technology "as mainly on tags

and readers "hich "ere being used in systems "here relatively lo" volumes of data are

involved. This is no" changing as &'! in the supply chain is e0pected to generate huge

volumes of data, "hich "ill have to be filtered and routed to the backend T systems. To

solve this problem companies have developed special soft"are packages called savants,

"hich act as buffers bet"een the &'! front end and the T backend. 2avants are the

equivalent to middle"are in the T industry.

COMMUNICATION

The C,(($0i#a&i,0process bet"een the R!a"!%and Tagis

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managed and controlled by one of several protocols, such as the 2 7CDB9 and 2 7


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ACTIVE TAGS:

These tags have integrated batteries for po"ering the chip. Active Tags are po"ered

by batteries and either have to be recharged, have their batteries replaced or be disposed of

"hen the batteries fail.

PASSIVE TAGS:

:assive tags are the tags that do not have batteries and have indefinite life

e0pectancies.

Di!%!0& &'! , &ag

Tags come in a variety of shapes and sizes. Tags can be attached to various objects. These

objects include products, cartons, totes, pallets, parts, assemblies in manufacturing, cars,

trucks, physical assets, etc. Tags come in various forms including 2mart cards, Tags, $abels,

"atches and even embedded in mobile phones. Tags are sold in various types. These include

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adhesive back labels, credit card shaped laminate, scre" do"n plastic assemblies and a host

of other types of tags.

ANTENNA

The Antenna is a device that either reads data from tags or, in some cases,

"rites data to tags using radio 'requency "aves. Antenna-s come in all shapes and sizes

depending on the environment or the required range. Antennas can be mounted on the floor,

to sides of conveyors, on lift trucks, or on building structures.

Antennas come in all sorts of sizes and shapes. The size of the antennadetermines the range of the application. $arge antennas used "ith Active Tags can have a

range of 7


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RFID FREQUENCIES

Tags and Antennas are tuned or matched much the same "ay as a radio istuned to a frequency to receive different channels. These frequencies are grouped into 'our

basic ranges= $o" 'requency, +igh 'requency, >ery +igh 'requency and ltraH+igh

'requencies. The communication frequencies used depends to a large e0tent on the

application, and range from 76C +z to 6.;C ?+z.

3ach frequency range has its advantages and disadvantages. 3urope uses

D M+z. for its +' applications "hile the 2 uses B7C M+z. for its +' applications.

Uapan does not allo" the use of the +' frequency for &'! applications. $o" 'requency

tags )$'* are less costly to manufacturer than ltra +igh 'requency )+'* tags. +' tags

offer better read/"rite range and can transfer data faster then other tags. +' tags "ork best atclose range but are more effective at penetrating nonHmetal objects especially objects "ith

high "ater content.

ANTI-COLLISION:

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f many tags are present then they "ill all reply at the same time, "hich

at the reader end is seen as a signal collision and an indication of multiple tags. The reader

manages this problem by using an antiHcollision algorithm designed to allo" tags to be sorted

and individually selected. There are many different types of algorithms )#inary Tree,

Aloha....* "hich are defined as part of the protocol standards. The number of tags that can be

identified depends on the frequency and protocol used, and can typically range from C< tags /

s for +' and up to 6


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PIN NO. SIGNAL DESCRIPTION

:in (o = D T0!Transmit data )TT$ level* output from

module to serial interface

:in (o = ;

5iegand !ATA +?+

) available in 5iegand *t "ill give !ATA +?+ signal.

:in (o = &0!&eceive data )TT$ level* input to the

module from serial interface

:in (o = 76 #uzzer )active lo"*#uzzer "ill buzz for 6< ms "hen tag

is detected

:in (o = 79 $3! ) active lo"*$3! "ill glo" for 6< ms "hen tag is

detected

:in (o = 7;

5iegand !ATA $5

) available in 5iegand *

t "ill give !ATA $5 signal.

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:in (o=68,6 Antenna nput $oop Antenna should be connected.

USES , RFID

'or many years &'! technology has been used for tracking livestock on farms. Tags

are installed either on or under the skin of animals. These tags store information about

the animal such as its identification number, its medical history, and its "eight and

age. #eing able to identify the needs of an animal during feeding and medical

attention "ithout having to look up the animals history in ed logs saves the farm

considerable time and money.

2ome airports currently use &'! technology to track and sort baggage in the

terminal. This allo"s for a completely automated baggage handling facility.

%urrently the applications of &'! include material handling, logistics, "arehousing,

manufacturing, personal identification and many more applications. 2imply put,

applications are limited only by your imagination.

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ADVANTAGES OF RFID

&'! technology is frequently compared to #arcode technology. 5hile &'!technology "ill probably never replace #arcode technology, it does have many advantages.

The follo"ing is a list of a fe" of these advantages=

[ 4ou must have -$ine of 2ightP to read a barcode label.

[ &'! tags can be placed inside containers or on surfaces that are not in the line of

sight from the antenna.[ &'! technology has a longer read range compared to #arcode Technology.

[ %onsiderably more data can be stored on &'! tags than on a #arcode label.

[ 4ou cannot "rite to a barcode label "hereas some &'! tags have &ead/5rite capabilities.

.

RFID R!a"!% RKI1513

The &'! reader sends a pulse of radio energy to the tag and listens for the tag1sresponse. The tag detects this energy and sends back a response that contains the tag1s serial

number and possibly other information as "ell.

n simple &'! systems, the reader1s pulse of energy functioned as an onHoff s"itch

in more sophisticated systems, the reader1s &' signal can contain commands to the tag,

instructions to read or "rite memory that the tag contains, and even pass"ords.

+istorically, &'! reader "ere designed to read only a particular king of tag,but soH

called ultio"e rea"ers that can read many different kinds of tags are becoming

increasingly popular.&'! readers are usually on, continually transmitting radio energy and

a"aiting any tags that enter their field of operation. +o"ever, for some applications, this is

unnecessary and could be undesirable in batteryHpo"ered devices that need to conserve

energy. Thus, t is possible to configure an &'! reader so that it sends the radio pulse only

in response to an e0ternal event. 'or e0ample, most electronic toll collection systems have

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the reader constantly po"ered up so that every passing car "ill be recorded. n the other

hand, &'! scanners used in veterinarian1s offices are frequently equipped "ith triggers and

po"er up the only "hen the trigger is pulled.

$ike the tag themselves, &'! readers come in many size. The largest readers might

consist of a desktop personal computer "ith a special card through shielded cable. 2uch A

reader "ould typically have a n

RFID Based ATM System

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