Review: Decision Feedback Equalization 기술을이용한 …
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Review: Decision Feedback Equalization 기술을이용한인체통신의장점과단점
Byungsub Kim
Department of Electrical Engineering
Pohang University of Science and Technology
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Embedded System Architecture Lab
Department of Electrical Engineering
• 인체 통신
• Early Works of Body Channel Communication
• High-Speed Body Channel Communication
Wideband TRX with Walsh Code
RF-based Full-Duplex TRX
DFE-base TRX
• Conclusion
2
Outline
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인체통신
Review: Decision Feedback Equalization 기술을 이용한
인체통신의 장점과 단점
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Embedded System Architecture Lab
Department of Electrical Engineering 4
응용분야
Cochlear Implant
Earset
Defibrillator
Pacemaker
Artificial Pancreas
Capsule EndoscopePhysiological monitoring
Retinal Implant
Neural recordingDBS
Hub
ECGEMG
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Embedded System Architecture Lab
Department of Electrical Engineering 5
응용분야
Entertainment
Military
Fitness (Sports)
Ambient Intelligence
Consumer Electronics
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Embedded System Architecture Lab
Department of Electrical Engineering 6
인체통신의종류
[2]
[1]
-
[5] J. Bae et al., JSSC, 2012
[2] A. Fort et al., JSAC, 2006[4] J. Bae et al., ISSCC, 2011
DBS
Smart
watch
Narrowband (NB)
Ultra-wideband (UWB)
Body-channel communication (B
CC)
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Early Works
Review: Decision Feedback Equalization 기술을 이용한
인체통신의 장점과 단점
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Embedded System Architecture Lab
Department of Electrical Engineering 8
Pioneer from MIT – Radio Frequency (RF) technique
Probably, the first human-body communication (1995)
2.4kb/s data rate OOK (400 mW)
[6] Z. G. Thomas, “Personal Area Network (PAN): Near-Field Intra-Body Communication ”,
M.S. Thesis, Media Arts and Science, MIT, Sept., 1995.
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Embedded System Architecture Lab
Department of Electrical Engineering 9
ECG monitoring system from Japan – RF technique
[7] T. Handa et al. "A very low-power consumption wireless ECG monitoring system using body as a signal transmission medium," International
Conference on Solid State Sensors and Actuators, Transducers, Chicago, IL, vol.2, pp. 1003-1006, 1997.
Analog ECG signal is transmitted; it is modulated by PWM at baseband and up
converted by OOK.
The RX recovers the analog ECG signal.
8 μW power consumption is reported.
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Embedded System Architecture Lab
Department of Electrical Engineering
Audio system
Baseband NRZ transmission
Clock and data recovery (CDR)
2 Mb/s @ 5 mW
10
Audio Player from KAIST – Baseband technique
[8] S. J. Song, S. J. Lee, N. Cho and H. j. Yoo, "Low Power Wearable Audio Player Using
Human Body Communications," 10th IEEE International Symposium on Wearable Computers,
Montreux, pp. 125-126, 2006.
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High-Speed Body Channel Communication
Review: Decision Feedback Equalization 기술을 이용한
인체통신의 장점과 단점
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Wideband TRX with Walsh Code
Review: Decision Feedback Equalization 기술을 이용한
인체통신의 장점과 단점
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Embedded System Architecture Lab
Department of Electrical Engineering
16b Walsh code is used for robustness and channel selectivity.
Fundamental redundancy of Walsh code.
Only codes of 7-14 are used 3 b/code
160MHz clock 10M code/s x 3 b/code 30 Mb/s
13
Wideband TRX with Walsh Code
4b Walsh code example.
• 0000 <-1, -1, -1, -1>
• 0101 <-1, 1, -1, 1 >
• 0011 <-1, -1, 1, 1 >
• 0110 <-1, 1, 1, -1>
𝑊2𝑛=𝑊𝑛 𝑊𝑛𝑊𝑛 𝑊𝑛
𝑊1=0
Walsh code: all codes are orthogonal.
𝑊2=0 00 1
𝑊4=
0 00 1
0 00 1
0 00 1
1 11 0
[3] J. Lee et al. “A 60 Mb/s wideband BCC transceiver with 150 pJ/b RX and 31 pJ/b TX for emerging wearable applications,” IEEE Int.
Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, Feb. 2014, pp. 498–499
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Embedded System Architecture Lab
Department of Electrical Engineering 14
4b Walsh Code Example
Two codes are added and transmitted (3-level modulation).
30 Mb/s x 2 60Mb/s at most.
[3] J. Lee et al. “A 60 Mb/s wideband BCC transceiver with 150 pJ/b RX and 31 pJ/b TX for emerging wearable applications,” IEEE Int.
Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, Feb. 2014, pp. 498–499
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Embedded System Architecture Lab
Department of Electrical Engineering 15
Wideband TRX with Walsh Code
Analog equalization is used to compensate channel distortion.
However, equalization capability of analog front-end is not enough.
Walsh code modulation/demodulation require significant power and area.
[3] J. Lee et al. “A 60 Mb/s wideband BCC transceiver with 150 pJ/b RX and 31 pJ/b TX for emerging wearable applications,” IEEE Int.
Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, Feb. 2014, pp. 498–499
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Embedded System Architecture Lab
Department of Electrical Engineering
Wideband Digital-Friendly Transceiver (1.122 mm2)
Walsh-coding TX
Maximum data rate of 60 Mb/s.
Only when Tx and Rx are placed proximity.
Power consumption of 181 pJ/b.
16
Wideband TRX with Walsh Code
ISSCC’ 14
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RF-based Full-Duplex TRX
Review: Decision Feedback Equalization 기술을 이용한
인체통신의 장점과 단점
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Embedded System Architecture Lab
Department of Electrical Engineering
Three bands are used avoiding FM-radio interference.
Two modes: Entertainment (ET) Mode; Healthcare (HC) Mode
ET-mode : fast (80 Mb/s), BPSK
HC-mode : slow (100 kb/s), ultra-low power (42.5 uW), OOK
18
RF-based Full-Duplex Transceiver
[1] H. Cho et al. "A 79 pJ/b 80 Mb/s Full-Duplex Transceiver and a 42.5μW 100 kb/s Super-Regenerative
Transceiver for Body Channel Communication," IEEE Journal of Solid-State Circuits, vol. 51, no. 1, pp. 310-317,
Jan. 2016
80-110 MHz
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Embedded System Architecture Lab
Department of Electrical Engineering
ET-mode consists of H-band (40 Mb/s) and L-band (40 Mb/s).
Half-duplex mode: H-band (40 Mb/s) + L-band (40 Mb/s) 80 Mb/s at
most
19
RF-based Full-Duplex Transceiver
[1] H. Cho et al. "A 79 pJ/b 80 Mb/s Full-Duplex Transceiver and a 42.5μW 100 kb/s Super-Regenerative
Transceiver for Body Channel Communication," IEEE Journal of Solid-State Circuits, vol. 51, no. 1, pp. 310-317,
Jan. 2016
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Embedded System Architecture Lab
Department of Electrical Engineering
On-chip RC-duplexer is used.
RC-notch filters are used. large area
C-bank is used to compensate for the mismatch/variation.
20
RF-based Full-Duplex Transceiver
[1] H. Cho et al. "A 79 pJ/b 80 Mb/s Full-Duplex Transceiver and a 42.5μW 100 kb/s Super-Regenerative
Transceiver for Body Channel Communication," IEEE Journal of Solid-State Circuits, vol. 51, no. 1, pp. 310-317,
Jan. 2016
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Embedded System Architecture Lab
Department of Electrical Engineering
Interference by L-band’s harmonic frequency.
L-band harmonics are reduced by using a sinusoidal wave.
Wein Bridge Oscillators are used.
21
RF-based Full-Duplex Transceiver
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Embedded System Architecture Lab
Department of Electrical Engineering
Synchronization circuits are shared to reduce power consumption.
22
RF-based Full-Duplex Transceiver
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Embedded System Architecture Lab
Department of Electrical Engineering
Area : 5.76 mm2
Active filters take too large area.
Required for full-duplex operation and FM
filtering.
Maximum data rate 80 Mb/s with -58 dBm.
distance is not reported.
Power consumption of 78.8 pJ/b.
23
RF-based Full-Duplex Transceiver
ET-mode: 5.76 mm2
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DFE-based TRX
Review: Decision Feedback Equalization 기술을 이용한
인체통신의 장점과 단점
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Embedded System Architecture Lab
Department of Electrical Engineering 25
DFE-based Transceiver.
(a)
Vb1
RRX
TX
+ -
d
Vb2
DFE
Clock Phase [UI]
(b)# of DFE taps
(c)
Eye
Heig
ht [m
V]
200
0
-200
0 1 2 3 4 5 6 7 8 9 10
Increasing RRX
-0.2
8UI
0 1 2 3 4 5 6 7 8 9 10
0
0.2
Norm
aliz
ed P
uls
e50Ω
10kΩ
11 1213 1415 16 171819
0.4
0.6
0.8
1.0
CLK
DDD
c8 c7 c1
+-
x
RX+
-
x
-x
...
-...
+c1 c2
c3 c4 c5
c6 c7c8
RRX
[9] J.-H Lee, K. Kim, M. Choi, J.-Y Sim, H.-J Park, and B. Kim,
“A 16.6-pJ/b 150-Mb/s Body-Channel Communication
Transceiver with Decision Feedback Equalization
Improving >200x Area Efficiency,” 2017 IEEE Symposium on
VLSI Circuits (VLSI-Circuits), Kyoto, Japan, 2017
Decision Feedback Equalization is
introduced in BCC for the first time.
Shows feasibility of great
improvement.
Maximum data rate of 150 Mb/s @ 16.6
pJ/b for 20 cm.
Maximum data rate of 100 Mb/s @ 23.5
pJ/b for 100 cm.
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Embedded System Architecture Lab
Department of Electrical Engineering 26
DFE-based Transceiver.
Ba
lun
50Ω
40
mm
25mm
(c)Frequency [MHz]
0 50 500-70
-60
-20
-10
-50
-40
-30
S21 [d
B]
100kHz 1MHz 10MHz 100MHzFrequency
-70
-60
-20
-10
-50
-40
-30
S21 [d
B]
-80
450400350300250200150100
Electrode
Body Channel
Sever channel distortion
DC-blocking nature
Similar to reflective wireline
Channels fits well with DFE.
DC blocking nature
Severe distortion Reflective pulse response
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Embedded System Architecture Lab
Department of Electrical Engineering 27
DFE-based Transceiver
TX Ground
Clock Phase [UI]
-0.2
8UI
0 1 2 3 4 5 6 7 8 9 10
0
0.2
Nor
mal
ized
Pul
se
0.4
0.6
0.8
1.0
c1 c2
c3 c4 c5
c6 c7c8
+
+C1
+C2
+C7
+C8 DFE
0 00 1 0 0
6.67ns0V
1V
150Mb/s data Nora
lized p
uls
e
Clock Phase (UI)
Decision Feedback Equalization (DFE)
Uses the previous bit-decision to compensate for the post-cursor inter-
symbol interference.
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Embedded System Architecture Lab
Department of Electrical Engineering
Termination resistance affects the channel response and amplitude.
Large R increases amplitudes.
Large R increases post-cursor inter-symbol interference (ISI).
• ISI can be compensated by DFE.
28
DFE-based Transceiver
(a)
Vb1
RRX
TX
+ -
d
Vb2
DFE
Clock Phase [UI]
(b)# of DFE taps
(c)
Eye
Heig
ht [m
V]
200
0
-200
0 1 2 3 4 5 6 7 8 9 10
Increasing RRX
-0.2
8UI
0 1 2 3 4 5 6 7 8 9 10
0
0.2
Norm
aliz
ed P
uls
e50Ω
10kΩ
11 1213 1415 16 171819
0.4
0.6
0.8
1.0
CLK
DDD
c8 c7 c1
+-
x
RX+
-
x
-x
...
-...
+c1 c2
c3 c4 c5
c6 c7c8
RRX
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Embedded System Architecture Lab
Department of Electrical Engineering
Termination resistance affects the channel response and amplitude.
Eye height is a function of
DFE count
Termination resistance
29
DFE-based Transceiver
(a)
Vb1
RRX
TX
+ -
d
Vb2
DFE
Clock Phase [UI]
(b)# of DFE taps
(c)
Eye H
eig
ht [m
V]
200
0
-200
0 1 2 3 4 5 6 7 8 9 10
Increasing RRX
-0.2
8UI
0 1 2 3 4 5 6 7 8 9 10
0
0.2
Norm
aliz
ed P
uls
e
50Ω
10kΩ
11 1213 1415 16 171819
0.4
0.6
0.8
1.0
CLK
DDD
c8 c7 c1
+-
x
RX+
-
x
-x
...
-...
+c1 c2
c3 c4 c5
c6 c7c8
RRX
Clock Phase [UI]
Differentia
l V
oltage [m
V]
0
-20
-40
-60
40
20
60
80
-0.2 -0.1 0 0.1 0.2 0.3
45mV22%
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Embedded System Architecture Lab
Department of Electrical Engineering
Unknown channel characteristics
Tx with impedance control.
Tx with strong inverter.
30
DFE-based Transceiver: Transmitter
X40
Ext. Data
PredriverInt. Pattern
Generator
Snapshot96bits
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Embedded System Architecture Lab
Department of Electrical Engineering 31
DFE-based Transceiver: Receiver
Main amplifier
Offset compensator
Tap controller
Slicer & DFETap
controllerIC7
Vin+
Vout+
Vout-
RRX
Vb1
CLK
To external interface
RL
IMAIN
RL
Vb2
RRX
D D D DIOS
OSp OSn
Slicer
Main-ampOffset
Compensator
Vin-
C7 C3 C2 C1
Q1Q2Q3Q7
Q7 Q7
EN7 EN7
EN7P7
EN7
P7
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Embedded System Architecture Lab
Department of Electrical Engineering 32
DFE-based Transceiver: Receiver
Main Amplifier
Linear amplification
Main current + ISIs.
Tap
controllerIC7
Vin+
Vout+
Vout-
RRX
Vb1
CLK
To external interface
RL
IMAIN
RL
Vb2
RRX
D D D DIOS
OSp OSn
Slicer
Main-ampOffset
Compensator
Vin-
C7 C3 C2 C1
Q1Q2Q3Q7
Q7 Q7
EN7 EN7
EN7P7
EN7
P7
Clock Phase [UI]
-0.2
8UI
0 1 2 3 4 5 6 7 8 9 10
0
0.2
Norm
aliz
ed P
uls
e
0.4
0.6
0.8
1.0
c1 c2
c3 c4 c5
c6 c7c8N
ora
lized p
uls
e
Clock Phase (UI)
Main
Cursor
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Embedded System Architecture Lab
Department of Electrical Engineering 33
DFE-based Transceiver: Receiver
DFE tap
Subtracting current
Disable option
Polarity control
Tap
controllerIC7
Vin+
Vout+
Vout-
RRX
Vb1
CLK
To external interface
RL
IMAIN
RL
Vb2
RRX
D D D DIOS
OSp OSn
Slicer
Main-ampOffset
Compensator
Vin-
C7 C3 C2 C1
Q1Q2Q3Q7
Q7 Q7
EN7 EN7
EN7P7
EN7
P7
Clock Phase [UI]
-0.2
8UI
0 1 2 3 4 5 6 7 8 9 10
0
0.2
Norm
aliz
ed P
uls
e
0.4
0.6
0.8
1.0
c1 c2
c3 c4 c5
c6 c7c8N
ora
lized p
uls
e
Clock Phase (UI)
Main
Cursor
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Embedded System Architecture Lab
Department of Electrical Engineering 34
DFE-based Transceiver: Receiver
Offset compensator
Offset cancellation
In-situ measurement.
Tap
controllerIC7
Vin+
Vout+
Vout-
RRX
Vb1
CLK
To external interface
RL
IMAIN
RL
Vb2
RRX
D D D DIOS
OSp OSn
Slicer
Main-ampOffset
Compensator
Vin-
C7 C3 C2 C1
Q1Q2Q3Q7
Q7 Q7
EN7 EN7
EN7P7
EN7
P7
Clock Phase [UI]
-0.2
8UI
0 1 2 3 4 5 6 7 8 9 10
0
0.2
Norm
aliz
ed P
uls
e
0.4
0.6
0.8
1.0
c1 c2
c3 c4 c5
c6 c7c8N
ora
lized p
uls
e
Clock Phase (UI)
Main
Cursor
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Embedded System Architecture Lab
Department of Electrical Engineering 35
DFE-based Transceiver
Fabricated in 65nm CMOS
Tx area: 0.00348 mm2 (data path only)
Rx area: 0.0021 mm2 (data path only)
TX Core
RX Core
43μm
81μm
30μm
70μm
TX Peripherals
RX Peripherals
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Embedded System Architecture Lab
Department of Electrical Engineering 36
DFE-based Transceiver: Measurement Set-up
FREQ: CLK_IN BER: 1e-6 PRBS
CH1SYNC
FREQ: 100MHz AMPL: 0.5 PRBS Latop
FPGA
Latop
FPGA
RX Board
RX
LDO
TX Board
TX
LDO
GPIB/LAN
GATEWAY
GPIB
d
RX_GND
TX_GND
Pattern generator
Error detector
Clock generator
CH2
DATACLK
DATACLK
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Embedded System Architecture Lab
Department of Electrical Engineering 37
DFE-based Transceiver: Measurement Set-up
FREQ: CLK_IN BER: 1e-6 PRBS
CH1SYNC
FREQ: 100MHz AMPL: 0.5 PRBS Latop
FPGA
Latop
FPGA
RX Board
RX
LDO
TX Board
TX
LDO
GPIB/LAN
GATEWAY
GPIB
d
RX_GND
TX_GND
Pattern generator
Error detector
Clock generator
CH2
DATACLK
DATACLK
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Embedded System Architecture Lab
Department of Electrical Engineering 38
DFE-based Transceiver: Measurement Set-up
FREQ: CLK_IN BER: 1e-6 PRBS
CH1SYNC
FREQ: 100MHz AMPL: 0.5 PRBS Latop
FPGA
Latop
FPGA
RX Board
RX
LDO
TX Board
TX
LDO
GPIB/LAN
GATEWAY
GPIB
d
RX_GND
TX_GND
Pattern generator
Error detector
Clock generator
CH2
DATACLK
DATACLK
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Embedded System Architecture Lab
Department of Electrical Engineering 39
DFE-based Transceiver: Measurement Set-up
FREQ: CLK_IN BER: 1e-6 PRBS
CH1SYNC
FREQ: 100MHz AMPL: 0.5 PRBS Latop
FPGA
Latop
FPGA
RX Board
RX
LDO
TX Board
TX
LDO
GPIB/LAN
GATEWAY
GPIB
d
RX_GND
TX_GND
Pattern generator
Error detector
Clock generator
CH2
DATACLK
DATACLK
TX Clock
TX Data
Ground decouple
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Embedded System Architecture Lab
Department of Electrical Engineering 40
DFE-based Transceiver: Measurement Set-up
FREQ: CLK_IN BER: 1e-6 PRBS
CH1SYNC
FREQ: 100MHz AMPL: 0.5 PRBS Latop
FPGA
Latop
FPGA
RX Board
RX
LDO
TX Board
TX
LDO
GPIB/LAN
GATEWAY
GPIB
d
RX_GND
TX_GND
Pattern generator
Error detector
Clock generator
CH2
DATACLK
DATACLK
TX Clock
TX Data
Recovered Data
RX Clock
Ground decouple
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Embedded System Architecture Lab
Department of Electrical Engineering 41
DFE-based Transceiver: Measurement Set-up
FREQ: CLK_IN BER: 1e-6 PRBS
CH1SYNC
FREQ: 100MHz AMPL: 0.5 PRBS Latop
FPGA
Latop
FPGA
RX Board
RX
LDO
TX Board
TX
LDO
GPIB/LAN
GATEWAY
GPIB
d
RX_GND
TX_GND
Pattern generator
Error detector
Clock generator
CH2
DATACLK
DATACLK
TX Clock
TX Data
Recovered Data
RX Clock
Wireless
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Embedded System Architecture Lab
Department of Electrical Engineering 42
DFE-based Transceiver: Measurement Reported with a Channel
Clock Phase [UI]
Diffe
rential V
oltage [
mV
]
0
-20
-40
-60
40
20
60
80
-0.2 -0.1 0 0.1 0.2 0.3
45mV22%
0
-20
-40
-60
40
20
60
-0.3 -0.2 -0.1 0 0.1 0.2 0.3
Clock Phase [UI]
Diffe
rential V
oltage [
mV
]
35mV17%
150 Mbps @ 20 cm
100 Mbps @ 100 cmd
= 1
.0m
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Embedded System Architecture Lab
Department of Electrical Engineering 43
Apple-to-Apple Comparison with known distance
ISSCC 2008
d =
1.0
m
X15
X10
For given distance
X15 for ~20 cm
X10 for ~100 cm
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Embedded System Architecture Lab
Department of Electrical Engineering 44
Comparison with recent works
Within
ProximityNo distance
*Within close distance**Improvement compared against prior best
ISSCC ‘14
[3]
JSSC ‘15
[1]This work
Technology 65nm 65nm 65nm
Communication
Scheme3-Level Walsh Coherent BPSK Decision Feedback Equalization
Input Impedance 10KΩ N.A 1kΩ
Target channel * N.A 20cm 1.0m
Data Rate 60Mb/s 40Mb/s 80Mb/s150Mb/s
(x1.9)**
100Mb/s
(x1.25)**
Power
consumption
TX 1.85mWN.A
1.7–2.6mW 0.49mW 0.35mW
RX 9.02mW 6.3mW 2.0mW
Energy/bit 181pJ/b N.A 100–111pJ/b 16.6pJ/b (x6.0)** 23.5pJ/b (x4.3)**
BER 10-3 10-5 N.A 10-5 10-6
(x10)** 10-5 10-6
(x10)**
Received Eye
Height
N.A N.A
57.5mV 35mV 61mV 45mV
Width 0.26UI 0.17UI 0.265UI 0.22UI
AreaTX 0.072mm2
5.76mm20.00348mm2 (x20)**
RX 1.05mm2 0.0021mm2 (x500)**
‘16
78.8 pJ/b
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Embedded System Architecture Lab
Department of Electrical Engineering 45
Comparison with recent works
*Within close distance**Improvement compared against prior best
ISSCC ‘14
[3]
JSSC ‘15
[1]This work
Technology 65nm 65nm 65nm
Communication
Scheme3-Level Walsh Coherent BPSK Decision Feedback Equalization
Input Impedance 10KΩ N.A 1kΩ
Target channel * N.A 20cm 1.0m
Data Rate 60Mb/s 40Mb/s 80Mb/s150Mb/s
(x1.9)**
100Mb/s
(x1.25)**
Power
consumption
TX 1.85mWN.A
1.7–2.6mW 0.49mW 0.35mW
RX 9.02mW 6.3mW 2.0mW
Energy/bit 181pJ/b N.A 100–111pJ/b 16.6pJ/b (x6.0)** 23.5pJ/b (x4.3)**
BER 10-3 10-5 N.A 10-5 10-6
(x10)** 10-5 10-6
(x10)**
Received Eye
Height
N.A N.A
57.5mV 35mV 61mV 45mV
Width 0.26UI 0.17UI 0.265UI 0.22UI
AreaTX 0.072mm2
5.76mm20.00348mm2 (x20)**
RX 1.05mm2 0.0021mm2 (x500)**
Within
ProximityNo distance
Datapath only
No CDR
‘16
78.8 pJ/b
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Embedded System Architecture Lab
Department of Electrical Engineering
• BCC
Ground isolation is important.
Similar to reflective wireline channel.
Allows high-speed energy-efficient communication.
Performance must be reported with distance.
• DFE-based BCC Transceiver shows great potential
High speed: 10x or 15x improvement for the same distance.
Energy efficiency: 4x (data path only)
Area: 1/100 (data path only)
CDR & adaptation are not included.
46
Conclusion
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Embedded System Architecture Lab
Department of Electrical Engineering 47
감사합니다
Special thanks for Ji-Hoon Lee, Jaehyun Ko, Kwangmin Kim, and Mionsoo Choi.
This work is supported by NRF (contract no. 2018R1A4A1025679).
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Embedded System Architecture Lab
Department of Electrical Engineering
• [1] H. Cho et al. "A 79 pJ/b 80 Mb/s Full-Duplex Transceiver and a 42.5μW 100 kb/s Super-Regenerative Transceiver for Body Channel
Communication," IEEE Journal of Solid-State Circuits, vol. 51, no. 1, pp. 310-317, Jan. 2016
• [1] Andrew Fort, Julien Ryckaert, Claude Desset, Philippe De Doncker, Piet Wambacq, and Leo Van Biesen, “Ultra-Wideband Channel
Model for Communication Around the Body,” IEEE Journal on Selected Area in Communications, vol. 24, no. 4, April 2006.
• [3] J. Lee et al. “A 60 Mb/s wideband BCC transceiver with 150 pJ/b RX and 31 pJ/b TX for emerging wearable applications,” IEEE Int.
Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, Feb. 2014, pp. 498–499
• [4] Joonsung Bae, Kiseok Song, Hyungwoo Lee, Hyungwoo Cho, Long Yan, and Hoi-Jun Yoo, “A 0.24nJ/b Wireless Body-Area-Network
Transceiver with Scalable Double-FSK Modulation,” IEEE International Solid-State Circuits Conference, Digest of Technical Papers, 2011.
• [5] Joonsung Bae, Kisok Song, Hyungwoo Lee, Hyunwoo Cho, and Hoi-June Yoo, “A Low-Energy Crystal-Less Double-FSK Sensor
Node Transceiver for Wireless Body-Area Network,” IEEE Journal of Solid-State Circuits, vol. 47, no. 11, Nov. 2012.
• [6] Z. G. Thomas, “Personal Area Network (PAN): Near-Field Intra-Body Communication ”, M.S. Thesis, Media Arts and Science, MIT,
Sept., 1995.
• [7] T. Handa et al. "A very low-power consumption wireless ECG monitoring system using body as a signal transmission
medium," International Conference on Solid State Sensors and Actuators, Transducers, Chicago, IL, vol.2, pp. 1003-1006, 1997.
• [8] S. J. Song, S. J. Lee, N. Cho and H. j. Yoo, "Low Power Wearable Audio Player Using Human Body Communications," 10th IEEE
International Symposium on Wearable Computers, Montreux, pp. 125-126, 2006.
• [9] J.-H Lee, K. Kim, M. Choi, J.-Y Sim, H.-J Park, and B. Kim, “A 16.6-pJ/b 150-Mb/s Body-Channel Communication Transceiver with
Decision Feedback Equalization Improving >200x Area Efficiency,” 2017 IEEE Symposium on VLSI Circuits (VLSI-Circuits), Kyoto, Japan,
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Reference