REVERSIBLE LOGIC SYNTHESIS. Overview of the Presentation 1. Introduction 2. Design of a Reversible...

REVERSIBLE LOGIC SYNTHESIS

Overview of the PresentationOverview of the Presentation

1. Introduction

2. Design of a Reversible Full-adder Circuit

Part 1

Introduction

The gate/circuit that does not loose information is called reversible .What is Reversible Logic / Reversibility ?What is Reversible Logic / Reversibility ?

Input Vector

Iv=( Ii,j , Ii+1,j , Ii+2,j , … , Ik-1,j, Ik,j )

Output Vector

Ov=( Oi,j , Oi+1,j , Oi+2,j , … , Ok-1,j, Ok,j )

For each particular vector j

IvOv

Defn 1: A Reversible circuit has the facility to generate a unique output vector from each input

vector, and vice versa .

What is Reversible Logic / Reversibility ? (cont.)What is Reversible Logic / Reversibility ? (cont.)

Defn 2: Reversible are circuits in which the number of inputs is equal to the number of outputs and there is one-to-one

mapping between vectors of inputs and outputs.

Reversible

Gate

i

ii

ii

1

2

3

K-1

K

O

OO

OO

1

2

3

K

K-1

A gate with k inputs and k outputs is called k*k gate.

Difference Between Reversible Gate and Difference Between Reversible Gate and Irreversible GateIrreversible Gate

Truth Table For Irreversible EXOR Logic

Inputs Output

A B C = A B

0 0 0

0 1 1

1 0 1

1 1 0

Difference Between Reversible Gate and Difference Between Reversible Gate and Irreversible Gate (cont.)Irreversible Gate (cont.)

Truth Table For Reversible EXOR Logic (Feynman Gate)

Inputs Output

A B P=A Q = A B

0 0 0 0

0 1 0 1

1 0 1 1

1 1 1 0

It has been proved ( by Bennett and It has been proved ( by Bennett and Landauer [1]) thatLandauer [1]) that , ,

“losing information in a circuit causes losing power. Information lost when the input vector cannot be uniquely

recovered from the output vector of a combinational circuit”.

The gate/ circuit does not loose information is called reversible.

Motivation Towards Reversible GateMotivation Towards Reversible Gate

Garbage BitGarbage BitEvery gate output that is not used as input

to other gate or as a primary output is called garbage. The unutilized outputs from a gate are called “garbage”. Heavy price is

paid off for every garbage output.

A

B

P = A *

Q = A B

Some Popular Reversible GatesSome Popular Reversible Gates

P = A'A Not Gate

A P

0 1

1 0

1 x 1 Not Gate

Some Popular Reversible Gates (cont.)Some Popular Reversible Gates (cont.)

A

B

P = A

Q = A B

FeynmanGate

A B P Q

0 0 0 0

0 1 0 1

1 0 1 1

1 1 1 0

2 x 2 Feynman Gate (CNOT Gate) [2]

Some Popular Reversible Gates (cont.)Some Popular Reversible Gates (cont.)

A

B Toffoli Gate

C

P = A

Q = B

R = AB C

A B C P Q R

0 0 0 0 0 0

0 0 1 0 0 1

0 1 0 0 1 0

0 1 1 0 1 1

1 0 0 1 0 0

1 0 1 1 0 1

1 1 0 1 1 1

1 1 1 1 1 03 x 3 Toffoli Gate [3]

Some Popular Reversible Gates(cont.)Some Popular Reversible Gates(cont.)

A

B FredkinGate

C

P = A

Q = A'B AC

R = A'C AB

A B C P Q R

0 0 0 0 0 0

0 0 1 0 0 1

0 1 0 0 1 0

0 1 1 0 1 1

1 0 0 1 0 0

1 0 1 1 1 0

1 1 0 1 0 1

1 1 1 1 1 13 x 3 Fredkin Gate [4]


A

B NewGate

C

P = A

Q = AB C

R = A'C' B'

A B C P Q R

0 0 0 0 0 0

0 0 1 0 1 1

0 1 0 0 0 1

0 1 1 0 1 0

1 0 0 1 0 1

1 0 1 1 1 1

1 1 0 1 1 0

1 1 1 1 0 03 x 3 New Gate

(Khan Gate) [5]


A

B PeresGate

C

P = A

Q = A B

R = AB C

A B C P Q R

0 0 0 0 0 0

0 0 1 0 0 1

0 1 0 0 1 0

0 1 1 0 1 1

1 0 0 1 1 0

1 0 1 1 1 1

1 1 0 1 0 1

1 1 1 1 0 03 x 3 Peres Gate[6]

Different Modes of Feynman GateDifferent Modes of Feynman Gate

0

B

P = 0

Q = B

FeynmanGate

All possible cases in 2 x 2 Feynman Gate

A as control input

Output

B as

control input

Output

P Q P Q

0 0 B 0 A A

1 1 B' 1 A A'

1

B

P = 1

Q = B'

FeynmanGate

A

0

P = A

Q = A

FeynmanGate

A

1

P = A

Q = A'

FeynmanGate

Realizations of Irreversible Gates Using Realizations of Irreversible Gates Using Reversible GatesReversible Gates

A

B Toffoli Gate

0

P = A

Q = B

R = AB 0 = AB

Input Output

A B C

0 0 0

0 1 0

1 0 0

1 1 1

A

B

AND GATE

C = AB

AND GATEAND GATE

Realizations of Irreversible Gates Using Realizations of Irreversible Gates Using Reversible Gates(cont.)Reversible Gates(cont.)

A

B Toffoli Gate

1

P = A

Q = B

R = AB 1 = AB

Input Output

A B C

0 0 1

0 1 1

1 0 1

1 1 0

A

B

NAND GATE

C = AB

NAND GATENAND GATE


A

B Toffoli Gate

1

P = A

Q = B

R = A B 1 =A B =A + B

Input Output

A B C

0 0 0

0 1 1

1 0 1

1 1 1

A

B

ORGATE

C = A + B

OR GATEOR GATE


A

B Toffoli Gate

0

P = A

Q = B

R = A B 0 = A + B

Input Output

A B C

0 0 1

0 1 0

1 0 0

1 1 0

A

B

NOR GATE

C = A + B

NOR GATENOR GATE

Reversible Network StructureReversible Network Structure

The main rules for efficient reversible logic synthesis

Use as many outputs of every gate as possible, and thus minimize the garbage outputs.

Do not create more constant inputs to gates that are absolutely necessary.

Avoid leading output signals of gates to more than one input( Fanout).

Don’t use any feedback loop; it is strictly restricted.

Use as less number of reversible gates as possible to achieve the goal.

The main rules for efficient reversible logic synthesis

Part 2

Design of a Reversible Full-adder Circuit

Input Output

A B Cin Sum Cout

0 0 0 0 0

0 0 1 1 0

0 1 0 1 0

0 1 1 0 1

1 0 0 1 0

1 0 1 0 1

1 1 0 0 1

1 1 1 1 1


Sum=A B C

Carry=AB + BC + CA =AB BC CA

Design of a Reversible Full-adder Circuit(cont.)

Sum=A B CCarry=AB + BC + CA =AB BC CA

A

B

EXOR GATE

A BEXOR GATE

Sum

ANDGATE

ANDGATE

ANDGATE

C

EXORGATE

EXORGATE

Carry


Sum=A B C Carry=AB + BC + CA =AB BC CA

A

B

P = A

Q = A B

FeynmanGate

Q = A B C = Sum

FeynmanGate

P = A B

C

Design of a Reversible Full-adder Circuit (cont.)

Sum=A B C Carry =AB BC CA

A

B Toffoli Gate

0

P = A

Q = B

R = AB

B

C Toffoli Gate

0

P = B

Q = C

R = BC

C

A Toffoli Gate

0

P = C

Q = A

R = CA

P = AB

Q = AB BC

FeynmanGate

P = AB BC

Q = AB BC CA= Carry

FeynmanGate

Design of a Reversible Full-adder Circuit (cont.)

Sum=A B C Carry= =AB BC CA = (A C)B CA

A

B Toffoli Gate

0

A

B

AB

C Toffoli Gate

A B

C

(A C)B CA = Carry

A

A B

FeynmanGate

P = A B

Q = A B C = Sum

FeynmanGate

Three GatesThree Gates &&

Three Garbage Three Garbage outputsoutputs

[5][5]

Four GatesFour Gates &&

Two Garbage Two Garbage outputsoutputs

[7][7]

Existing Reversible Full-adder Circuits

Two GatesTwo Gates &&


Three GatesThree Gates &&


Proposed Reversible Full-adder Circuits

Comparative Results

GatesGates Garbage Garbage OutputsOutputs

Existing 1Existing 1 44 22

Existing 2Existing 2 33 33

Proposed 1Proposed 1 33 22

Proposed 2Proposed 2 22 22

Input Section Output Section

A B Cin

Sum (S) Cout

0 0 1 1 0

0 1 0 1 0

1 0 0 1 0

Theorem: A reversible full-adder circuit can be Theorem: A reversible full-adder circuit can be realized with at least two garbage outputsrealized with at least two garbage outputs

A reversible full-adder circuit can be realized A reversible full-adder circuit can be realized with at least two garbage outputs (cont.)with at least two garbage outputs (cont.)


A B Cin

S Cout G1

0 0 1 1 0 0

0 1 0 1 0 0

1 0 0 1 0 1

A reversible full-adder circuit can be realized A reversible full-adder circuit can be realized with at least two garbage outputs (cont.)with at least two garbage outputs (cont.)


A B Cin S Cout G1 G2

0 0 1 1 0 0 0

0 1 0 1 0 0 1

References[1] C. H. Bennett. Logical reversibility of computation, IBM J. Research and Development, 17:pp. 525-532, November 1973. [2] R. Feynman, Quantum Mechanical Computers, Optical News (1985) 11-20.[3] T. Toffoli., Reversible Computing, Tech memo MIT/LCS/TM-151, MIT Lab for Computer Science (1980).

[4] E. Fredkin, T Toffoli, Conservative Logic, International Journal of Theor. Physics, 21(1982), pp.219-253.

[5] Md. M. H Azad Khan, Design of Full-adder with Reversible Gates, International Conference on Computer and Information Technology, Dhaka, Bangladesh, pp 515-519, 2002.

[6] Peres, A., Reversible Logic and Quantum Computers, Physical Review A, 32: 3266-3276, 1985.

[7] A. Mishchenko and M. Perkowski. Logic synthesis of reversible wave cascades. International Workshop on Logic Synthesis, pages 197-202, June 2002.

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REVERSIBLE LOGIC SYNTHESIS

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