Reversible Computing A Brief Introduction Dr. Michael P. Frank [email protected] Dept. of Computer &...

Reversible ComputingReversible ComputingA Brief IntroductionA Brief Introduction

Dr. Michael P. FrankDr. Michael P. [email protected]@cise.ufl.edu

Dept. of Computer & Information Science & EngineeringDept. of Computer & Information Science & Engineering(Affil. Dept. of Electrical & Computer Engineering)(Affil. Dept. of Electrical & Computer Engineering)

University of Florida, Gainesville, FloridaUniversity of Florida, Gainesville, Florida

Presented at:2004 Computing Beyond Silicon Summer School (Week 4)

California Institute of TechnologyPasadena, California, July 6-8, 2004

mailto:[email protected]

http://www.ece.ufl.edu/

AbstractAbstract• The performance of power-limited computing systems is The performance of power-limited computing systems is

directly limited by the energy efficiency of logic operations.directly limited by the energy efficiency of logic operations. Performance Performance (ops / time) = (ops / time) = Power Power (energy dissipated / time)(energy dissipated / time) × ×

Energy efficiency Energy efficiency (ops / energy (ops / energy dissipated)dissipated)

• Traditional logic techniques are approaching a number of Traditional logic techniques are approaching a number of very general physical limits on energy efficiency.very general physical limits on energy efficiency.– Due to quite fundamental thermodynamic considerations.Due to quite fundamental thermodynamic considerations.

• The The onlyonly potential way to circumvent potential way to circumvent allall of these limits is of these limits is through (logically & physically) reversible computing (RC).through (logically & physically) reversible computing (RC).– It is related to quantum computing, but easier in some ways.It is related to quantum computing, but easier in some ways.

• RC appears to be doable, but it is still very challenging…RC appears to be doable, but it is still very challenging…– But, it is a challenge that we But, it is a challenge that we mustmust meet, for continued progress. meet, for continued progress.

• In this talk, we survey fundamental concepts, available In this talk, we survey fundamental concepts, available technologies, and outstanding problems of RC.technologies, and outstanding problems of RC.

http://www.ece.ufl.edu/

Moore’s Law – Devices per ICMoore’s Law – Devices per IC

1

10

100

1,000

10,000

100,000

1,000,000

10,000,000

100,000,000

1,000,000,000

1950 1960 1970 1980 1990 2000 2010

Avg. increaseof 57%/year

4004

8086286

386486DX Pentium

P2P3

P4Itanium 2

Madison

Early Fairchild

ICs

Intel µpu’s

Naïve linear extrapolationsEffective gate oxide thickness

Device Size Scaling TrendsDevice Size Scaling TrendsBased on ITRS ’97-03 roadmaps

(1 µm)

Silicon atom

DNA/CNT radius

Protein molecule

Virus

Hydrogen atom

Practical limit for CMOS?

Naïve linear extrapolation

Trend of Minimum Transistor Switching EnergyTrend of Minimum Transistor Switching Energy

fJ

aJ

zJ

Based on ITRS ’97-03 roadmaps

The Leakage ProblemThe Leakage Problem• The primary traditional approach to decrease energy dissipation per The primary traditional approach to decrease energy dissipation per

logic-op has been:logic-op has been:– Simply decrease the magnitude of the Simply decrease the magnitude of the ½½CVCV22 energy that is stored per bit. energy that is stored per bit.

• This is done by moving to smaller transistor structures, which This is done by moving to smaller transistor structures, which decreases decreases CC and usable and usable VV..– HoweverHowever, as , as VV decreases, there is a problem. decreases, there is a problem.

• An upper bound on the An upper bound on the on/off ratio on/off ratio RRon/offon/off = = IIonon//IIoffoff of transistors is of transistors is given by the relation given by the relation log log RRon/offon/off ≲≲ VV//ss..– The parameter The parameter ss is called the is called the subthreshold slopesubthreshold slope..

• Typical units: Typical units: mV/decademV/decade (decade = log 10) (decade = log 10)• The exact value of The exact value of ss depends on the precise device geometry, depends on the precise device geometry,

– It is reduced by going to multi-gate or surround-gate structures.It is reduced by going to multi-gate or surround-gate structures.• But, But, ss has a fundamental room-temperature has a fundamental room-temperature TT minimum of minimum of

ss ≥ ≥ TT//qq = ( = (kT/qkT/q ln 10)/decade ≈ 60 mV/decade ln 10)/decade ≈ 60 mV/decade in FETs, independent in FETs, independent of materials! (Whether carbon nanotubes, Si nanowires, of materials! (Whether carbon nanotubes, Si nanowires, etc.etc.– This is just due to the ratio between above-barrier state occupancy This is just due to the ratio between above-barrier state occupancy

probabilities for a change in barrier height of probabilities for a change in barrier height of VV. (From Boltzmann distrib.). (From Boltzmann distrib.)• At low voltages (At low voltages (e.g.e.g., a few hundred mV), transistors can’t turn off , a few hundred mV), transistors can’t turn off

effectively, and there is substantial continuous power dissipation.effectively, and there is substantial continuous power dissipation.– Leakage already accounts for as much as 40% of total power in many Leakage already accounts for as much as 40% of total power in many

designs! designs!

A Fairly Conventional “Optimistic” A Fairly Conventional “Optimistic” Technology Scenario for CMOSTechnology Scenario for CMOS

• Suppose device lengths are cut in half every 3 years…Suppose device lengths are cut in half every 3 years…– From 90 nm today down to 22 nm node in 2010 (then stop).From 90 nm today down to 22 nm node in 2010 (then stop).– Node capacitances, gate delays also decrease accordingly…Node capacitances, gate delays also decrease accordingly…

• ““Technology boosters” such as high-Technology boosters” such as high-κκ dielectrics & dielectrics & novel FET structures (FinFET, surround-gate, novel FET structures (FinFET, surround-gate, etc.etc.) ) keep leakage power manageable, for a little while…keep leakage power manageable, for a little while…– However, the absolute minimum room-However, the absolute minimum room-TT subthreshold slope subthreshold slope

for FETs will remain 60 mV/decade! (for FETs will remain 60 mV/decade! (= (= (kTkT//qq)/log 10)/log 10))• Assume this point is also reached by around 2007.Assume this point is also reached by around 2007.

• Voltages then reach a minimum of Voltages then reach a minimum of ~0.5V~0.5V in 2007. in 2007.– Can’tCan’t go lower while keeping on/off ratio above 10 go lower while keeping on/off ratio above 1088 level! level!

• A minimum level chosen so as to keep leakage smallA minimum level chosen so as to keep leakage small

• Now, consider what all this implies about future chip Now, consider what all this implies about future chip performance, given a 100 W maximum power level…performance, given a 100 W maximum power level…– Let Let max raw performance = 100 W / (½max raw performance = 100 W / (½CVCV22 gate energy) gate energy)

CMOS Raw Performance - "Optimistic" Scenario

1.00E+17

1.00E+18

1.00E+19

2004 2006 2008 2010 2012 2014 2016 2018 2020

Year

Dev

ice-

op

s/se

con

d p

er 1

00W

ch

ip

CMOS

Not much life left for standard CMOS…Not much life left for standard CMOS…

e.g., 67 million devices actively switching @ 3 GHz

Now, even if the leakage problem were solved, the ~100 kT limit for reliable switching is only another factor of 70 beyond this point!

e.g. 825 million devices actively switching @ 4 GHz, ~7,000 kT dissip. per device-op

Reversible ComputingReversible Computing

Motivation & Basic ConceptsMotivation & Basic Concepts

Landauer’s (1961) principle:Landauer’s (1961) principle: The minimum energy cost of oblivious bit erasureThe minimum energy cost of oblivious bit erasure

…

Npossibledistinct

states

Npossibledistinct

states

……

2Npossibledistinctstates

Unitary(one-to-one)evolution

Before bit erasure: After bit erasure:

Increase in entropy: ∆S = log 2 = k ln 2. Energy dissipated to heat: T∆S = kT ln 2

0s0

0sN−1

…

1s′0

1s′N−1

…

…

0t0

0tN−1

0tN

0t2N−1

…

(Was hinted at byvon Neumann ’49)

Non-oblivious “erasure” (by Non-oblivious “erasure” (by decomputingdecomputing known known bits) avoids the von Neumann–Landauer bound bits) avoids the von Neumann–Landauer bound

…

Npossibledistinct

states

Npossibledistinct

states

……

Npossibledistinctstates

Unitary(one-to-one)evolution

Before decomputing B: After decomputing B:

Increase in entropy: ∆S → 0. Energy dissipated to heat: T∆S → 0

0s0

0sN−1

…

1s′0

1s′N−1

…

…

0t0

0tN−1

0t′0

0t′N−1

…

0

0

1

1

Npossibledistinctstates

0

0

1

1

A B

A B

A B

A B A B

A B

A B

A B

Reversible ComputingReversible Computing• A A reversiblereversible digital logic operation is: digital logic operation is:

– Any operation that performs an invertible (one-to-one) Any operation that performs an invertible (one-to-one) transformation of the device’s local digital state space.transformation of the device’s local digital state space.

• Or at least, of that Or at least, of that subset subset of states that are of states that are actually used actually used in a design.in a design.

• Landauer’s principle Landauer’s principle onlyonly limits the energy dissipation of limits the energy dissipation of ordinary ordinary irreversibleirreversible (many-to-one) logic operations. (many-to-one) logic operations.– Reversible logic operations can dissipate much less energy, Reversible logic operations can dissipate much less energy,

• Since they can be implemented in a thermodynamically reversible way.Since they can be implemented in a thermodynamically reversible way.

• In 1973, Charles Bennett (IBM Research) showed how In 1973, Charles Bennett (IBM Research) showed how any desired computation can in fact be performed using any desired computation can in fact be performed using only only reversible operations (with basically no bit erasure).reversible operations (with basically no bit erasure).– This opened up the possibility of a vastly more energy-efficient This opened up the possibility of a vastly more energy-efficient

alternative paradigm for digital computation.alternative paradigm for digital computation.• After 30 years of (sporadic) research, this idea is finally After 30 years of (sporadic) research, this idea is finally

approaching the realm of practical implementability…approaching the realm of practical implementability…– Making it happen is the goal of the RevComp project at UF.Making it happen is the goal of the RevComp project at UF.

Requirements for Reversible vs. Requirements for Reversible vs. Quantum ComputingQuantum Computing

Property of Property of Computing Computing MechanismMechanism Approximate MeaningApproximate Meaning

Required for Required for Quantum Computing?Quantum Computing?

Required for Required for Reversible Reversible

Computing?Computing?

(Treated As)(Treated As)UnitaryUnitary

System’s full invertible System’s full invertible quantum evolution, w. all quantum evolution, w. all phase information, is phase information, is modeled & trackedmodeled & tracked

Yes, device & system Yes, device & system evolution must be evolution must be modeled as ~unitary, modeled as ~unitary, within thresholdwithin threshold

No, only reversible No, only reversible evolution of classical evolution of classical state variables must be state variables must be modeled & trackedmodeled & tracked

CoherentCoherentPure quantum statesPure quantum statesdon’t decohere (for us) don’t decohere (for us) into statistical mixturesinto statistical mixtures

Yes, must maintain full Yes, must maintain full global coherence, global coherence, locally within thresholdlocally within threshold

No, only maintain No, only maintain stability of local pointer stability of local pointer states & transitionsstates & transitions

AdiabaticAdiabaticNo heat flow in/out of No heat flow in/out of computational subsystemcomputational subsystem

Yes, must be above a Yes, must be above a certain thresholdcertain threshold

Yes, adiabaticity as Yes, adiabaticity as high as possiblehigh as possible

Isentropic / Isentropic / Thermodynamically Thermodynamically

ReversibleReversible

No new entropy generated No new entropy generated by mechanismby mechanism

Yes, must be above a Yes, must be above a certain thresholdcertain threshold

Yes, isentropicity as Yes, isentropicity as high as possiblehigh as possible

Time-Independent Time-Independent Hamiltonian,Hamiltonian,

Self-ControlledSelf-Controlled

Closed system, evolves Closed system, evolves autonomously w/o autonomously w/o external controlexternal control

No, transitions can be No, transitions can be externally timed & externally timed & controlledcontrolled

Yes, if we care about Yes, if we care about energy dissipation in energy dissipation in the driving systemthe driving system

BallisticBallisticSystem evolves w. net System evolves w. net forward momentumforward momentum

No, transitions can be No, transitions can be externally drivenexternally driven

Yes, if we care about Yes, if we care about performanceperformance

Some Doubts and Their AnswersSome Doubts and Their AnswersSome Claims Against Reversible ComputingSome Claims Against Reversible Computing Eventual Resolution of ClaimEventual Resolution of Claim

John von Neumann, 1949 – Offhandedly claims during a lecture that computing John von Neumann, 1949 – Offhandedly claims during a lecture that computing requires requires kTkT ln 2 dissipation per “elementary act of decision” (bit-operation). ln 2 dissipation per “elementary act of decision” (bit-operation).

No proof provided. Twelve years later, Rolf Landauer of IBM tries valiantly to No proof provided. Twelve years later, Rolf Landauer of IBM tries valiantly to prove it, but succeeds only for logically irreversible operations.prove it, but succeeds only for logically irreversible operations.

Rolf Landauer, 1961 – Proposes that the logically irreversible operations which Rolf Landauer, 1961 – Proposes that the logically irreversible operations which necessarily cause dissipation are unavoidable.necessarily cause dissipation are unavoidable.

Landauer’s argument for unavoidability of logically irreversible operations was Landauer’s argument for unavoidability of logically irreversible operations was conclusively refuted by Bennett’s 1973 paper.conclusively refuted by Bennett’s 1973 paper.

Bennett’s 1973 construction is criticized for using too much memory.Bennett’s 1973 construction is criticized for using too much memory. Bennett devises a more space-efficient version of the algorithm in 1989.Bennett devises a more space-efficient version of the algorithm in 1989.

Bennett’s models criticized by various parties for depending on random Brownian Bennett’s models criticized by various parties for depending on random Brownian motion, and not making steady forward progress.motion, and not making steady forward progress.

Fredkin and Toffoli at MIT, 1980, provide ballistic “billiard ball” model of Fredkin and Toffoli at MIT, 1980, provide ballistic “billiard ball” model of reversible computing that makes steady progress.reversible computing that makes steady progress.

Various parties note that Fredkin’s original classical-mechanical billiard-ball model Various parties note that Fredkin’s original classical-mechanical billiard-ball model is chaotically unstable.is chaotically unstable.

Zurek, 1984, shows that quantum models can avoid the chaotic instabilities. Zurek, 1984, shows that quantum models can avoid the chaotic instabilities. (Though there are workable classical ways to fix the problem also.)(Though there are workable classical ways to fix the problem also.)

Various parties propose that classical reversible logic principles won’t work at the Various parties propose that classical reversible logic principles won’t work at the nanoscale, for unspecified or vaguely-stated reasons.nanoscale, for unspecified or vaguely-stated reasons.

Drexler, 1980’s, designs various mechanical nanoscale reversible logics and Drexler, 1980’s, designs various mechanical nanoscale reversible logics and carefully analyzes their energy dissipation.carefully analyzes their energy dissipation.

Carver Mead, CalTech, 1980 – Attempts to show that the Carver Mead, CalTech, 1980 – Attempts to show that the kTkT bound is unavoidable bound is unavoidable in electronic devices, via a collection of counter-examples.in electronic devices, via a collection of counter-examples.

No general proof provided. Later he asked Feynman about the issue; in 1985 No general proof provided. Later he asked Feynman about the issue; in 1985 Feynman provided a quantum-mechanical model of reversible computing.Feynman provided a quantum-mechanical model of reversible computing.

Various parties point out that Feynman’s model only supports serial computation.Various parties point out that Feynman’s model only supports serial computation. Margolus at MIT, 1990, demonstrates a parallel quantum model of reversible Margolus at MIT, 1990, demonstrates a parallel quantum model of reversible computing—but only with 1 dimension of parallelism. computing—but only with 1 dimension of parallelism.

People question whether the various theoretical models can be validated with a People question whether the various theoretical models can be validated with a working electronic implementation.working electronic implementation.

Seitz and colleagues at CalTech, 1985, demonstrate working energy recovery Seitz and colleagues at CalTech, 1985, demonstrate working energy recovery circuits using adiabatic switching principles.circuits using adiabatic switching principles.

Seitz, 1985—Has some working circuits, unsure if arbitrary logic is possible.Seitz, 1985—Has some working circuits, unsure if arbitrary logic is possible. Koller & Athas, Hall, and Merkle (1992) separately devise general reversible Koller & Athas, Hall, and Merkle (1992) separately devise general reversible combinational logics.combinational logics.

Koller & Athas, 1992 – Conjecture reversible Koller & Athas, 1992 – Conjecture reversible sequential sequential feedback logic impossible.feedback logic impossible. Younis & Knight @MIT do reversible sequential, pipelineable circuits in 1993-94.Younis & Knight @MIT do reversible sequential, pipelineable circuits in 1993-94.

Some computer architects wonder whether the constraint of reversible logic leads to Some computer architects wonder whether the constraint of reversible logic leads to unreasonable design convolutions.unreasonable design convolutions.

Vieri, Frank and coworkers at MIT, 1995-99, refute these qualms by demonstrating Vieri, Frank and coworkers at MIT, 1995-99, refute these qualms by demonstrating straightforward designs for fully-reversible, scalable gate arrays, straightforward designs for fully-reversible, scalable gate arrays, microprocessors, and instruction sets.microprocessors, and instruction sets.

Some computer science theorists suggest that the algorithmic overheads of Some computer science theorists suggest that the algorithmic overheads of reversible computing might outweigh their practical benefits.reversible computing might outweigh their practical benefits.

Frank, 1997-2003, publishes a variety of rigorous theoretical analysis refuting these Frank, 1997-2003, publishes a variety of rigorous theoretical analysis refuting these claims for the most general classes of applications.claims for the most general classes of applications.

Various parties point out that high-quality power supplies for adiabatic circuits seem Various parties point out that high-quality power supplies for adiabatic circuits seem difficult to build electronically.difficult to build electronically.

Frank, 2000, suggests microscale/nanoscale electro mechanical resonators for high-Frank, 2000, suggests microscale/nanoscale electro mechanical resonators for high-quality energy recovery with desired waveform shape and frequency.quality energy recovery with desired waveform shape and frequency.

Frank, 2002—Briefly wonders if synchronization of parallel reversible computation Frank, 2002—Briefly wonders if synchronization of parallel reversible computation in 3 dimensions (not covered by Margolus) might not be possible.in 3 dimensions (not covered by Margolus) might not be possible.

Later that year, Frank devises a simple mechanical model showing that parallel Later that year, Frank devises a simple mechanical model showing that parallel reversible systems can indeed be synchronized locally in 3 dimensions.reversible systems can indeed be synchronized locally in 3 dimensions.

Adiabatic CircuitsAdiabatic Circuits• Reversible logic can be implemented today using fairly Reversible logic can be implemented today using fairly

ordinary voltage-coded CMOS VLSI circuits.ordinary voltage-coded CMOS VLSI circuits.– With a few changes to the logic-gate/circuit architecture.With a few changes to the logic-gate/circuit architecture.

• We avoid dissipating most of the circuit node energy We avoid dissipating most of the circuit node energy when switching, by transferring charges in a nearly when switching, by transferring charges in a nearly adiabaticadiabatic (literally, “without flow of heat”) fashion. (literally, “without flow of heat”) fashion.– I.e.I.e., asymptotically thermodynamically reversible., asymptotically thermodynamically reversible.

• In the limit, as various low-level technology parameters are scaled.In the limit, as various low-level technology parameters are scaled.

• There are many designs for purported “adiabatic” circuits There are many designs for purported “adiabatic” circuits in the literature, but most of them contain fatal flaws and in the literature, but most of them contain fatal flaws and are not truly adiabatic.are not truly adiabatic.– Many past designers are unaware of (or accidentally failed to Many past designers are unaware of (or accidentally failed to

meet) all the requirements for true thermodynamic reversibility.meet) all the requirements for true thermodynamic reversibility.

Reversible and/or Adiabatic VLSI Chips Reversible and/or Adiabatic VLSI Chips Designed @ MIT, 1996-1999Designed @ MIT, 1996-1999

By Frank and other then-students in the MIT Reversible Computing group,under CS/AI lab members Tom Knight and Norm Margolus.

Transition TablesTransition Tables• Recall how a Recall how a truth tabletruth table for Boolean for Boolean

logic lists all possible input logic lists all possible input combinations on the left, and the combinations on the left, and the corresponding output(s) on the right.corresponding output(s) on the right.

• A A transition tabletransition table is a similar device designed to allow us to easily distinguish is a similar device designed to allow us to easily distinguish reversible operations from irreversible ones.reversible operations from irreversible ones.

– We list We list eacheach combination of combination of all local bitsall local bits once in both “before” and “after” columns.once in both “before” and “after” columns.

• Corresponding to just before the operation begins, Corresponding to just before the operation begins, and just after it is completely finished.and just after it is completely finished.

– We draw an arrow from each We draw an arrow from each beforebefore state state to the particular to the particular afterafter state that it transforms to. state that it transforms to.

• Red if the transition is dissipative, green otherwise.Red if the transition is dissipative, green otherwise.– Must obey the following rule: Only one of the Must obey the following rule: Only one of the

arrows going arrows going into into any given any given afterafter state may be green. state may be green.• It is convenient to order the It is convenient to order the afterafter column so that column so that

all the green arrows go straight horizontally.all the green arrows go straight horizontally.– It may be that only a It may be that only a subsetsubset of the input and/or output of the input and/or output

states arise in the context of a given circuit design.states arise in the context of a given circuit design.• We may “fade away” the particular states and We may “fade away” the particular states and

transitions which never arise.transitions which never arise.– An operation is An operation is always reversiblealways reversible iff there are no iff there are no

red arrows in the table.red arrows in the table.• This means the operation is one-to-one.This means the operation is one-to-one.

– An operation is An operation is reversible in contextreversible in context iff there are iff there areno no un-faded un-faded red arrows in the resulting table.red arrows in the resulting table.

• I.e.I.e., the operation is 1-1 on , the operation is 1-1 on the states that arisethe states that arise..• We will find these tables to be very useful.We will find these tables to be very useful.

AA BB QQ

00 00 00

00 11 00

11 00 00

11 11 11

AND

BeforeBefore AfterAfterinin outout inin outout

00 00 00 00

00 11 00 11

11 00 11 00

11 11 11 11

Standard inverter(present-day “NOT gate”)operation.

Function: out := ¬ in

Usually irreversible.Only reversible in the context that itsinput never changes!

BeforeBefore AfterAfterCC DD CC DD

00 00 00 00

00 11 00 11

11 00 11 11

11 11 11 00

cNOT (controlled-NOT) “gate” (operation)

Function: D = C

Always reversible.

Bistable Potential-Energy WellsBistable Potential-Energy Wells

• Consider any system having an (adjustable) potential Consider any system having an (adjustable) potential energy surface (PES) in its configuration space.energy surface (PES) in its configuration space.– The PES should have at least two local minima (or The PES should have at least two local minima (or wellswells))– Therefore the system is Therefore the system is bistablebistable

• It has two stable (or at least metastable) configurations It has two stable (or at least metastable) configurations – Located at well bottomsLocated at well bottoms

• The two stable states form a natural bit.The two stable states form a natural bit.– One state can represent 0, the other 1.One state can represent 0, the other 1.

• This picture can also be easily generalized toThis picture can also be easily generalized tolarger numbers of stable states.larger numbers of stable states.

• Consider now the PES havingConsider now the PES havingtwo adjustable parameters:two adjustable parameters:– (1) “Height” (energy) of the potential energy (1) “Height” (energy) of the potential energy

barrier between wells, relative to well bottomsbarrier between wells, relative to well bottoms– (2) Relative height of the left and right(2) Relative height of the left and right

states in the well (call this “bias”)states in the well (call this “bias”)

0 1

(Landauer ’61)A Technology-Independent Model of Digital Devices

Generalizedconfiguration

coordinate

Pot

enti

alen

ergy

Possible Parameter SettingsPossible Parameter Settings• In the following slides, we will distinguish In the following slides, we will distinguish

six qualitatively different settings of the six qualitatively different settings of the well parameters, as shown below… well parameters, as shown below…

Direction of Bias Force

BarrierHeight

Raised

Lowered

Left RightNeutral

One Mechanical ImplementationOne Mechanical Implementation

Boxspring

Rightwardbias

Leftwardbias

Barrier up

Barrier down

Barrierwedge

Stateknob

Fixedsleeve

bearingBias rod Gat

e ro

d

MOSFET ImplementationMOSFET Implementation• The logical state is in the location of a charge packet The logical state is in the location of a charge packet

(excess of electrons) on either side terminal of a FET.(excess of electrons) on either side terminal of a FET.– The charge packet might even consist of just a single excess The charge packet might even consist of just a single excess

electron in a sufficiently small (nanoscale) logic node.electron in a sufficiently small (nanoscale) logic node.• The potential energy barrier is provided by the built-in The potential energy barrier is provided by the built-in

voltage across the PN junctions in the FET.voltage across the PN junctions in the FET.– The barrier height is lowered when the device is turned on The barrier height is lowered when the device is turned on

by adjusting the voltage on the gate electrode.by adjusting the voltage on the gate electrode.• Bias forces can be provided by (Bias forces can be provided by (e.g.e.g.) capacitive ) capacitive

coupling to nearby electrodes.coupling to nearby electrodes.

n p n

e e e

Possible Well TransitionsPossible Well Transitions• Catalog of all the possible transitions in Catalog of all the possible transitions in

the bistable wells, the bistable wells, adiabaticadiabatic & & notnot......– We can characterize a wide variety of digitalWe can characterize a wide variety of digital

logic and memory styles in terms of how theirlogic and memory styles in terms of how theiroperation corresponds to subgraphs of this diagram.operation corresponds to subgraphs of this diagram.


BarrierHeight

0 0 0

111

10 N

(Ignoring superposition states.)

leak

leak

“1”states

“0”states

∆E∆E

k ln 2

Logic & Memory StylesLogic & Memory Styles

• Irreversible styles:Irreversible styles:– Input-barrierInput-barrier, , fixed-biasfixed-bias logic. logic.

• E.g.E.g. standard static CMOS inverters & combinational gates. standard static CMOS inverters & combinational gates.– Input-bias, clocked-barrierInput-bias, clocked-barrier latching. latching.

• Standard static CMOS latches, dynamic RAM cells, Standard static CMOS latches, dynamic RAM cells, etcetc..• Reversible styles:Reversible styles:

– Type 1: Type 1: Input-bias, clocked-barrier Input-bias, clocked-barrier latching.latching.– Type 2: Type 2: Input-barrier, clocked-bias Input-barrier, clocked-bias logic.logic.– Type 3: Type 3: Input-barrier, clocked-biasInput-barrier, clocked-bias latching logic. latching logic.

• All of these are available in a very wide variety of All of these are available in a very wide variety of different physical instantiations of the bistable well.different physical instantiations of the bistable well.– E.g.E.g., CMOS, superconducting, quantum-dot, Y-branch , CMOS, superconducting, quantum-dot, Y-branch

switches, mechanical implementations, switches, mechanical implementations, etc.etc.

All describable within the potential-well paradigm!

Ordinary Ordinary IrreversibleIrreversible Logics Logics• Principle of operation:Principle of operation: Lower a barrier, or not, Lower a barrier, or not,

based on input. Series/parallel combinations ofbased on input. Series/parallel combinations of barriers do logic. Major barriers do logic. Major dissipation in at least one of dissipation in at least one of

the possible transitions.the possible transitions.

0

1

0

Example: Ordinary CMOS logics

Input changes,barrier

lowered

Outputirreversiblychanged to 0

• Can amplify input signals.

Irreversible SET/CLR operationsIrreversible SET/CLR operations• Irreversible SET:Irreversible SET: Turn on a pFET connecting node Turn on a pFET connecting node BB to a high to a high

voltage source. voltage source.

Voltage Voltage color scheme: color scheme:

LowLow / / HighHigh

• Irreversible CLR:Irreversible CLR: Turn on an nFET connecting node Turn on an nFET connecting node BB to a to a low voltage source. low voltage source.

½CV2

½CV2

BBbeforebefore

BBafterafter

00 00

11 11

BBbeforebefore

BBafterafter

00 00

11 11

B B

B

B B

B

SET operation

CLR operation

Conventional Logic is IrreversibleConventional Logic is Irreversible

• Here’s what all of today’s logic gates (including NOT) Here’s what all of today’s logic gates (including NOT) do do continuallycontinually, , i.e.i.e., every time their input changes:, every time their input changes:– They They overwriteoverwrite previous output with a function of their input. previous output with a function of their input.– Performs many-to-one transformation of local digital state!Performs many-to-one transformation of local digital state! required to dissipate required to dissipate ≳≳kkT T on avg., by Landauer principleon avg., by Landauer principle– Incurs Incurs ½½CVCV22 energy dissipation when the output changes. energy dissipation when the output changes.

Just beforetransition:

Aftertransition:

in out in out0 00 1 0 11 0 1 01 1

in out

Example:

Static CMOS Inverter:

Inverter transition table:

Even a simple NOT gate, as it’s traditionally implemented!

Example: Standard CMOS InverterExample: Standard CMOS InverterPower (Vdd)

Ground (0V)

In Out

Inputgoeshigh

Power (Vdd)

Ground (0V)

In Out= 0 = 1 = 1

= 0

Barrier btwn.Out and Groundlowered, charge“falls” to lower

energy level

Out

Barrierlowered

Inputgoeslow

GNDVdd

Charge falls out

Out

Barrierraised

GNDVdd

Charge

falls in

Barrierlowered

Simplified← picture →

of PES

off

on

on

off

Voltage color scheme: Voltage color scheme: LowLow / / HighHigh

Spacetime Logic Network DiagramsSpacetime Logic Network Diagrams• In this general class of diagrams (popular in reversible & quantum logic), In this general class of diagrams (popular in reversible & quantum logic),

– Time is plotted in one direction, often leftTime is plotted in one direction, often left→→right, right, – Horizontal lines denote locations (nodes, bits of state).Horizontal lines denote locations (nodes, bits of state).– Operations (potential change events) are denoted by icons on Operations (potential change events) are denoted by icons on

and/or connections between bit-lines.and/or connections between bit-lines.• Please keep in mind: These diagrams Please keep in mind: These diagrams do notdo not directly depict the spatial directly depict the spatial

structure of how a physical circuit is wired!structure of how a physical circuit is wired!– E.g.E.g., a long horizontal line denotes the evolution of a , a long horizontal line denotes the evolution of a localized nodelocalized node in a in a

physical circuit over a long period of time, physical circuit over a long period of time, not not a long, spatially extended wire.a long, spatially extended wire.– A vertical connection between lines or an icon on a line (often called a “gate”) A vertical connection between lines or an icon on a line (often called a “gate”)

denotes a momentary interaction denotes a momentary interaction eventevent, , not not a perpetual physical link, or a a perpetual physical link, or a physical object.physical object.

I

O

Time

Loc

atio

n

This arrow denotes that some external event causes the value of node I to change at this time.

The change in I is propagated so as tocause node O to change a moment later.

An icon denotes that Opotentially changes (whetherspontaneously or under external control) at this time.

Inverter action in spacetime diagramInverter action in spacetime diagram• Note:Note: This notation makes it explicit that an ordinary This notation makes it explicit that an ordinary

inverter’s inverter’s realreal semantics is that it should carry out a semantics is that it should carry out a logically logically irreversibleirreversible transformation of its output node. transformation of its output node.

In

Out

Time

Loc

atio

n

Some outsideinfluence causesIn to possiblychange here

The “×” icon denotesthat the old valueof Out gets obliv-iously overwritten

This (standard) icon denotesthat In’s value gets copied (with gain & delay) & invertedto produce the new Out.





BarrierHeight

0 0 0

111

10 N


leak

leak

“1”states

“0”states

∆E∆E

k ln 2

Ordinary Ordinary IrreversibleIrreversible Memory Memory• (1) Lower a barrier, obliviously erasing stored (1) Lower a barrier, obliviously erasing stored

information.information. (2) Apply an input bias.(2) Apply an input bias. (3) Raise (3) Raise the barrier to latch the new informationthe barrier to latch the new informationinto place.into place. (4) Remove input(4) Remove inputbias.bias.

0 0

11

10 N

Examples:ordinary

DRAM cell,rod logicregister

Dissipationhere can be

made as low as kT ln 2

Input“0”

Input“1”

Barrier up

Barrierup

Retractinput

Retractinput

(1)

(2) (2)

(3)

(3)

(4)

(4)

(1) and (2) can also be in theopposite order

Example: NMOS latch / DRAM cellExample: NMOS latch / DRAM cell• Sequence corresponds exactly to general Sequence corresponds exactly to general

picture illustrated on previous slide.picture illustrated on previous slide.

(1) Oblivious

erasure

(2) Apply inputbias

(3)Raisebarrier

I M

I M

I M

I M

I M

I M

I M

I M

I M

(4) Remove

inputbias

Could also do these in the other order also

(& backto start)

off

off

on

on

on off

off off

off

Voltage color scheme: Voltage color scheme: LowLow / / MediumMedium / / HighHigh

Irreversible latch in spacetime diagramIrreversible latch in spacetime diagram• Again, this notation makes it clear that irreversible Again, this notation makes it clear that irreversible

behavior is occurring.behavior is occurring.

I

M

Time

Loc

atio

n

Outsideinfluence causesI to possiblychange here

The “×” & arrow denotes that the old value of M

gets obliviously erased or overwritten by I when

barrier islowered

Later arrow denotes thatI gets reflected (without gain) inlocation M with a small delay

I may changeagain later withoutnecessarilyaffecting value of M

Barrier is raised shortlyafterwards (end of shaded area)

Conventional Conventional vs.vs. Adiabatic Charging Adiabatic Charging

• Conventional charging:Conventional charging:– Constant voltage sourceConstant voltage source

– Energy dissipated:Energy dissipated:

• Ideal adiabatic charging:Ideal adiabatic charging:– Constant current sourceConstant current source

– Energy dissipated:Energy dissipated:

V C

Q=CV

R CI

Q=CV

t

RCCV

t

RQRtIE 2

22

diss 2

21

diss CVE

Note: Adiabatic beats conventional by advantage factor A = t/2RC.

For charging a capacitive load C through a voltage swing V

Adiabatic Switching with MOSFETsAdiabatic Switching with MOSFETs• Use a voltage ramp to approximate Use a voltage ramp to approximate

an ideal current source.an ideal current source.• Switch Switch conditionallyconditionally,,

if MOSFET gate voltage if MOSFET gate voltage VVgg > > VV++VVTT during ramp. during ramp.

• Can discharge the load later using a similar ramp.Can discharge the load later using a similar ramp.– Either through the same path, or a different path.Either through the same path, or a different path.

tt ≫≫ RCRC

tt ≪≪ RCRC

t

RCCVE 2

diss

221

diss CVE

Exact formula:

given speed fraction s : RC/t

2/1diss 11 CVessE s

Athas ’96, Tzartzanis ‘98

Requirements for True Adiabatic LogicRequirements for True Adiabatic Logicin Voltage-coded, FET-based circuitsin Voltage-coded, FET-based circuits

• Avoid passing current through diodes.Avoid passing current through diodes.– Crossing the “diode drop” leads to irreducible dissipation.Crossing the “diode drop” leads to irreducible dissipation.

• Follow a “dry switching” discipline (in the relay lingo):Follow a “dry switching” discipline (in the relay lingo):– Never turn on a transistor when Never turn on a transistor when VVDSDS ≠ 0.≠ 0.– Never turn Never turn offoff a transistor when a transistor when IIDSDS ≠ 0. ≠ 0.

• Together these rules imply:Together these rules imply:– The logic design must be logically reversibleThe logic design must be logically reversible

• There is no way to erase information under these rules!There is no way to erase information under these rules!– Transitions must be driven by a quasi-trapezoidal waveformTransitions must be driven by a quasi-trapezoidal waveform

• It must be generated resonantly, with high It must be generated resonantly, with high QQ

• Of course, leakage power must also be kept manageable.Of course, leakage power must also be kept manageable.– Because of this, the optimal design point will Because of this, the optimal design point will notnot necessarily necessarily

use the smallest devices that can ever be manufactured!use the smallest devices that can ever be manufactured!• Since the smallest devices may have insoluble problems with leakage.Since the smallest devices may have insoluble problems with leakage.

Importantbut oftenneglected!





BarrierHeight

0 0 0

111

10 N


leak

leak

“1”states

“0”states

∆E∆E

k ln 2

Erasing Digital Erasing Digital EntropyEntropy • Note that if the information in a bit-system is Note that if the information in a bit-system is alreadyalready entropy, entropy,

– Then erasing it just Then erasing it just movesmoves this entropy to the surroundings. this entropy to the surroundings.– This can be done with a thermodynamically reversible process, and does This can be done with a thermodynamically reversible process, and does

notnot necessarily necessarily increaseincrease total entropy! total entropy!• However, if/when we take a bit that is known, and irrevocably However, if/when we take a bit that is known, and irrevocably

commit ourselves to thereafter treating it as if it were commit ourselves to thereafter treating it as if it were unknownunknown, , – thatthat is the true irreversible step, is the true irreversible step, – and and thatthat is when the entropy is is when the entropy is

effectively generated!!effectively generated!!

0 0

0 N

1

1

? This state contains 1 bitof physical entropy, but ina stable, “digital” form

In these 3 states, there is no entropy in the digital state; it has all been pushed out into the environment.

This state contains 1 bitof decomputable information, in a stable, “digital” form

Note: This transformation is reversible!!

Reversible Set (rSET) & Clear (rCLR)Reversible Set (rSET) & Clear (rCLR)• rSET operation semantics: rSET operation semantics: Given assuranceGiven assurance that a bit is initially 0, that a bit is initially 0,

unconditionally change it to 1.unconditionally change it to 1.– To implement: Traverse the adiabat (reversible trajectory) shown below.To implement: Traverse the adiabat (reversible trajectory) shown below.

• Reverse this path to perform rCLR.Reverse this path to perform rCLR.


BarrierHeight

0 0

11

10 N

“1”states

“0”states

(1)

(2)

(3) (4)

(5)

(6)

Get workout

Put workback in

Taking rSET & rCLR out of contextTaking rSET & rCLR out of context• What happens if we attempt to perform rSET on a bit that is What happens if we attempt to perform rSET on a bit that is alreadyalready a 1? a 1?

– It still ends up with the right value (1), but…It still ends up with the right value (1), but…– Irreversible dissipation occurs in step 2 (when barrier is lowered), as shown below.Irreversible dissipation occurs in step 2 (when barrier is lowered), as shown below.

• Similarly if we try to rCLR a 0.Similarly if we try to rCLR a 0.


BarrierHeight

11

10 N

“1”states

“0”states

1 (1)

(2)

(3) (4)

(5)

(6)(takes

work toraise 1)

(dissipatesit as heat)

(takeswork toraise 1)

rSET/rCLR transition tablesrSET/rCLR transition tables• Note that these tables are Note that these tables are notnot reversible according to the strict reversible according to the strict

traditional definition…traditional definition…– Since they don’t represent a 1-1 transformation of Since they don’t represent a 1-1 transformation of allall possible input possible input

states.states.• HoweverHowever, if we , if we restrictrestrict our use of these operations so as to our use of these operations so as to

always always avoidavoid the input states that actually result in dissipation, the input states that actually result in dissipation,– ThenThen, we obtain a 1-1 transformation of , we obtain a 1-1 transformation of the subset of the input states the subset of the input states

that are actually usedthat are actually used,,– And And thatthat is the correct statement of the true logical requirement for is the correct statement of the true logical requirement for

avoiding Landauer’s principle!avoiding Landauer’s principle!

Before Before rSETrSET

AfterAfterrSETrSET

00 11

11

Before Before rCLRrCLR

AfterAfterrCLRrCLR

00

11 00

Type 1:Type 1: Input-Bias Clocked-Barrier Input-Bias Clocked-Barrier Reversible Latching (& Logic)Reversible Latching (& Logic)

• Cycle of operation:Cycle of operation:– (1)(1) Data input applies biasData input applies bias

• Add forces to do majority logicAdd forces to do majority logic– (2) Clock signal raises barrier(2) Clock signal raises barrier– (3) Data input bias removed(3) Data input bias removed

0 0

11

10 N

(Can amplify/restore input signalin the barrier-raising step.)

Can reset latch reversibly (4) given copy ofcontents.

Examples: AdiabaticQCA, SCRL latch, Rod logic latch, PQ logic,Buckled logic, Helical logic

(1) (1)

(2)

(2)(3)

(3)

(4)(4)

(4) (4)

(4)

(4)

Type 1 Example: Adiabatic Type 1 Example: Adiabatic NMOS latch / DRAM cellNMOS latch / DRAM cell

• Same as irrev. latch, just skip the erasure step!Same as irrev. latch, just skip the erasure step!

(1) Apply inputbias

(2)Raisebarrier

I M

I M

I M

I M

I M

I M

I M

(3) Remove

inputbias

(Reverse stepsto reversibly

unlatch M)

on

on

on off

off off

off


Can similarly use a CMOS transmissiongate (nFET/pFET pair) to latch a full-swing signal if necessary.

A Simple Reversible CMOS LatchA Simple Reversible CMOS Latch• Uses a single standard CMOS Uses a single standard CMOS transmission gatetransmission gate (T-gate). (T-gate).• Sequence of operation:Sequence of operation:

(0) input level initially tied to latch ‘contents’ (output);(0) input level initially tied to latch ‘contents’ (output);(1) input changes gradually (1) input changes gradually output follows closely; output follows closely; (2) latch closes, charge is stored dynamically (node (2) latch closes, charge is stored dynamically (node

floats); floats); (3) afterwards, the input signal can be removed.(3) afterwards, the input signal can be removed.

P

P

in out

Before Input Inputinput: arrived: removed:in out in out in out0 0 0 0 0 0

1 1 0 1

(0) (1) (2) (3)

• Later, we can reversibly “unlatch” the data with an exactly time-reversed sequence of steps.“Reversible latch”

Reversible latch in spacetime diagramReversible latch in spacetime diagram

I

M

Time

Loc

atio

n

Outsideinfluence causesI to possiblychange here

Arrow to dotted line denotes that changeto I is reversibly carried through (without gain) to location M at this time (energytransferred into I is also fanned out to M)

I may be restored toneutral again later without necessarilyaffecting value of M

Barrier is raised some timeafterwards (end of shaded area)

Dotted lines denote that thesenodes contain no information

at these times (they are ina predetermined state)

Barrier is lowered some timein here (start of shaded area)

I

M

Unlatchingsequence:

Note this operation is reversible only if I and M match up exactly when they are first connected together!

Time

Simplified Version of DiagramSimplified Version of Diagram• Suppose the signal on the input node Suppose the signal on the input node II was produced was produced

as a temporary copy of some origin node as a temporary copy of some origin node OO..– We will see how to implement this reversibly later.We will see how to implement this reversibly later.

• Then for simplicity of our diagrams, we may wish to Then for simplicity of our diagrams, we may wish to omit explicit representation of the intermediate node omit explicit representation of the intermediate node II..– However, we must keep in mind that there is then a small However, we must keep in mind that there is then a small

additional space usage not explicitly shown in the diagram.additional space usage not explicitly shown in the diagram.

O

M

Time

I

O

M

Time

“Reversible copy”

Type 2: Type 2: Input-Barrier, Clocked-Bias Input-Barrier, Clocked-Bias Reversible Retractile LogicReversible Retractile Logic

• Cycle of operation:Cycle of operation:– (1) Inputs raise or lower barriers(1) Inputs raise or lower barriers

• Do logic w. series/parallel barriersDo logic w. series/parallel barriers– (2) Clock applies bias force, which changes state, or not(2) Clock applies bias force, which changes state, or not

0 0 0

10 N

• Barrier signal is amplified! Gain, restoring logic, fan-out.• Must reset output prior to changing input.• Combinational logic only!

(1) Input barrier height

(2) Clocked bias force applied

Examples:Hall’s logic,SCRL gates,Rod logic interlocks

Type 2 example: Adiabatic CMOS Type 2 example: Adiabatic CMOS “buffer” (really, a cSET/cCLR gate)“buffer” (really, a cSET/cCLR gate)

• Controlled-SET / controlled-CLEAR.Controlled-SET / controlled-CLEAR.• Structure: Essentially just a pair of CMOS transmission gates Structure: Essentially just a pair of CMOS transmission gates

– 2 transistors each, an nFET and a pFET in parallel2 transistors each, an nFET and a pFET in parallel• Using dual-rail signaling, we can reversibly set or clear a bit on an Using dual-rail signaling, we can reversibly set or clear a bit on an

unoccupied logic node (pair of voltage nodes), conditionally on an input unoccupied logic node (pair of voltage nodes), conditionally on an input node.node.– Amplifies input signal.Amplifies input signal.– Fully restores logic levels.Fully restores logic levels.

InN

InP

DriveN

OutN

(And similarly for OutP)

InN InP

DriveN

OutNVoltage color scheme: Voltage color scheme: LowLow / / HighHigh

off InN InP

DriveN

OutN

InN InP

DriveN

OutN

InN InP

DriveN

OutN

on on

offoff

Spacetime diagram for bufferSpacetime diagram for buffer• Subscript Subscript NPNP notation denotes shorthand for dual-rail NP pair of wires. notation denotes shorthand for dual-rail NP pair of wires.

– Still denotes a single Still denotes a single logicallogical bit. bit.• Diagram emphasizes that the buffer copies Diagram emphasizes that the buffer copies InInNPNP’s value to a ’s value to a newnew location. location.

– The value simultaneously remains available in the old location.The value simultaneously remains available in the old location.• Dotted horizontal line shows that Dotted horizontal line shows that OutOutNPNP is empty prior to the operation. is empty prior to the operation.

– The absence of “The absence of “×” icon shows that the operation is reversible.×” icon shows that the operation is reversible.• Buffer icon indicates that the input signal is being amplified and restored.Buffer icon indicates that the input signal is being amplified and restored.

– Note that the input comes from Note that the input comes from InInNPNP, , notnot from previous value of from previous value of OutOutNPNP..• Downward wedges remind us the output remains dependent on the input.Downward wedges remind us the output remains dependent on the input.

– Input can’t be changed without (possibly) irreversibly destroying output.Input can’t be changed without (possibly) irreversibly destroying output.• Fortunately, the buffer’s entire operation sequence is reversible!Fortunately, the buffer’s entire operation sequence is reversible!

– So, sometime later on, we can So, sometime later on, we can unbufferunbuffer the output, the output, • and then we are free to change the input.and then we are free to change the input.InNP

OutNP

Time

InNP

OutNP

Time

Input valuecan be changedafterwards.

Restored to null.

…

Reversible Buffered LatchReversible Buffered Latch

• Uses two dual-rail T-gates.Uses two dual-rail T-gates.• Combines a buffer and latch.Combines a buffer and latch.

– Reversibly copies Reversibly copies InInNPNP to to

MemMemNPNP when operated. when operated.

InNP

DriveNP

LatchNP

IntNP

MemNP

Spacetime diagram for operation sequence:InNP

MemNP

IntNP

A

B

CNP

This is our icon for a CMOS transmission

gate (T-gate). It saysthat nodes A and B

are connected wheneverthe control signal

CNP has logic value 1.

Implements “reversible copy”:InNP

MemNP

Physical structure:

Transition Table for cSETTransition Table for cSET• It is not It is not always reversiblealways reversible,,

– Not a one-to-one transformation of Not a one-to-one transformation of allall possible possible local states, local states,

• But, it But, it isis reversible reversible in contextin context– I.e.I.e., in the context that input state 1,1 is avoided., in the context that input state 1,1 is avoided.

Before cSETBefore cSET After cSETAfter cSET

SourceSource DestinationDestination SourceSource DestinationDestination

00 00 00 00

00 11 00 11

11 00 11 11

11 11 11 00

Type 2 example: SCRL inverter (w/o latch)Type 2 example: SCRL inverter (w/o latch)• Same structure as static CMOS inverter, but used reversibly.Same structure as static CMOS inverter, but used reversibly.• Produces a fully-restored, amplified output signal.Produces a fully-restored, amplified output signal.• Inverters can be cascaded, but need latches to get feedback.Inverters can be cascaded, but need latches to get feedback.

In Out

In Out

In Out

off

off on

off

off

on

driveH

driveL

driveL

driveH

driveH

driveL

In Out

on

off

driveH

driveL

In Out

off

on

driveL

driveH


SCRL Inverter Transition TableSCRL Inverter Transition TableBefore Before

SCRL-InvSCRL-InvAfter After

SCRL-InvSCRL-Inv

InIn OutOut InIn OutOut

00 00

00 ½½ 00 11

00 11

½ ½ 00

½ ½ ½½

½ ½ 11

11 00

11 ½½ 11 00

11 11

Before Before SCRL-InvSCRL-Inv

After After SCRL-InvSCRL-Inv

InIn OutOut InIn OutOut

00 ½½ 00 11

11 ½½ 11 00

• Reversible in context, if input is valid and output is ½ just before drivers do their thing.

• No point in even listing the table entries that don’t occur; can summarize operation below.

Spacetime Diagram for SCRL InverterSpacetime Diagram for SCRL Inverter• Note that the notation shows that Note that the notation shows that OutOut is being is being

computed from computed from InIn on a on a separate wire.separate wire. – InIn is explicitly is explicitly not not being inverted “in place.”being inverted “in place.”

• Wedge symbols show ongoing dependence.Wedge symbols show ongoing dependence.– Of course, we can always undo the op later.Of course, we can always undo the op later.

In

Out…

Example: Adiabatic NMOS OR gateExample: Adiabatic NMOS OR gate

• Together Together

OutA

B

OutA

B

OutA

B

OutA

B

OutA

B

Drive

Drive

Drive

Drive

Drive

OutA

B

OutA

B

OutA

B

OutA

B

Drive

Drive

Drive

Drive

Out = A B

• Reverse sequence decomputes Out.

• Can’t change A,B freely until then.

• With NMOS, Out is weak (orange).• Can use an SCRL inverter to restore the signal levels.

• If appropriately biased…

• Or, just use CMOS transmission gates instead (8T OR)

Type 3: Type 3: Input-Barrier, Clocked-Bias Input-Barrier, Clocked-Bias Latching LogicLatching Logic

0 0 0

1

10 N

●● Cycle of operation:Cycle of operation:1.1. Input Input conditionally lowersconditionally lowers barrier barrier

• Do logic w. series/parallel barriersDo logic w. series/parallel barriers

2.2. Clock applies bias force; conditional bit flipClock applies bias force; conditional bit flip3.3. Input removed, Input removed, raisingraising the barrier & the barrier &

locking in the state-changelocking in the state-change4.4. ClockClock

bias canbias canretractretract

Examples: Mike’s4-cycle 2-level adiabaticCMOS logic (2LAL)

(1)

(2) (2)

(2) (2)

(3)

(4)(4)

2LAL: 2-level Adiabatic Logic2LAL: 2-level Adiabatic Logic

• Use simplified T-gate symbol:Use simplified T-gate symbol:• Basic buffer element: Basic buffer element:

– cross-coupled T-gates:cross-coupled T-gates:• need 8 transistors to need 8 transistors to

buffer 1 dual-rail signalbuffer 1 dual-rail signal

• Only 4 timing signals Only 4 timing signals 0-30-3 are are

needed. Only 4 ticks per cycle:needed. Only 4 ticks per cycle: ii rises during ticks rises during ticks tt≡i≡i (mod 4) (mod 4) ii falls during ticks falls during ticks tt≡≡ii+2 (mod 4)+2 (mod 4)

TN

TP

T

:

in

out

1

0

0 1 2 3 …Tick #

0

1

2

3

A pipelined fully-adiabatic logic invented at UF (Spring 2000),implementable using ordinary CMOS transistors.

2

(implicitdual-railencoding

everywhere)

2lal.swf

Animation:

2LAL Cycle of Operation2LAL Cycle of Operation

in

in1

in=0

01

01

10

11

out1

out=0

00

00

in011

out0

Tick #0 Tick #1 Tick #2 Tick #3

A Schematic Notation for 2LALA Schematic Notation for 2LAL

≡PN

PP

PP

PN

A B BA≡P

PN

A B

tin out ≡ in

φt mod 4

PNout

in0 out5

tA

B

tin out ≡ tint-1

outtt-1

1 2 3 4 5

≡AB

A tA A

B

AB

tA

B ≡A+Bt

t

A

B

A+B

A ~A ≡ A2

A=0

A=1

~A=0

~A=12

~A

(a)

(b)

(c)

(d)

(e)

(f)

(g)

(h)

t

AA

BAB ≡

tA=1

B=1AB=1

A=1

t AB=0A=0

B=0

PN

PN

2LAL Shift Register Structure2LAL Shift Register Structure

• 1-tick delay per logic stage:1-tick delay per logic stage:

• Logic pulse timing and signal propagation:Logic pulse timing and signal propagation:

in@0

1

0

2

1

3

2

out@4

0

3

inN

inP

0 1 2 3 ... 0 1 2 3 ...

2lal.swf

Animation:

More Complex Logic FunctionsMore Complex Logic Functions• Non-inverting multi-input Boolean functions:Non-inverting multi-input Boolean functions:

• One way to do inverting functions in pipelined One way to do inverting functions in pipelined logic is to use a quad-rail logic encoding:logic is to use a quad-rail logic encoding:– To invert, justTo invert, just

swap the rails!swap the rails!• Zero-transistorZero-transistor

“inverters.”“inverters.”

A0

B0

0

A1

(AB)1

A0 B0

(AB)1

AN

AP

AN

AP

A = 0 A = 1

AND gate (plus delayed A)

OR gate

Minimum Losses w. LeakageMinimum Losses w. Leakage

S

leak

E

leakopt c

S

c

Pt

Sleak

Eleak

2

2

cST

cP

Eleak = Pleak·tr

Eadia = cE / tr

Etot = Eadia + Eleak

MEMS Resonator ConceptMEMS Resonator Concept

A potential approach for efficiently A potential approach for efficiently driving adiabatic logic transitionsdriving adiabatic logic transitions

UF CONFIDENTIAL – PATENT PENDING

The Power Supply ProblemThe Power Supply Problem• In adiabatics, the factor of reduction in energy In adiabatics, the factor of reduction in energy

dissipated per switching event is limited to (at most) dissipated per switching event is limited to (at most) the the QQ factor of the clock/power supply. factor of the clock/power supply.

QQoveralloverall = ( = (QQlogiclogic−1−1 + + QQsupplysupply

−1−1))−1−1

• Electronic resonator designs typically have low Electronic resonator designs typically have low QQ factors, due to considerations such as:factors, due to considerations such as:– Energy overhead of switching a clamping power MOSFET Energy overhead of switching a clamping power MOSFET

to limit the voltage swing of a sinusoidal to limit the voltage swing of a sinusoidal LCLC oscillator. oscillator. – Low coil count, substrate coupling in integrated inductors.Low coil count, substrate coupling in integrated inductors.– Unfavorable scaling of inductor Unfavorable scaling of inductor QQ with frequency. with frequency.

• Our proposed solution: Our proposed solution: – Use electromechanical resonators instead!Use electromechanical resonators instead!

MEMS (& NEMS) ResonatorsMEMS (& NEMS) Resonators

• State of the art of technology demonstrated in lab:State of the art of technology demonstrated in lab:– Frequencies up to the 100s of MHz, even GHzFrequencies up to the 100s of MHz, even GHz– QQ’s >10,000 in vacuum, several thousand even in air!’s >10,000 in vacuum, several thousand even in air!

• An important emerging technology being exploredAn important emerging technology being exploredfor use in RF filters, for use in RF filters, etc.etc., in , in communicationscommunicationsSoCs, SoCs, e.g.e.g. for for cellphones.cellphones.

U. Mich., poly, U. Mich., poly, ff=156 MHz, =156 MHz, QQ=9,400=9,400

34 µm

Original ConceptOriginal Concept• Imagine a set of charged plates whose horizontal position Imagine a set of charged plates whose horizontal position

oscillates between two sets of interdigitated fixed plates.oscillates between two sets of interdigitated fixed plates.– Structure forms a variable capacitor and voltage divider with the load.Structure forms a variable capacitor and voltage divider with the load.

• Capacitance changes substantially only when crossing border.Capacitance changes substantially only when crossing border.– Produces nearly flat-topped (quasi-trapezoidal) output waveforms. Produces nearly flat-topped (quasi-trapezoidal) output waveforms. – The two output signals have opposite The two output signals have opposite phases (2 of the 4 phases (2 of the 4 φφ’s in 2LAL)’s in 2LAL)

Logicload #1

CL

RL

V1

Logicload #2

CL

RL

tV1

tV2

t

V2

x


MEMS Resonant Power Supply for MEMS Resonant Power Supply for Ultra-Low-Power Adiabatic CircuitsUltra-Low-Power Adiabatic Circuits

• Part of CISE’s Reversible & Quantum Computing groupPart of CISE’s Reversible & Quantum Computing group– Collab. with Huikai Xie (MEMS, ECE dept.)Collab. with Huikai Xie (MEMS, ECE dept.)

• Goal: Goal: Demonstrate orders-of-magnitude improvement in Demonstrate orders-of-magnitude improvement in power-performance efficiency of digital CMOS circuits.power-performance efficiency of digital CMOS circuits.

– Based on reversible logic in adiabatic circuits powered by Based on reversible logic in adiabatic circuits powered by high-quality custom microelectromechanical resonators.high-quality custom microelectromechanical resonators.

• Funding: Funding: $40K seed grant from SRC’s Cross-Disciplinary $40K seed grant from SRC’s Cross-Disciplinary Semiconductor Research (CSR) ProgramSemiconductor Research (CSR) Program

MEMS Designer: Maojiao He

VLSI designer: Krishna Natarajan

A.k.a. The “AdiaMEMS” Project


Key Characteristics of ResonatorKey Characteristics of Resonator• Goal:Goal: Produce a near-ideal trapezoidal output voltage Produce a near-ideal trapezoidal output voltage

waveform resonantly, with high waveform resonantly, with high QQ..• To be optimized with logic: To be optimized with logic: Resonant frequency Resonant frequency ff..• Key resonator figures of merit:Key resonator figures of merit:

– Effective quality factor: Effective quality factor: QQeffeff = = EEtranstrans//EEdissdiss..– Area efficiency: Area efficiency: EEAA = = EEtranstrans//AA..

• Key resonator figures of demerit:Key resonator figures of demerit:– Maximum relative transition slope:Maximum relative transition slope:

ssmaxmax = ( = (dCdC//ddtt))maxmax / (∆ / (∆CCmaxmax/∆/∆tttranstrans))– Fractional capacitance variation:Fractional capacitance variation:

vvCC = ∆ = ∆CCvarvar / ∆ / ∆CCmaxmax ∆Cmax

∆ttrans

∆Cvar


max

dt

dC

First MEMS Technology TriedFirst MEMS Technology Tried• MEMS process donated by Robert Bosch corp.MEMS process donated by Robert Bosch corp.• It is a thin-film technologyIt is a thin-film technology

– We have since moved to a multi-layer, bulk single-We have since moved to a multi-layer, bulk single-crystal process which can be expected to do better.crystal process which can be expected to do better.

• Integrated CMOS/MEMS devices will Integrated CMOS/MEMS devices will eventually be available in this process.eventually be available in this process.– However our initial design was dual-dieHowever our initial design was dual-die

• CMOS side was not mature yet in this processCMOS side was not mature yet in this process

• Minimum etched structure width: Minimum etched structure width: λλ = 0.5 µm = 0.5 µm • Minimum etched gap size: Minimum etched gap size: dd = 0.1 µm = 0.1 µm


Some Early Resonator DesignsSome Early Resonator DesignsBy Ph.D. student Maojiao He, under supervision of Huikai Xie

sensecomb

drivecomb

Close-up of sense fingers

Anotherfingerdesign


acv

acvcV

bV

cVbcp VVV

Actuator

Actuator

Sensor

Sensor

Sensor

Sensor

acvcV

aCsC

rC

bVResonator SchematicUF CONFIDENTIAL – PATENT PENDING

dd s sW

stL

sL sstW

stW

sW

sd

stL)20( dLdL ss

t0

2

4

6

8

10

12

14

-5 -4 -3 -2 -1 0 1 2

Capacitance F1610

t

Four-finger sensor

stLX 8

FCsf161084

Sensor DesignSensor Design

4st sW W d

2sst sW W d

Simulated Output Waveform


(Earlydesignw. thinfingers)

Dissipation in ResonatorDissipation in ResonatorWays to minimize some major sources of dissipation:Ways to minimize some major sources of dissipation:• Air damping:Air damping:

– Vacuum packaging, small size, or optimize airflowVacuum packaging, small size, or optimize airflow• Clamping losses to the substrate:Clamping losses to the substrate:

– Locate support at a nodal point of vibration modeLocate support at a nodal point of vibration mode– Use impedance-mismatched supports to reflect energy backUse impedance-mismatched supports to reflect energy back

• Thermoelastic dissipation (heat flow resulting from Thermoelastic dissipation (heat flow resulting from nonuniform strain):nonuniform strain):– Small sizeSmall size– Use stiff, high thermal conductivity materials (Si, diamond?)Use stiff, high thermal conductivity materials (Si, diamond?)– Utilize modes with uniform compression/expansionUtilize modes with uniform compression/expansion

• Surface loss mechanisms:Surface loss mechanisms:– Avoid layered structures (thin-film interfaces) at surfacesAvoid layered structures (thin-film interfaces) at surfaces

• Intrinsic material losses:Intrinsic material losses:– Prefer single-crystal materialsPrefer single-crystal materials

Status / Plans for Near FutureStatus / Plans for Near Future• Improved resonator designs afforded by a suitably Improved resonator designs afforded by a suitably

modified post-CMOS process flow are being developed.modified post-CMOS process flow are being developed.– I will briefly review some aspects of the new process.I will briefly review some aspects of the new process.

• A small prototype resonator design was taped out in a A small prototype resonator design was taped out in a post-CMOS MEMS process (TSMC .35)post-CMOS MEMS process (TSMC .35)– Parts were just received last week; are presently being etched.Parts were just received last week; are presently being etched.

• Process donation has been obtained from MOSIS for Process donation has been obtained from MOSIS for fabricating a integrated CMOS/MEMS test chip (~$20k).fabricating a integrated CMOS/MEMS test chip (~$20k).– Resonator driving a simple 2LAL shift register or adder pipelineResonator driving a simple 2LAL shift register or adder pipeline– Tape-out for this chip is scheduled for July 26.Tape-out for this chip is scheduled for July 26.

• Test the various parts separately, & together.Test the various parts separately, & together.– Characterize power dissipation using sensitive calorimetry Characterize power dissipation using sensitive calorimetry

techniques.techniques.

Post CMOS-MEMS Process Post CMOS-MEMS Process (DRIE)(DRIE)

metal-1

metal-2metal-3(a) Backside

etch

CMOS-region

Single-crystal Si (SCS) membrane

poly-Si

oxide

(b) Oxide etch

STS: 12-sec etching130-sccm SF6, 13-sccm O2, 23 mT, 600 W coil power, 12 W platen power;8-sec passivation85-sccm C4F8, 12 mT, 600 W coil power, 0 platen power.

PlasmaTherm-790: 22.5-sccm CHF3, 16-sccm O2, 100 W, 125 mT for 125 minutes and then 100 mT for 10 minutes.

Post CMOS-MEMS Process Post CMOS-MEMS Process (DRIE)(DRIE)

(c) Deep Si etch

CMOS layer

STS: same as Step (a).

Flat structure

(d) Si undercut SCS layer

(20~100m)

Thin-film structure

STS: 130-sccm SF6, 13-sccm O2, 23 mT, 600 W coil power, and 0 platen power.

(a)

(b)

H. Xie et al, J. MEMS, Vol.11, no.2, 2002

Electrical Isolation of Silicon

Electrically isolated silicon island

Electrically isolated comb fingers

Using n-well to improve undercut yield

n-wellAl

Oxide

Serpentine spring

Comb drive

Proof mass

Front-side view

Back-side view

DRIE CMOS-MEMS Resonators

Resonators

150 kHz

Post-TSMC35 AdiaMEMS ResonatorPost-TSMC35 AdiaMEMS ResonatorUF CONFIDENTIAL – PATENT PENDING

Drivecomb

Flexarm

Sensecomb

Taped out April ‘04

Close-Up View, Drive/Sense CombsClose-Up View, Drive/Sense CombsUF CONFIDENTIAL – PATENT PENDING

Side View, Showing Si UndercutSide View, Showing Si UndercutUF CONFIDENTIAL – PATENT PENDING

New Comb Finger Shape New Comb Finger Shape ConceptsConcepts

For improved waveform shape and For improved waveform shape and area efficiencyarea efficiency


Minimumthicknessto minimizeundesiredarm-loadcapacitance

Fixed plate

Movingplate

Moving plate support arm/electrode

Moving Plate Range of Motion

Fixedplate

(cut awayview)

Maximum vertical (z)

thickness for maximum

overlap capacitance

per planar area

Minimum gap sizefor maximum overlapcapacitance per-area

Siliconsubstratematerial

Metal/oxide layers

Fixedplate

Colorkey:

New Comb Finger Shape INew Comb Finger Shape I

Note that the new configuration increases the magnitude of the capacitance variation whilereducing the magnitude of departures fromthe desired trapezoidal wave shape.

Load electrode


New Comb Finger Shape IINew Comb Finger Shape II

Fixed plate


Movingplate

Moving Plate Range of Motion

Fixedplate

(cut awayview)

Maximum vertical (z)

thickness for maximum

overlap capacitance

per planar area



Metal/oxide layers

Fixedplate

Colorkey:

Note that the new configuration increases the magnitude of the capacitance variation whilereducing the magnitude of departures fromthe desired trapezoidal wave shape. In addition, the structures are made of silicon


Fixedplate

Noteseparationto reduceundesiredarm-loadcapacitanceHigh vertical

(z) thickness for large overlap

capacitance per planar

area


Metal/oxide layers

Colorkey:

New Comb Finger Shape IIINew Comb Finger Shape III

Note that the new configuration increases the magnitude of the capacitance variation whilereducing the magnitude of departures fromthe desired trapezoidal wave shape.


Movingplate


Moving Plate Range of MotionFixedplate

Load electrode


Movingplate

Moving metal plate support arm/electrode

New Comb Finger Shape IVNew Comb Finger Shape IV

Range of Motion

Arm anchored to nodal points of fixed-fixed beam flexures,located a little ways away, in both directions (for symmetry)

Phase 0° electrode Phase 180° electrode

θ0° 360°

C(θ) C(θ)

θ0° 360°

Or, if we can do the structure on the previous slide, then why not this one too? Or, will there be a problem etching the intervening silicon out from in between the metal/oxide layers and the bulk substrate?

… Repeatinterdigitated

structurearbitrarily many

times along y axis,all anchored to the

same flexure

x

yz


Fixedplate

New Comb Finger Shape VNew Comb Finger Shape V

Fixedplate Moving

plateFixedplate

In this design, the plates are attached directly to a supprt arm which extends in the y direction instead of x. This arm can be the flexure, or it can be attached to a surrounding frame anchored to a flexure. Note that in the initial position, at all points, we only need etch from top and/or bottom, with no undercuts. Also, the flexure can be single-crystal Si.

Fixedplate


Requires accurate,variable-depthbackside etch(not presentlyavailable).


New finger: One Candidate LayoutNew finger: One Candidate Layout

New finger simulation resultsNew finger simulation results

0

1

2

3

4

5

6

7

8

0 1 2 3 4 5 6 7 8 9

0

1

2

3

4

5

6

7

8

0 2 4 6 8 10 12


Cadence simulation resultsCadence simulation results

Work by AdiaMEMS project students:Work by AdiaMEMS project students:Krishna NatarajanKrishna Natarajan

Venkiteswaran AnantharamVenkiteswaran Anantharam(UF ECE Dept., under supervision of (UF ECE Dept., under supervision of

Dr. Frank, CISE/ECE)Dr. Frank, CISE/ECE)

2LAL 8-stage

circular shift register

Shift register layout, in progressShift register layout, in progress

Pulse propagation in 8-stage circuitPulse propagation in 8-stage circuit

Simulation Results from CadenceSimulation Results from CadenceAssumptions & caveats:•Assumes ideal trapezoidal power/clock waveform.• Minimum-sized devices, 2λ×3λ * .18 µm (L) × .24 µm (W)• nFET data is shown * pFETs data is very similar• Various body biases tried * Higher Vth suppresses leakage • Room temperature operation.• Interconnect parasitics have not yet been included.• Activity factor (transitions per device-cycle) is 1 for CMOS, 0.5 for 2LAL in this graph.• Hardware overhead from fully- adiabatic design style is not yet reflected * ≥2× transistor-tick hardware overhead in known reversible CMOS design styles

1 nJ

100 pJ10 pJ

1 pJ

100 fJ

10 fJ

1 fJ

100 aJ

10 aJ

1 aJ

100 zJ10 zJ

1 zJ

kT ln 2

1 eV

Standard CMOS

2V1V0.5V

0.25V

2LAL 1.8-2.0V

Ene

rgy dissipated per nF

ET

per cycle

>100× faster @ 1 pW/T<

.01×

th

e p

ower

@

1 M

Hz

100 yJ

O(log O(log nn)-time carry-skip adder)-time carry-skip adder

(8 bit segment shown)(8 bit segment shown)

Pms Gls Pls

CinGCout

P

P

Pms Gls Pls

CinGCout

P

MS LS

LS

Pms Gls Pls

G

Pms Gls Pls

G

P

P

Pms Gls Pls

CinGCout

P

MS LS

MS

Pms Gls Pls

G

Pms Gls Pls

CinGCout

P

LS

GCoutCin

S A B

P

G Cin

S A B

P

GCoutCin

S A B

P

S A B

P

GCoutCin

S A B

P

S A B

P

GCoutCin

S A B

P

S A B

P

G CinG CinG Cin

With this structure, we can do a2n-bit add in 2(n+1) logic levels

→ 4(n+1) reversible ticks→ n+1 clock cycles.

Hardwareoverhead is<2× regular

ripple-carry.

1st ca

rry tic

k

2nd carry tick3rd carry tick4th carry tick

Adder Schematic – High 16 BitsAdder Schematic – High 16 Bits

32-bit Adder Simulation Results32-bit Adder Simulation Results

1V CMOS

0.5V CMOS

1V CMOS

0.5V CMOS

2V 2LA

L, Vsb =1V

2V 2LAL, Vsb =1V

(All results normalized to a throughput level of 1 add/cycle)

20x better perf.@ 3 nW/adder

Plenty of Room forPlenty of Room forDevice ImprovementDevice Improvement• Recall, Recall, irreversibleirreversible device device

technology has technology has at mostat most ~3-4 orders of magnitude ~3-4 orders of magnitude of power-performance of power-performance improvements remaining.improvements remaining.– And then, the firm And then, the firm kTkT ln 2 ln 2

limit is encountered.limit is encountered.• But, a wide variety of But, a wide variety of

proposed proposed reversiblereversible device device technologies have been technologies have been analyzed by physicists.analyzed by physicists.– With theoretical power-With theoretical power-

performance up to performance up to 10-12 10-12 orders of magnitudeorders of magnitude better better than today’s CMOS!than today’s CMOS!

• Ultimate limits are unclear.Ultimate limits are unclear.

.18µm CMOS.18µm

2LAL

k(300 K) ln 2

Variousreversibledevice proposals

Power per device, vs. frequency

A Potential Scaling Scenario for A Potential Scaling Scenario for Reversible Computing TechnologyReversible Computing Technology

• Assume Assume energy coefficientenergy coefficient (energy diss. / freq.) (energy diss. / freq.) of reversible technology continues declining at of reversible technology continues declining at historical rate of 16historical rate of 16× / 3 years, through 2020.× / 3 years, through 2020.– For adiabatic CMOS, For adiabatic CMOS, ccEE = = CVCV22RCRC = = CC22VV22RR..

• This has been going as ~This has been going as ~44 under constant-field scaling. under constant-field scaling.– But, requires new devices after CMOS scaling stops.But, requires new devices after CMOS scaling stops.

• However, many candidates are waiting in the wings…However, many candidates are waiting in the wings…

• Assume number of affordable Assume number of affordable layers layers of active of active circuitry per chip (or per package, circuitry per chip (or per package, e.g.e.g., stacked , stacked dies) doubles every 3 years, through 2020.dies) doubles every 3 years, through 2020.– Competitive pressures will tend to ensure this will Competitive pressures will tend to ensure this will

happen, esp. if device-size scaling stops, as assumed.happen, esp. if device-size scaling stops, as assumed.

Make same assumptions as previously, except:

Result of ScenarioResult of ScenarioA Potential Scenario for CMOS vs. Reversible Raw Affordable Chip Performance

1.00E+17

1.00E+18

1.00E+19

1.00E+20

1.00E+21

1.00E+22

1.00E+23

2004 2006 2008 2010 2012 2014 2016 2018 2020

Year

Dev

ice-

op

s/se

con

d p

er a

ffo

rdab

le 1

00W

ch

ip

CMOS

Reversible

Note that by 2020, there could be a factor of 20,000× difference in rawperformance per 100W package. (E.g., a 100× overhead factor from reversible design could be absorbed while still showing a 200× boost in performance!)

40 layers, ea. w.8 billion activedevices,freq. 180 GHz,0.4 kT dissip.per device-op

Microsoft Excel Worksheete.g. 1 billion devices actively switching at

3.3 GHz, ~7,000 kT dissip. per device-op

ConclusionsConclusions• Standard CMOS is approaching imminent limits on Standard CMOS is approaching imminent limits on

raw performance per unit power consumed.raw performance per unit power consumed.– Due to various lower bounds on the energy dissipated by Due to various lower bounds on the energy dissipated by

conventional irreversible switching.conventional irreversible switching.• OnlyOnly mostly-reversible logic architectures have the mostly-reversible logic architectures have the

potential to bypass potential to bypass allall of the known energy limits! of the known energy limits!– Via migration to an increasingly adiabatic, ballistic mode of Via migration to an increasingly adiabatic, ballistic mode of

operation, and an increasingly reversible logic design.operation, and an increasingly reversible logic design.• With increasingly high-With increasingly high-QQ energy transfers during logic. energy transfers during logic.

• UF’s AdiaMEMS project is refining techniques for UF’s AdiaMEMS project is refining techniques for near-term reversible computing in CMOS/MEMS.near-term reversible computing in CMOS/MEMS.– Potentially viable technology for ultra-low-power products.Potentially viable technology for ultra-low-power products.

• Long-term, digital circuit architectures that are Long-term, digital circuit architectures that are designed in a mostly-reversible logic style will be the designed in a mostly-reversible logic style will be the onlyonly ones that can be easily ported to future ultra-high- ones that can be easily ported to future ultra-high-performance reversible logic-device nanotechnologies.performance reversible logic-device nanotechnologies.– We need to start paying more attention to these issues!We need to start paying more attention to these issues!

AdiaMEMS Project Members – Thanks!AdiaMEMS Project Members – Thanks!

Left toRight:Venki,Mike,Maojiao,Krishna,& Huikai

Reversible Computing A Brief Introduction Dr. Michael P. Frank [email protected] Dept. of Computer &...

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Transcript of Reversible Computing A Brief Introduction Dr. Michael P. Frank [email protected] Dept. of Computer &...